JP3392688B2 - Elevator control device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an elevator control device, and more particularly to a data communication method in elevator control.

[0002]

2. Description of the Related Art Elevators are being installed not only in middle- and high-rise buildings but also in small-scale buildings and private houses as a vertical transportation system in buildings. In recent years, the number of installed units has increased dramatically, and the number of units installed in Japan alone exceeds 100,000.

Further, due to the progress of semiconductor technology, most elevator control devices have a structure in which a plurality of microcomputers (microprocessors) are used, and the performance is being improved and the control device is being downsized. In such an apparatus, a plurality of microcomputers are diversified, for example, elevator operation control, motor control, elevator car processing, elevator landing processing, display devices installed in elevator cars and landings, and elevator monitoring devices. It is designed to perform distributed processing by appropriately dividing functions according to the configuration.

Although these microcomputer circuits independently perform dedicated processing, they naturally operate as an elevator by exchanging data with a microcomputer that performs main control.

As a data communication method, a method of providing a common bus line between microcomputer circuits or 2
Dual port RA between two microcomputer circuits
There are a method of communicating by using M (hereinafter referred to as “DP-RAM”), a method of communicating between two central processing elements (hereinafter referred to as CPU) by serial transmission, and the like.

FIG. 6 is a block diagram showing a part of the device configuration of an elevator control device in which a common bus line, that is, a common bus is provided between microcomputer circuits to perform communication.

The operation control unit 1 shown in FIG. 1 includes a CPU (A) 2 as a microprocessor and the CPU (A) 2
To the program storage unit 3 (nonvolatile read-only storage device EP-ROM
Etc.), data storage unit 4 (volatile read / write storage device R
AM, etc.), setting data storage unit 5 (electrically erasable RO
EE-ROM which is M), a call control unit 6, a car position control unit 7, and the like.

These storage units and control units 3 to 7 are controlled on the local bus A by about 30 signals such as addresses and data output by the CPU (A) 2 and control signals thereof. It has become.

On the other hand, in the motor control section shown in FIG. 8, a CPU which is a core for controlling a motor (not shown)
On the local bus B having the (B) 9 and controlled by the CPU (B) 9, a program storage unit 10 for storing the processing procedure of the CPU (B) 9, a storage unit 11 for storing data, Setting data storage unit 1 that stores building unit data
2. The speed controller 13 is connected.

Further, the CPU (A) 2 and the CPU (B) 9
Are connected to a common bus 16 which is a common bus line via common bus control units 14 and 15, respectively. The common bus 16 includes an input / output unit 17 including a digital input circuit and a digital output circuit, and , R
A common storage unit 18 composed of AM or the like is connected. Data is exchanged between the CPU (A) 2 and the CPU (B) 9 via the common bus 16 and the common storage unit 18.

By the way, in recent years, not only the circuit for the elevator operation processing as described above, but also a circuit for exclusively managing the maintenance of the elevator is required.

That is, an elevator is a device for transporting people by automatic operation for 24 hours, but its inspection is performed on a monthly basis. Such a device is unique and requires extremely high reliability. Therefore, it is necessary to construct a system that does not miss any abnormality.

Similarly, when adjusting the elevator at the time of installing the elevator, it is possible to shorten the installation time by using the information for maintenance and check, and shorten the failure recovery time by the function of detecting an abnormality. It is becoming popular.

By the way, in the above-mentioned method of performing communication between CPUs by providing the common bus 16, since the data input time interval is determined by the performance of the CPU that handles it, the elevator maintenance and management cannot be performed sufficiently. There is a risk.

That is, a CPU for controlling the operation
In (A) 2, if the data is read at intervals of about 100 ms, sufficient operation control processing can be performed. But this CP
When performing maintenance management of an elevator apparatus using U (A) 2, in order to perform fine management, it is necessary to take in data at a sampling interval of 10 ms.

In order to deal with this, there is also a method of setting the data sampling interval of the CPU (A) 2 to 10 ms, but this may make it impossible to perform other processing necessary for operation control due to the load. is there.

Therefore, as shown in FIG. 6, a maintenance management unit 20 is connected to the common bus 16 and maintenance management processing such as abnormality detection of an elevator is performed using the CPU (C) 21 which is a maintenance management microprocessor. There is a dedicated method. The CPU (C) 21 uses the common bus 1 via the local bus C and the common bus control unit 22.
Connected to 6. Also, on this local bus C,
Peripheral circuits such as a program storage unit 23 and a data storage unit 24 controlled by the CPU (C) 21 are provided. The CPU (C) 21 takes in the data input to the input / output unit 17 and the like via the common bus 16 and the local bus C and performs operation maintenance, and stores basic information such as the number of times of operation and time of the elevator. Besides management,
It is necessary to have a function to perform preventive maintenance if there is no prediction of abnormality during driving.

However, in such a configuration, there is a problem that the load applied to the common bus 16 becomes heavy. That is, the common bus 16 has a plurality of CPUs.
Since it is a common circuit of (A) 2 to (C) 21, one C
Other CPUs may have to wait while the PU is accessing its common bus 16. As a result, there is a problem in that the processing time of the entire elevator control device becomes long and the operation of the elevator is affected.

On the other hand, FIG. 7 shows the DP as a common storage unit.
FIG. 7 is a block diagram showing a control device for an elevator configured to perform communication using RAMs 25 and 26. Note that FIG.
Constituent elements similar to those are denoted by the same reference numerals, and illustration of constituent elements not related to data communication is omitted.

27 is a digital input circuit as a peripheral circuit of the CPU (A) 2. The digital input circuit 27 has a parallel data input section 28 which receives an input signal and an input data holding section 29 which receives data from the parallel data input section and outputs it to the local bus A.

The input data holding unit 29 is a CPU
(A) The I / O select signal from (2) is received, and the data communication timing is set. In this control device, the data sampling interval of the CPU (A) 2 for operation control is about 100 ms as described above, and the sampled input signal is described in the DP-RAMs 25 and 29 so that the CPU (B ) 9 and CPU (C) 21
Can know the contents of its input signal.

However, even with such a structure, after all,
CPU (C) 21 for maintenance and inspection is a CPU for operation control
Since the data held by (A) 2 is received via the DP-RAM 26, the data sampling interval of the CPU (A) 2 must be shortened in order to obtain the data of the required sampling interval. No, this CP
There is a problem that the load on U (A) 2 becomes heavy.

As another communication method different from the above, there is a method in which CPUs are directly connected to each other to perform serial transmission as described above. In this method, however, when a CPU for maintenance is newly provided, Since it is necessary to separately provide a dedicated serial transmission circuit, there is a drawback that the load of the CPU required for serial transmission increases.

[0024]

As described above, when the elevator control device communicates data with a plurality of processors (CPUs), the data sampling interval required by the processor used for maintenance and inspection is This is sometimes shorter than the data sampling interval of the processor, and there is a disadvantage that the load of the entire system increases when trying to cope with this.

The present invention has been made in view of the above circumstances, and a signal for input / output to / from a peripheral circuit of another processor is maintained and maintained without affecting the operation of the entire control device. It is an object of the present invention to provide a control device for an elevator that can be processed by.

[0026]

According to the present invention, at least one or more processors are used in an elevator control apparatus which uses a plurality of processors and which is provided with a common circuit between the processors to communicate data and control the elevator. The peripheral circuit of the processor is the peripheral circuit of the processor.
Connected to a storage unit and access this storage unit regularly
Means for serially synchronizing the contents of the storage unit with a clock.
Data and then transfer it to the maintenance processor.
The has a control device for an elevator provided with a circuit for the maintenance management processor can be controlled independently of those of the processor.

[0027]

Further, the present invention provides a control device of the elevator further provided an abnormality detection unit for detecting an abnormality of the corresponding processor, the abnormality detecting unit disconnects the data transmission to the peripheral circuit by the said processor ,
It is preferable to have a means for causing the transmission of data to the peripheral circuit from the circuit in which the maintenance management processor can be controlled independently of the processor.

[0029]

[0030]

DETAILED DESCRIPTION OF THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. First, a first embodiment will be described with reference to FIG. This FIG. 1 relates to a control device for performing communication between CPUs via a common bus, similarly to the control device shown in FIG. 6 in the section of the conventional example. Note that the same components as those described with reference to FIG. 6 in the section of the conventional example are denoted by the same reference numerals, and of the components shown in FIG. Illustration is omitted.

In this embodiment, an input circuit (input / output circuit) 31 shown in the drawing is connected to an auxiliary processing section 32 provided on the local bus A of the CPU (A) 2 and a CPU for maintenance and inspection ( C) A data processing unit 33 that communicates with the auxiliary processing unit 32 and a data processing procedure storage unit 34 that stores the processing procedure of the data on the local bus C of 21.
Is provided.

According to this structure, the auxiliary processing section 32 can be controlled by both the CPU (A) 2 and the CPU (C) 21. That is, the auxiliary processing section 32 outputs the input signal from the input circuit 31 to the local bus A for the CPU (A) 2 by receiving the I / O select signal from the CPU (A) 2, and At the same time, an I / O signal which is a signal for the CPU (C) 21 is sent to the data processing unit 33 on the local bus C. At this time, the CPU (A) 2 is the CPU (C) 2
I corresponding to the data sampling interval required for processing 1
The / O signal is generated.

The data processing unit 33 includes the UPU.
(C) It operates as a device on the local bus C of 21 and reads the input signal from the I / O signal 24 which is a parallel signal from the auxiliary processing section 32.

Next, the reading of data in this control device will be described with reference to the timing chart shown in FIG. FIG. 2A shows data α and data β input to the input / output unit. FIG. 2B shows a CPU
2A shows the timing of data sampling of (A) 2, whereby the data read by the CPU (A) 2 becomes data α'and data β'shown in FIG. 2C, respectively.

Further, FIG. 2D shows the CPU (C) 21.
The data sampling timing of
As a result, the CPU (C) is transferred via the data processing unit 33.
The data read in 21 becomes the data α ″ and the data β ″ shown in FIG.

As shown in this figure, the CPU (C) 21
Can read the data more accurately. That is, the CPU (A) 2 reads data at a data sampling timing (for example, 100 ms interval) necessary and sufficient for operation control. On the other hand, the CPU (C) 21 is for performing maintenance management of the elevator, detects abnormal changes in the signals, and prepares for a serious accident in the future, and therefore follows not only normal changes in the signals but also short changes in intervals. There is a need. Therefore, data is read at a data sampling timing (for example, 10 ms) shorter than that of the CPU (A) 2.

According to such a configuration, the CPU (C) 2
1 can receive and sample the input signal without passing through the common bus 16, and therefore the CPU (A)
2 without affecting the operation of the common bus 1
Necessary processing can be performed without increasing the load of 6. Therefore, according to the elevator control device of the first embodiment, it is possible to realize highly accurate maintenance management control without affecting the elevator control.

Next, a second embodiment of the present invention will be described with reference to FIG. The control device shown in FIG. 3 performs communication between the CPUs via the DP-RAMs 25 and 26, as in the conventional device shown in FIG. The same components as those described with reference to FIGS. 6 and 7 in the section of the conventional example are designated by the same reference numerals, and the components shown in FIG. 7 are not related to data communication. Illustration of components is omitted.

Reference numeral 28 in this figure denotes a parallel data input section as an input circuit, which receives an input signal composed of a digital signal or an analog signal from the outside. The data received by the parallel data input unit 18 is sent to the input data holding unit 36, which is a device on the local bus A of the CPU (A) 2, and the shift register indicated by 37 in the figure.

Further, the input data holding unit 36 stores the CP
The input signal from the parallel data input unit 28 is sent to the CPU (A) 2 by the I / O select signal from the U (A) 2.
It is designed to be output on the local bus A of. The I / O select signal corresponds to the data sampling interval of the CPU (A) 2, unlike the first embodiment.

The shift register 37 is a CPU
(C) 21 is connected to the data processing unit 39, which is a device on the local bus C, and the input signal is a serial signal at the data sampling interval of the CPU (C) 21 based on the clock signal of the CPU (C) 21. And output to the data processing unit 39. Further, the data processing unit 39 converts the received serial signal and outputs it on the local bus C of the CPU (C) 21.

On the local bus C of the CPU (C) 21, there is provided a data processing procedure storage section 40 for storing the processing procedure of the data. According to such a configuration, the maintenance management CPU (C) 21 is
From (A) 2, the state of the input signal can be sampled regardless of the I / O select signal 20. Therefore, the first
As compared with the above embodiment, there is an effect that the load on the CPU (A) 2 can be further reduced.

Compared with the first embodiment of the present invention, the shift register 37 may be used although a processing delay may occur because the input signal is converted into a serial signal and transmitted to the CPU (C) 21. Since the configuration is different, it can be implemented with only about three signals, and the load on the CPU (C) 21 is reduced.

Further, according to such a configuration, there is an effect that the influence of noise from the inverter circuit for driving the motor, which is a problem in elevator control, can be reduced. Next, a third embodiment of the present invention will be described with reference to FIG. Note that the elevator control device according to the present embodiment uses the DP-R communication to communicate between the CPUs as in the second embodiment.
This is done via the AMs 25 and 26. The same components as those in the second embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

In this figure, 41 is a driver circuit as a digital output circuit. This elevator controller normally controls C in elevator control.
The CPU (C) 21 for maintenance management backs up the driver circuit 41 that the PU (A) 2 controls via the output data holding unit 42 when the CPU (A) 2 becomes abnormal. It is composed.

Reference numeral 43 in the drawing denotes a CPU abnormality detecting section for detecting an abnormality of the CPU (A) 2. The CPU abnormality detection unit 43 is a device on the local bus A of the CPU (A) 2 and is composed of a circuit generally called a watchdog. The CPU abnormality detection unit 43 is the CPU
(A) When it is detected that an abnormality has occurred in (2), a command is issued to the output data holding section 42 to prohibit the output of a signal to the driver circuit 41. On the other hand, the CPU abnormality detection unit 43 issues a command to the auxiliary processing unit indicated by 44 in the figure to permit output of a signal to the driver circuit 41.

This auxiliary processing section 44 is provided in the CPU (C) 21.
The data processing unit 39 connected to the local bus C of
From the driver circuit 41.
It has the function of sending to.

In such a configuration, the CPU
If an abnormality is detected in (A) 2, the CPU (C) 21 can know the fact via the DP-RAM 26. Based on this, the CPU (C) 21
The PU (A) 2 is backed up and the data required for control is sent to the auxiliary processing unit 44 via the data processing unit 39. The auxiliary processing unit 44 outputs the signal received from the auxiliary processing unit 44 to the driver circuit 41 based on the signal transmission permission command from the CPU abnormality detection unit 43.

According to this structure, the following effects can be obtained. That is, the driver circuit 41 as a digital output circuit is a circuit that cannot be shared, unlike the input circuits described in the first and second embodiments, and if the CPU (A) 2 becomes abnormal, this CPU (A) The digital output section controlled by 2 is reset and the other CPU
It becomes impossible to control from.

However, according to the configuration of this embodiment, even if an abnormality occurs in the CPU (A) 2,
The driver circuit 41 is backed up by the CPU (C) 21.
Can be controlled. As a result, I / O unit
It is not necessary to have PU (A) and (C) units, and CPUs of each other, such as when communicating via the common bus 16.
There is an effect that necessary processing can be performed without delaying the operation time of.

Further, according to such a configuration, since only one digital output circuit (driver circuit 41), which is a common part, needs to be provided, the area of the substrate required for configuring this control device is small. Therefore, the manufacturing cost can be reduced.

Further, the circuit that has been conventionally backed up after once being converted into a contact of an electromagnetic relay or the like becomes unnecessary, and the cost can be reduced. Next, a fourth embodiment of the present invention will be described with reference to FIG.

The fourth embodiment is a CP for operation control.
E which is the setting data storage unit 5 controlled by U (A) 2
The E-ROM is shared by a plurality of CPUs. Generally, this EE-ROM 5 is necessary for operation control, and is almost unnecessary for the CPU (B) 9 for motor control.

However, in the maintenance CPU (C) 21,
This EE-RO is used to maintain and manage the contents of the EE-ROM 5 when the contents of the EE-ROM 5 are changed locally, such as speed adjustment
It is necessary to read the setting data stored in M5. However, in the conventional configuration shown in FIG. 6, this EE-R
The contents of the OM 5 cannot be directly read by the CPU (C) 21 and must be received via the common bus 16. Therefore, as described above, the CPU for operation control
(A) 2 and the common bus 16 may be burdened.

As a configuration for solving such a problem, in the present embodiment, the setting data storage unit 5 is provided with an auxiliary processing unit 46 for transferring the contents of the storage unit 5 to the CPU (C) 21. It is connected.

The CPU (A) 2 uses the procedure stored in the common data processing procedure storage unit 47 to set the setting data storage unit 5.
Regularly access all areas of. As a result, all the data in the setting data storage unit 5 is output to the local bus A. At this time, the auxiliary processing unit 46 converts the data into a serial signal by a shift register having a built-in data, and C
The data is transferred to the data processing unit 39 provided on the local bus C of the PU (C) 21. This transfer is for this CPU (C)
It is performed in synchronization with the internal clock of. This data processing unit
39 , after converting the serial signal into parallel data, CP
It is sent to the local bus C of the U (C) 21.

In the present invention, the signals of the CPU (A) 2 are generated in order according to the processing procedure stored in the common data processing procedure storage unit 47. This makes the CPU
(A) 2 only needs to increase the load to execute its own processing collectively.

For example, the size of the setting data storage unit 4 is 4K.
If it is a byte, a means for generating an address of 4 Kbytes is programmed as a common data processing procedure. This processing step only increases the load by about 10 ms, and compared with the above-mentioned I / O transfer, EE-RO.
This is a sufficient M check interval.

Although it is necessary to complete the transmission of the serial signal within one memory cycle, there is no problem in consideration of noise resistance because it is data transfer within the same substrate. Also,
This function itself can be implemented by using the bus line as a common bus. However, with the configuration of the present invention, the maintenance CPU (C) 21 only reads the EE-ROM 5, so the common bus is used. In this case, the influence of erroneous writing is eliminated and a stable maintenance function can be realized.

The above description is not limited to the EE-ROM which is an electrically erasable storage device, but an electrically batch erasable storage device (flash ROM), a battery-backed RAM, and the like. Can also be easily implemented.

Although the description has been given of the method of transmitting data to the other CPU by the shift register using the serial signal, it goes without saying that an asynchronous serial signal, another serial transmission means or a parallel signal may be used.

Further, in the fourth embodiment, the CPU
(A) The example in which 2 issues an address has been described, but DM
A process such as A that is not directly executed by the CPU is sufficient.
Further, other components can be variously modified without changing the gist of the present invention.

[0063]

As described above, according to the present invention, at least an elevator control apparatus that uses a plurality of processors and provides a common circuit between the processors to communicate data and control the elevator is provided. For the peripheral circuits of one or more processors, the processor for maintenance management is provided with a circuit that can be controlled independently of the processor, so that when the data for maintenance management is sampled, the load on the processor and It is possible to effectively prevent the load of the common bus between the processors from increasing and to exert the maintenance management function well.

[Brief description of drawings]

FIG. 1 is a block diagram showing an elevator controller according to a first embodiment of the present invention.

FIG. 2 is a time chart which similarly illustrates sampling of data by the elevator control device.

FIG. 3 is a block diagram showing an elevator control device according to a second embodiment.

FIG. 4 is a block diagram showing an elevator controller according to a third embodiment.

FIG. 5 is a block diagram showing an elevator control device according to a fourth embodiment.

FIG. 6 is a block diagram showing a conventional elevator control device.

FIG. 7 is a block diagram showing a conventional elevator control device.

[Explanation of symbols]

2 ... CPU (A) for operation control (the relevant processor) 21 ... CPU (C) for maintenance management (processor for maintenance management) 31 ... Input circuit (peripheral circuit) 32 ... Auxiliary processing unit (processor for maintenance management) 37 ... Shift register (circuit that maintenance processor can independently control) 41 ... Driver circuit (peripheral circuit, output circuit) 43 ... CPU abnormality detection unit

Claims (2)

(57) [Claims] 1. An elevator control apparatus using a plurality of processors, wherein a common circuit is provided between the processors to communicate data and control an elevator, wherein at least one peripheral circuit of the processor is provided with Connected to the memory that is the peripheral circuit of the processor.
And the above-mentioned means for accessing this storage section regularly.
Convert the contents of the memory to serial data in synchronization with the clock,
Maintenance management and a means for transferring to the processor, the control device for an elevator, characterized in that the <br/> maintenance management processor is provided with a circuit that can be controlled independently of those of the processor. 2. The elevator control apparatus according to claim 1, further comprising an abnormality detection unit that detects an abnormality of the processor.
Only, the abnormality detection section, the peripheral by the said processor
Disconnect the data transmission to the circuit and
From the circuit that the controller can control independently of the processor.
An elevator control device comprising means for transmitting data to peripheral circuits .