JP3392632B2 - Pilot cancel signal generation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pilot cancel signal generation circuit whose output level can be adjusted according to a control signal from an external circuit.

[0002]

2. Description of the Related Art FIG. 2 is a diagram showing a conventional stereo demodulation circuit. The IF signal generated from the preceding circuit is amplified by the IF amplifier circuit (1) and FM-detected by the FM detection circuit (2), and a stereo composite signal is generated at its output end. The stereo composite signal, after the pulse noise in the signal is removed by the noise removal circuit (3),
It is applied to the LPF (4) and the sub-signal decoder (5) which form a stereo demodulation circuit. The output signal of the FM detection circuit (2) is applied to the pilot signal detection circuit (6). The pilot signal detection circuit (6) detects the presence or absence of a pilot signal, extracts the pilot signal from the stereo composite signal, and transmits it to the phase comparison circuit (7) at the next stage. The pilot signal is phase-compared with the reproduced pilot signal in the phase comparison circuit (7), and a control signal corresponding to the phase comparison result is generated from the LPF (8). An output signal of 76 KHz is generated from the VCO (9) according to the control signal, divided by the first frequency dividing circuit (10) to reproduce the subcarrier signal, and further divided by the second frequency dividing circuit (11). And the pilot signal is reproduced. Second frequency divider circuit (1
The reproduction pilot signal of 1) is applied to the phase comparison circuit (7). Phase comparator circuit (7) to second frequency divider circuit (11)
Composes a PLL circuit, and the sub-carrier signal synchronized with the stereo composite signal is reproduced by the PLL circuit.

The reproduced subcarrier signal is applied to the subsignal decoder (5) as a switching signal. In the sub signal decoder (5), the sub signal (LR) is obtained by multiplying the stereo composite signal by the switching signal. In addition, in the LPF (4), the main signal (L +
Only R) passes through and the main signal is extracted. The main signal (L + R) and the sub signal (LR) are matrixed by a matrix circuit (12), and a stereo L signal and a stereo R signal are generated at an output terminal of the matrix circuit (12).

Further, the second frequency dividing circuit (11) has a signal of 19 KHz which is applied to the phase comparison circuit (7) and which is shifted by 90 degrees, as well as 0 degree and 0 degree as shown in FIGS. A 19 KHz signal shifted by 180 degrees is applied to the pilot cancel signal generation circuit (13). In addition, the first frequency dividing circuit (1
0) is applied to the second frequency dividing circuit (11) in FIG.
In addition to the 38 KHz signal as shown in FIG.
A 38 KHz signal with a deviation is applied to the pilot cancel signal generation circuit (13). During stereo reception, when a pilot signal is detected by the pilot signal detection circuit (6), a signal indicating pilot signal detection is applied to the pilot cancellation signal generation circuit (13), and the first and second frequency dividing circuits (10) And FIG. 3 based on the output signals of (11).
A pilot cancel signal as shown in (d) is generated. The output signal of the pilot cancellation signal generation circuit (13) is generated in the current mode, converted into a voltage by the current-voltage conversion circuit (14), and then applied to the noise removal circuit (3). The waveform of the noise canceling pilot canceling signal is generated by the Walsh function. By using such a function, it is possible to reduce the generation of harmonics.

[0005]

When the circuit of FIG. 2 is integrated into an IC, the current-voltage conversion circuit (14) of FIG. 2 becomes an external circuit. In the case of IC, the pilot cancel signal generation circuit (1
Since the output signal level of 3) varies, the cancellation characteristic of the pilot signal in the noise removal circuit (3) deteriorates, and as a result, the separation characteristic of the stereo demodulation circuit deteriorates. Therefore, the current-voltage conversion circuit (14) is made a variable resistance, and the resistance value of the variable resistance is changed to adjust the output signal level of the current-voltage conversion circuit (14), and the pilot signal cancellation of the noise removal circuit (3) is performed. The deterioration of the characteristics was prevented. However, the adjustment of the variable resistor is performed by adjusting the output signal level of the current-voltage conversion circuit (14) so that the output signal level of the current-voltage circuit (14) becomes a predetermined level in the adjustment process of the radio receiver set production. Since it was done manually while watching, there was a problem that the production efficiency of the radio receiver set fell.

[0006]

According to the present invention, a pilot cancel signal is generated according to a first input signal whose frequency is equal to that of a pilot signal and a second input signal whose frequency is equal to that of a subcarrier signal and which is offset by 90 degrees. A pilot cancellation signal generating circuit for generating a binary signal generating circuit for generating a binary signal of a predetermined ratio according to the second input signal;
A level changing circuit for changing the binary signal to N times based on a control signal of an external control circuit, and a signal generating circuit for generating an inverted signal or a non-inverted signal of an output signal of the level changing circuit according to a first input signal. And are provided.

Further, the level changing circuit comprises a plurality of current mirror circuits having different mirror ratios and a selection circuit for selecting one of the output signals of the plurality of current mirror circuits based on the control signal. Is characterized by. further,
V for generating an output signal having a frequency four times that of the pilot signal
CO, a first frequency divider circuit for dividing the output signal of the VCO by two, a second frequency divider circuit for dividing the output signal of the first frequency divider circuit by two, a pilot signal and a second frequency divider circuit. A subcarrier signal regenerating circuit including a phase comparison circuit that compares the phase of the output signal and controls the output frequency of the VCO according to the phase comparison result, and outputs the output signal of the first frequency dividing circuit to the first input signal. And the output signal of the second frequency dividing circuit is the second input signal.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing an embodiment of the present invention, in which (15) is 38 KH displaced by 90 degrees from the base.
The transistor (16) to which the input signal of z is applied, and the signal and the transistor (1
Transistor (17) supplied with collector current of 6)
And a binary signal generating circuit including a transistor (18) to which a signal indicating stereo reception is supplied to the base, (1
9) is a level change circuit for changing the magnitude of the added collector current of the transistors (17) and (18) to N times, (2)
0), the output current of the level changing circuit (19) flows through the common emitter, and the bases have 19 KH of opposite phase to each other.
A transistor (2
1) and (22) and transistors (21) and (2)
A signal generation circuit (26) comprising current mirror circuits (23) and (24) for inverting the collector currents of 2) and a current mirror circuit (25) for inverting the output current of the current mirror circuit (23), An external control circuit for setting N of the level changing circuit (19), (27) a resistor for converting the differential current of the current mirror circuits (24) and (25) into a voltage,
(28) is an amplifier for amplifying the output voltage generated from one end of the resistor (27).

In FIG. 1, "L" is applied to the input terminal (29).
When a signal indicating a level monaural reception is applied, the transistors (17) and (18) are turned off, so that an operating current does not flow in the differential pair including the transistors (21) and (22), and the differential pair is Does not work. Therefore, no output signal is generated from the amplifier (28). When receiving stereo
An "H" level input signal indicating stereo reception is applied to the bases of the transistors (17) and (18) from the stereo detection circuit (6) as shown in FIG. The transistors (17) and (18) are fully operated by the input signal at the input terminal (29). Further, the input signal of 38 KHz from the first frequency dividing circuit (10) of FIG. 1 as shown in FIG. 3C is applied to the base of the transistor (16) via the input terminal (30). Since the transistor (16) is turned on or off according to the input signal of the input terminal (30), the transistor (17) is also turned on or off. The transistor (1
7) operates so that when the transistor (16) turns on, it turns off. Therefore, the collector current of the transistor (17) switches according to the input signal of the input terminal (30), and the collector current of the transistor (18) becomes a constant current. Therefore, if the collector currents of the transistors (17) and (18) are Ic17 and Ic18, respectively,
The added current of the collector currents of the transistors (17) and (18) is as shown in FIG. The added current is supplied to the level change circuit (18), and then the transistor (2
It flows to the common emitter of 1) and (22). The control circuit (26) retrieves control data from a built-in storage device and generates a control signal based on the control data. According to the control signal, the level changing circuit (19) is set to multiply the addition current by N times. Therefore, the current flowing through the common emitter is equal to the sum of the added current and N.
It doubles and is similar to the added current.

Also, the transistors (21) and (22)
The input signals of (a) and (b) of FIG. 3 generated from the first frequency divider circuit of FIG. 1 are applied to the bases of the above (3) and (3) through input terminals (31) and (32). Since the input signals of the input terminals (31) and (32) are signals having opposite phases to each other, the transistors (21) and (22) are turned on / off alternately according to the input signals. Input terminals (31) and (32)
When the input signals of are at "H" and "L" levels, respectively, the transistor (21) turns on and the transistor (22) turns off, so that the output signal of the level change circuit (19) flows only to the transistor (21). , Transistor (21)
Collector current is as shown in FIG. The collector current of the transistor (21) is inverted by the current mirror circuits (23) and (25). Since no collector current is generated from the transistor (22), only the output current of the current mirror circuit (25) flows into the resistor (27) and is converted into voltage. The voltage-converted output signal becomes a non-inverted signal of the output signal of the level changing circuit (19) and is applied to the noise removing circuit (3) as shown in FIG. 1 via the amplifier (28).

On the other hand, when the input signals of the input terminals (31) and (32) are at the "L" and "H" levels, respectively, the transistors (21) and (23) are turned off and on, respectively, so that the level change circuit (19). 3), the collector current of the transistor (22) is as shown in FIG. Transistor (22)
The collector current of is inverted by the current mirror circuit (24) and then flows through the resistor (27). The output signal voltage-converted by the resistor (27) becomes a signal obtained by inverting the output signal of the level change circuit (19), and is transmitted to the subsequent circuit via the amplifier circuit (28). Therefore, by the above operation, the pilot cancel signal as shown in FIG. 3 (g) is generated from the output terminal (33).

By the way, according to the control signal of the control circuit (26), the level change circuit (19) causes the transistor (1
The summed collector currents of 7) and (18) are multiplied N times, and the current flowing through the common emitter of the transistors (21) and (22) is N times the summed collector current. Therefore, the magnitude of the current flowing through the resistor (27) is also N times. Therefore, the output signal voltage-converted by the resistor (27) becomes N times as large as the control signal. For example, a level changing circuit (19)
Of the output terminal (3
The output signal level of 3) is doubled.

The control signal of the control circuit (26) is adjusted during the production adjustment process of the radio receiver set. That is, during the adjustment process, the control circuit (26) and the output terminal (3
3) Connect an adjusting circuit between the radio receiver set and the radio receiver set to receive the stereo broadcast test signal. In that state, the adjusting circuit instructs the control circuit (26) to sequentially change the control signal, and sees the output signal level of the output terminal (33) every time the control signal is changed. The adjustment circuit detects the optimum level of the pilot cancellation signal from among them,
The corresponding control signal is stored in the storage device built in the control circuit (26). The adjustment process is completed and the adjustment circuit is removed.

Here, since the level of the pilot cancel signal changes depending on the characteristics of the elements constituting each circuit according to the temperature inside the radio receiver set, for example, a noise canceling circuit (FIG. 1) using the pilot cancel signal ( The noise removal characteristic of 3) deteriorates with temperature change. If the control signal of the control circuit (12) has a temperature characteristic, the pilot cancel signal level changes according to the temperature in the radio receiver set, so that the pilot cancel signal suitable for the temperature can be obtained.

[0015]

FIG. 4 shows a concrete circuit of a level changing circuit (19), in which (35) is transistors (17) and (18).
Input terminals to which the added collector current of (3) is supplied, (36) to (38) control terminals to which a control signal from the control circuit (26) is applied, and (39) transistor (40), (4
1) and (42) are current mirror circuits, (43) and (44) are transistors forming current mirror circuits with transistors (40) and (41), and (45) and (4).
6) is a current mirror circuit for inverting the collector current of the transistor (42), (47) and (48) is a current mirror circuit for inverting the collector current of the transistor (43),
(49) and (50) are current mirror circuits for inverting the collector current of the transistor (44), and (51) to (5)
3) is a control transistor for controlling the operation of the current mirror circuit according to the control signals of the control terminals (36) to (38),
(54) is a current mirror circuit (46), (48) and (5)
0) is an output terminal for generating the output current.

Control terminals (36), (37) and (38)
Control signal levels of "L", "H" and "H" respectively
At the level, the transistors (52) and (53) are turned on. Therefore, the current mirror circuits (48) and (50)
Since the bases of the transistors forming the above are grounded, the current mirror circuits (48) and (50) are turned off. Also,
The current mirror circuit (46) is in operation. In this state, the input signal of the input terminal (35) is sequentially inverted by the current mirror circuits (39), (45) and (46), and is generated via the output terminal (54). The ratio between the input current of the input terminal (35) and the output current of the output terminal (54) is determined by the emitter resistance R40 of the transistor (40) and the emitter resistance R46 of the transistor (46 ') forming the current mirror circuit (46). It is determined by the ratio of. The emitter resistance ratio of the transistors (40) and (46 ') is R40: R46 = 1: 1.
Therefore, the output current of the output terminal (54) becomes equal to the magnitude of the input signal of the input terminal (35).

Further, when the control signal levels of the control terminals (36), (37) and (38) are "H", "L" and "H" levels, respectively, the transistors (51) and (5).
3) turns on. Therefore, although the current mirror circuit (48) is in operation, the current mirror circuits (46) and (50)
Turn off. In this state, the input current of the input terminal (35) is inverted by the current mirror circuit composed of the transistors (40), (41) and (43) and the current mirror circuits (47) and (48), It occurs at the output terminal (54). The input current of the input terminal (35) and the output terminal (5
The ratio to the output current of 4) is determined by the ratio of the emitter resistance R40 of the transistor (40) and the emitter resistance R48 of the transistor (48 ') forming the current mirror circuit (48), and the resistance ratio is R40: R48. = 1: 2, the output current of the output terminal (54) is
It is twice the input current of 5).

Further, when the control signal levels of the control terminals (36), (37) and (38) are "H", "H" and "L" levels, respectively, the transistors (51) and (5).
2) turns on. Therefore, although the current mirror circuit (50) is in operation, the current mirror circuits (46) and (48)
Turn off. In this state, the input current of the input terminal (35) is inverted by the current mirror circuit composed of the transistors (40), (41) and (44) and the current mirror circuit (49) and (50), It occurs at the output terminal (54). The input current of the input terminal (35) and the output terminal (5
The ratio to the output current of 4) is determined by the ratio of the emitter resistance R40 of the transistor (40) and the emitter resistance R50 of the transistor (50 ') forming the current mirror circuit (50), and the resistance ratio is R40: R50. = 1: 4, the output current of the output terminal (54) is
It is four times the input current of 5).

Therefore, it is possible to generate an output current of a predetermined multiple of the input current according to the control signal. The number of control signals is not limited to three as shown in FIG. 4, and may be set arbitrarily. Further, the input / output current ratio is not limited to the current ratio as shown in FIG.
It may be set arbitrarily. By increasing the number of control signals and finely setting the input / output current ratio, the level of the pilot cancel signal can be set with high accuracy.

[0020]

As described above, according to the present invention, a predetermined binary signal is generated, the magnitude of the binary signal is multiplied by N according to the control signal, and then the signal is inverted or non-inverted. An optimum level of pilot cancellation signal can be obtained. Since the control signal can be obtained by automatic adjustment in the production process of the radio receiver set, the production efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is a waveform diagram for explaining the present invention.

FIG. 4 is a circuit diagram showing a specific circuit example of a level changing circuit (19).

[Explanation of symbols]

15 Binary signal generation circuit 19 Level change circuit 20 Signal generation circuit 27 Resistance 28 amplifier

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04H 5/00 H03D 3/02

Claims (3)

(57) [Claims] 1. A pilot cancel signal generation circuit for generating a pilot cancel signal in response to a first input signal having the same frequency as a pilot signal and a second input signal having the same frequency as the subcarrier signal and shifted by 90 degrees. , A non-zero first level and a first level higher than said first level
Generating two levels and synchronizing with the second input signal
A binary signal generating circuit for alternately generating first and second levels, a level changing circuit for changing the binary signal generating circuit to N times based on a control signal of an external control circuit, and a first input signal Output of the level change circuit in the first half cycle of
A second signal following the first half cycle by generating an inverted signal of the signal.
A non-inverted signal of the output signal of the level change circuit is output in a half cycle.
Generated and synchronized with the pilot signal
By combining the inverted and non-inverted signals, the pyro
And a signal generation circuit for generating a stop cancellation signal. 2. The level changing circuit comprises a plurality of current mirror circuits having different mirror ratios, and a selection circuit for selecting one of the output signals of the plurality of current mirror circuits based on the control signal. The pilot cancel signal generating circuit according to claim 1, wherein 3. A VCO which generates an output signal having a frequency four times as high as a pilot signal, a first frequency divider circuit which divides the output signal of the VCO by two, and an output signal of the first frequency divider circuit which is divided into two. Subcarrier signal reproduction including a second frequency dividing circuit that performs frequency division, a phase comparison circuit that compares the pilot signal and the output signal of the second frequency dividing circuit, and controls the output frequency of the VCO according to the phase comparison result 2. The pilot cancel signal generating circuit according to claim 1, further comprising a circuit, wherein an output signal of the first frequency dividing circuit is a first input signal and an output signal of the second frequency dividing circuit is a second input signal.