JP3392545B2 - Instruction sequence optimizer - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction sequence optimizing device for optimizing, for example, a control program of an information processing device.

[0002]

2. Description of the Related Art With the recent development of multimedia,
For example, portable information processing devices such as book computers, notebook computers, and mobile phones have become widely used.

FIG. 26 shows a schematic configuration of a control unit of such a portable information processing apparatus. The CPU (Centr
In al processing Unit) 2610, execution unit 2611 executes each instruction that constitutes the control program. The input / output unit 2612 is the execution unit 2611.
Address of the instruction to be executed by the address bus 2631
And the instruction corresponding to this address is fetched from the instruction bus 2632. The register unit 2613 is
The data generated by the execution of the instruction by the execution unit 2611 is temporarily stored.

On the other hand, in the program memory 2620, the storage section 2621 stores in advance the respective commands constituting the control program. Also, the input / output unit 2622
Reads an instruction corresponding to the address input from the address bus from the storage unit 2621,
Output to.

In such a configuration, the CPU 2610
When performing control by, first, the execution unit 2611
The address of the instruction to be executed is sent from the input / output unit 2612 of the CPU 2610 to the input / output unit 2622 of the program memory 2620 via the address bus 2631. As a result, the program memory 2620 reads the instruction corresponding to the designated address from the storage unit 2621,
It is output from the input / output unit 2622. The input / output unit 2612 of the CPU 2610 inputs this instruction via the instruction bus 2632 and sends it to the execution unit 2611. Then, the execution unit 2611 executes this instruction to control the information processing device.

In this way, when the execution unit 2611 is executing an instruction, if there is data that needs to be temporarily stored, this data is stored in the CPU 261.
It is stored in the register unit 2613 in 0 and is read out as needed.

Here, the control program used for the information processing apparatus as shown in FIG. 26 is created in advance and stored in the program memory 2620 when the information processing apparatus is manufactured. In the development of such a control program, various optimization processes are performed in a means for creating a target program (that is, a program to be stored in the program memory 2620) by compiling a high-level language or an assembly language. As this optimization processing, for example,
An optimization process for reducing the execution time of the control program, an optimization process for reducing the memory area used for storing the control program, and the like are already known.

[0008]

In the information processing apparatus as described above, reduction in power consumption has been conventionally required. In particular, portable information processing devices are required to reduce power consumption in order to improve the continuous use time. Further, also in information processing devices other than the portable type, reduction of power consumption is required from the viewpoint of environmental protection and energy consumption reduction.

The power consumption P of the internal circuit of the information processing apparatus is
It is expressed by the following formula.

P = α · C · Vdd ² · n · f + Ps where α is the operating rate, C is the capacitance of the entire circuit,
Vdd is the power supply voltage, n is the number of circuit elements, f is the operating frequency,
Ps is the power consumption during standby.

Conventionally, the power consumption has been reduced by configuring the hardware so that the value of each of these parameters becomes small.

However, the power consumption could not be sufficiently reduced only by such hardware measures.

The present invention has been made in view of the above-mentioned drawbacks of the prior art, and it is possible to perform an optimization process for reducing power consumption at the stage of creating a control program for an information processing device. An object is to provide a column optimization device.

[0014]

(1) An instruction sequence optimizing apparatus according to a first aspect of the present invention comprises a program memory for storing a program and an arithmetic processing unit for fetching the program from the program memory via an instruction bus. In an instruction string optimizing device for optimizing the program for use by an information processing device provided, an instruction string analyzing means for analyzing mutual dependence relations of respective instructions constituting the program, and the instruction string analyzing means. By changing the order of the instructions within a range that does not affect the dependency analyzed in step 1, the Hamming distance between the bit strings appearing on the instruction bus when the instructions are transferred from the program memory to the arithmetic processing unit is reduced. Instruction sequence changing means for reducing the program, dividing the program into basic blocks, and dividing the basic block into the instruction sequence analysis means. And a block dividing means for sending to, the instruction string changing means, the last bit string of the basic block immediately before the instruction sequence determining process and the first bit string of the basic block to perform the current instruction sequence determining process. It is characterized in that the instruction order determination processing in this block is performed in consideration of the Hamming distance between the blocks. (2) An instruction sequence optimizing device according to a second aspect of the present invention follows a plurality of registers for temporarily storing data, a program memory for storing a program, and an instruction fetched from the program memory via an instruction bus. In an instruction sequence optimizing device for optimizing a program for use by an information processing device having an arithmetic processing unit for writing / reading data to / from the register, the register number in each instruction constituting the program is A register number recognizing unit for recognizing, a register valid range recognizing unit for recognizing the valid range of the register number recognized by the register number recognizing unit, and a valid range recognized by the register valid range recognizing unit are not affected. By changing the register number in the range, the instruction containing this register number Characterized in that and a instruction sequence changing means for reducing the Hamming distance bit Retsukan appearing on the instruction bus when transferring from program memory to the processing unit. (3) The instruction sequence optimizing apparatus according to the third invention is used by an information processing apparatus including a program memory for storing a program and an arithmetic processing unit for fetching the program from the program memory via an instruction bus. In the instruction sequence optimizing device for optimizing the program, a storage means for storing another bit pattern meaning the same instruction for some or all of the instructions constituting the program, and an instruction in the program, Instruction string changing means for reducing the Hamming distance between bit strings appearing on the instruction bus when the instruction is transferred from the program memory to the arithmetic processing unit by replacing the bit pattern stored in the storage means, It is characterized by having. (4) The instruction sequence optimizing device according to the fourth invention is used by an information processing device having a program memory for storing a program and an arithmetic processing unit for fetching the program from the program memory via an instruction bus. In the instruction sequence optimizing device for optimizing the program, selection means for selecting another instruction or instruction sequence that can obtain the same processing result for the instruction or instruction sequence in the program, and the instruction in the program Alternatively, by replacing the instruction sequence with the instruction or instruction sequence selected by the selecting means, the Hamming distance between the bit sequences appearing on the instruction bus when the instruction or instruction sequence is transferred from the program memory to the arithmetic processing unit. And an instruction sequence changing means for reducing (5) The instruction sequence optimizing device according to the fifth invention is used by an information processing device having a program memory for storing a program and an arithmetic processing unit for fetching the program from the program memory via an instruction bus. In the instruction sequence optimizing device for optimizing the program, selection means for selecting another instruction or instruction sequence that can obtain the same processing result for the instruction or instruction sequence in the program, and the instruction in the program Alternatively, regarding the instruction sequence and the instruction or the instruction sequence selected by the selecting means, the power consumption in the instruction bus when the instruction or the instruction sequence is transferred from the program memory to the arithmetic processing unit, considering the Hamming distance. Calculating means and a command selected in the selecting means by the command or command sequence in the program Or by replacing the instruction sequence, wherein said computing means is provided with a instruction sequence changing means for reducing the power consumption estimated.

[0015]

[Action]

(1) According to the instruction sequence optimization device of the first invention,
By analyzing the mutual dependence of each instruction that composes the program and changing the order of the instructions within the range that does not affect the dependence, the instruction bus is transferred to the arithmetic processing unit when the instruction is transferred from the program memory. Since the Hamming distance between the appearing bit strings is reduced, the power consumption of the information processing device can be reduced. (2) According to the instruction sequence optimization device of the second invention,
Recognize the register number of each instruction that makes up the program,
Then, by recognizing the valid range of this register number and changing the register number within the range that does not affect this valid range, the bit string that appears on the instruction bus when the instruction containing this register number is transferred. Since the Hamming distance between them is reduced, the power consumption of the information processing device can be reduced. (3) According to the instruction sequence optimization device of the third invention,
By replacing another bit pattern that means the same instruction with the instruction in the program, the Hamming distance between bit strings appearing on the instruction bus when transferring this instruction from the program memory to the arithmetic processing unit is reduced. The power consumption of the information processing device can be reduced. (4) According to the instruction sequence optimization device of the fourth invention,
A bit string that appears on the instruction bus when this instruction or instruction string is transferred from the program memory to the arithmetic processing unit by replacing another instruction or instruction string that can obtain the same processing result with the instruction or instruction string in the program. Since the Hamming distance between them is reduced, the power consumption of the information processing device can be reduced. (5) According to the instruction sequence optimization device of the fifth invention,
Estimating the power consumption of an instruction or instruction sequence in a program and other instructions or instruction sequences that can obtain the same processing result as this instruction or instruction sequence, and replacing it with an instruction or instruction sequence that consumes less power. Therefore, the power consumption of the information processing device can be reduced.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) As Embodiment 1, an embodiment of the first invention (corresponding to claims 1 to 4) will be described.

FIG. 1 is a flow chart schematically showing the concept of the first invention (corresponding to claim 1). As shown in the figure, in the first aspect of the invention, first, with respect to each instruction forming the program, mutual dependency is analyzed using the instruction sequence analysis means (step S100).
Then, the order of the instructions is changed so that the Hamming distance between the bit strings appearing on the instruction bus is reduced without affecting this dependency (step S101). Then, by changing the instruction order, reduction of power consumption in the instruction bus is realized.

In step S101, first, the power consumption reducing means (corresponding to the "instruction sequence changing means" of the first invention) is used to change the instruction order and determine the Hamming distance at this time. Perform (step S102). Next, the determined Hamming distance is compared with a predetermined reference value (step S103). Here, the reference value may be a predetermined value, or may be the lowest value of the Hamming distance that has been determined by the power consumption reduction unit until then. Then, when the Hamming distance determined by the power consumption reduction means is smaller than the reference value, the order of this instruction is output as the result of optimization, and this optimization processing ends (step S10).
4). On the other hand, if the determined Hamming distance is larger than the reference value, the same processing (steps S102 and S103) is repeated for another instruction order.

Next, an example embodying FIG. 1 (claims 1 to 3)
2) will be described with reference to the flowchart of FIG.

In this case, the information processing apparatus in which the execution unit and the instruction bus are both 32 bits (see FIG. 14A).
The case where the first invention is applied to the optimization of the control program used in (see) will be described as an example.

In FIG. 2, in step S200, the control program is divided into basic blocks. Here, the basic block means a program block in which a branch from the middle to the outside does not occur and a branch from the outside to the middle does not occur, such as a sequence of expressions and assignment statements. When the division into basic blocks is completed, next, for each instruction sequence in this basic block, the dependency relationship of those instructions and the dependency relationship of registers are analyzed, and the range that does not violate the causality of processing by exchanging instructions. Specify. Then, an identifier for identifying each range thus specified is added to the program.

The process in step 200 is a process used also in other optimization processes known in the related art, and therefore detailed description thereof is omitted here. Documents disclosing such processing include the following, for example.

Z.Li and PC.Yew, “Efficient Interpro
cedual Analysis fir Program Parallelization and Re
structuring, ”Proc.ACM SIGPLAN PPEALS, pp85-97,198
8.S. Jain and C. Thompson, ”An Efficient Approach to
Dataflow Analysis ina Multiple Pass Global Optimi
zer, ”Proc.SIGPLAN'88 Cof.on Prog.Lang.Design an
d Implementation (PLDI'88), pp.154-163, 1988. Next, in step S201, optimization processing is performed for each basic block. The processing procedure of step S101 will be described below.

First, in step S202, initial setting is performed. In FIG. 2, the variable LastCom is substituted with the last instruction of the basic block that was previously optimized. In the initial setting, this variable LastCo
The default value (one of the instruction bit strings) is assigned to m. Any value may be used as the default value, for example, all bits “1” or all bits “0”. However, in reality, the most frequently appearing instruction statistically, and the header program (prologue program, that is, the program created by the target user from the OS) to be finally linked is started, and after execution is completed. Program to return to the OS) or runtime
It is preferable to use a final instruction such as a routine as a default value.

In subsequent steps S203 to S212,
Processing is performed to minimize the Hamming distance. The procedure shown here uses a naive and reliable "busy" method that optimizes by sequentially changing the order of instructions and trying all possible patterns. In addition,
In the case of a basic block having a complicated data structure, it is effective to perform high-speed processing using a special method, but the present invention is not particularly limited to this.

In step S203, it is determined whether or not all the processing has been completed. Since the optimization processing in this embodiment is performed for each basic block, it ends when the processing for all basic blocks is completed.
If the result of this determination is that there is a basic block that has not been processed, the processes in and after step S204 are executed.

In step S204, it is determined whether or not the optimization process in the basic block is completed. This optimization processing is performed by replacing the execution order of each instruction in the basic block. The process for the basic block of interest ends when all possible replacement methods (permutations) that do not cause inconsistency in order dependency or register dependency of the instruction have been tried, and step S21
Go to 3. On the other hand, when all the trials of the replacement method are not completed, the optimization process after step S205 is continued.

In step S205, initialization is performed prior to optimization within the block. In FIG. 2, the variable Hd_
sum represents the sum of Hamming distances between instructions in the basic block of interest, and variable Hd_bound is variable L.
It is the Hamming distance between astCom and the head instruction of the basic block of interest. Also, the variable Hd_total
Indicates the sum of the variable Hd_sum and the variable Hd_bound, and the variable Hd_min indicates the minimum value of the variable Hd_total. "∞" is substituted into this variable Hd_min as an initial setting. Here, “∞” is a value larger than any number.

In step S206, the sum of the Hamming distances in the basic block of interest is obtained, and the variable Hd_s
Substitute in um. This sum is
It can be easily obtained by comparing the patterns and accumulating when the value of the bit of the corresponding digit is different as "1".

In step S207, the Hamming distance between the last instruction (variable LastCom) of the previously processed basic block and the first instruction of the basic block of interest this time is calculated in the same manner as in step 206, and the variable Hd_bo is obtained.
Substitute in un. By performing this operation, it is possible to perform an optimization process that spans basic blocks.

In step S208, the sum of Hamming distances between instructions in the current instruction sequence pattern,
That is, the sum of the variable Hd_sum and the variable Hd_bound is calculated and substituted into the variable Hd_total.

In step S209, step S208
The value of Hd_total obtained in (4) is compared with Hd_min, which is the minimum value of Hd_total obtained by the trials up to now. And Hd_tot
If al ≧ Hd_min, a different instruction sequence
To make further trials on the pattern, step S
212 and subsequent steps are executed. On the other hand, Hd_total <Hd
In the case of _min, steps S210 and S211 are executed, and then steps S212 and thereafter are executed.

In steps S210 and S211, the variables are updated. First, in step S210, Hd
Substitute the value of _total for Hd_min. Further, in step S211, the instruction sequence pattern corresponding to this Hd_min is set to the variable MinHdSeq.
memorize in uence.

In step S212, the instruction sequences are exchanged. Here, by changing the order of the instructions in the basic block, an instruction sequence that has not been tried is generated, and the process returns to step S204.
In this command exchange, the causality is prevented from being inconsistent based on the result of the analysis performed in step S200.

Steps S203 to S212 described above
The optimization can be performed by repeatedly performing the process consisting of.

When the trials for all the instruction sequence patterns are completed (step S204), then,
Step S213 is executed. In step S213,
Optimized instruction sequence (variable MinHdSequ
(stored in ence) is output as the result of optimization.

In step S214, the variable LastCo
Update m. That is, this variable LastCom
To the last instruction stored in the variable MinHdSequence.

Then, in the same manner as described above, the processing from step S203 is executed for the next basic block.

Next, the case where the optimization process of this embodiment is actually performed will be described by taking the case of using the program shown in FIG. 3 as an example.

The program of FIG. 3 is a program for performing an inner product of integers, and is written in C language.

FIGS. 4 to 7 show assembly source program lists when the program shown in FIG. 3 is compiled by the "Sun SPARC C compiler". 4 to 7, the first column shows the line number, the second column shows the address, the third column shows the object code, and the fourth column shows the assembly source. In addition, C101 to C313 and B1 to
B6 is a code for description. Here, the assembly grammar, mnemonics, and the like are publicly known techniques, and therefore description thereof will be omitted. However, examples of documents disclosing these are as follows.

SPARC International, Inc., The SPARC Arc
hitecture Manual Version 8, Prectice-Hall, Inc.A Sim
on and Schuster Company Englewood Cliffs, New Lerse
y 07632. The assembly source as shown in FIGS. 4 to 7 is input to the optimization processing apparatus of this embodiment. And
This assembly source is searched for a basic block in step S200 in FIG. As a result, this program is executed as shown in B1 to B6 in FIGS.
Is divided into basic blocks.

Furthermore, the dependency relationship of the instructions in each basic block is analyzed. 8 and 9 are directed graphs showing the results of dependency analysis. Here, FIG. 8 is a directed graph of the basic block B1 (see FIG. 4), and C10 of FIG.
1 to C104 are nodes N101 to N10 in FIG.
It corresponds to 4. Similarly, FIG. 9 shows a basic block B3.
6 is a directed graph (see FIG. 5), and C301 to C301 in FIG.
Reference numerals 313 correspond to the nodes N301 to N313 in FIG. 9, respectively. Also, the nodes N100 and N300 are dummy nodes that represent the top of the directed graph.
05 and N314 are dummy nodes representing the bottom of the directed graph. Further, the arcs A101 to A105, A3
01 to A314 indicate instruction dependencies, which indicate that instructions must not be executed in the reverse order of the arrows. The order relation of the instructions in the basic block is managed by creating such a directed graph.

First, the optimization process of the first basic block B1 will be described. The basic block B1 is a prologue process for saving the internal state in order to execute this program. As shown in the directed graph of FIG. 8, since the four instructions C101 to C104 can be executed only in this order, they are output as they are.

The description of the optimization process of the second basic block B2 is omitted, but at the end of the process of the basic block B2, "nop" as the last instruction C204.
Are stored in LastCom.

Next, the optimization processing of the third basic block B3 is performed. In the basic block B3, as shown in the digraph of FIG. 9, "C301", "C302 to C3"
It is possible to change the order of instruction sequences among 04 "," C305 ", and" C306 to C308 ", but" C302 to C304 "and" C306 to C308 "
You cannot change the order of instructions within. Also, C
309 to C313 can be executed only in this order, and C3
It cannot be executed before 01-C308.

First, when the instruction sequence pattern is as shown in FIG. 5, that is, C301, C302 ... C313, the optimization processing steps S205 to S211 as shown in FIG. 2 are performed. At this time, LastC
As described above, "nop" as the last instruction C204 of the basic block B2 is stored in om. In addition, “∞” is substituted for the minimum Hamming distance Hd_min as an initial setting.

FIG. 10 shows the last instruction C204 of the basic block B2 and each instruction C301 to C3 of the basic block B3.
313 shows the bit pattern. For such bit patterns, Hd_sum, Hd_bou
When n and Hd_total are calculated (step S in FIG. 2).
206 to S208), Hd_sum = 161, Hd
_Bound = 13, so Hd_total
= 174.

Here, the minimum Hamming distance Hd_min =
Since it is ∞, as a result of the comparison in step S209 (see FIG. 2), Hd_min is set to Hd_total = 174 (step S210), and the instruction sequence shown in FIG. 5 is changed to the variable MinHdSequence.
It is stored in e (step S211).

Next, similar processing (steps S205 to S211) is performed when the order of the instructions is changed.

When the trials of all the interchangeable instruction sequences are completed, the variable MinHd
The sequence of instructions stored in Sequence is
It is output as a result of optimizing the instruction sequence (step S213).

FIG. 11 shows the bit pattern of the instruction sequence output in step S213. As a reference example, the worst bit pattern (that is, the total sum of Hamming distances is maximum) is shown in FIG. The total Hamming distance Hd_total in FIG. 11 is 130.
In addition, the total sum Hd_tot of the Hamming distances in FIG.
al becomes 196. That is, according to the present embodiment, the number of times of switching of the instruction bus when executing the basic block B3 can be set to 74.7% before the optimization by the optimization processing, and 66. It could be 3%.

In the same manner, the optimization processing for the fourth to sixth basic blocks B4 to B6 is performed in the same manner. However, since the order of the instructions cannot be changed in each of these blocks B4 to B6, they are output as they are. Ends the process.

Next, a modified example (corresponding to claim 4) of the instruction sequence optimizing apparatus according to this embodiment will be described with reference to FIG.

Depending on the instruction in the program, the instruction format includes a "do not care" bit, that is, a bit that does not affect the operation of the instruction regardless of whether it is "1" or "0". There are cases. For example, in the above basic block B3, the instruction C303,
The 12th to 6th bits (bits <11: 5>) of C304, C307, and C308 are "do not care" bits (see FIG. 10). By appropriately changing the value of such bits, it may be possible to reduce the Hamming distance between adjacent instructions.

FIG. 13 is a flowchart showing an example of processing for reducing the Hamming distance by changing the value of the bit "do not care".

By executing the processing shown in FIG. 13 instead of step S206 in FIG. 2, "do not c
The Hamming distance can be further reduced by taking the "are" bit into consideration.

In the figure, in step S1301,
As an initial setting, the initial value “∞” is assigned to the variable Hd_sum.

Next, in step S1302, it is determined whether or not this processing is completed. In this process,
Perform the following trials while changing the value of all bits of "do not care". Then, when all the trials for the combination of "1" and "0" of the "do not care" bits are completed, this processing is completed.

In step S1303, the current "do"
For the bit pattern of "not care", the sum of the Hamming distances between the adjacent instructions is calculated, and the variable Hd_sum is calculated.
Substitute in _current.

In step S1304, the magnitude comparison between Hd_sum and Hd_sum_current is performed. Here, if Hd_sum ≧ Hd_sum_current, Hd_s is added to Hd_sum in step S1305.
After substituting the value of um_current, step S
Proceed to 1306. On the other hand, Hd_sum <Hd_sum_
If it is current, the process directly proceeds to step S1306 without executing step S1305.

In step S1306, "do not care".
Change the bit pattern of "to a bit pattern that has not been tried yet.

Such processing is performed, for example, in the basic block B.
In the pre-optimization program of 3 (see FIG. 10),
The sum of the Hamming distances Hd_sum and Hd_total can be reduced by 10.

The control program optimized as described above is stored in the program memory of the information processing apparatus, and the control program is used to control the CPU or the like to reduce the power consumption in the instruction bus. It becomes possible.

The procedure shown in this embodiment is a one-pass method in which optimization is sequentially performed on input data. Therefore, the Hamming distance may not be the minimum in the finally obtained instruction example. This is because the optimization of the boundaries of the basic blocks only considers the final instruction of the basic block immediately preceding the basic block of interest. Therefore, in order to further reduce the Hamming distance, for example, a method of considering a basic block next to the basic block of interest, a basic block next to the basic block, or the like can be considered. However, in order to quickly perform optimization with simple processing, it is preferable to divide the processing into basic blocks and perform the processing.

The optimization processing according to the present embodiment and other optimization processing (for example, optimization processing for shortening the execution time of the control program,
When performing an optimization process for reducing the memory area used for storing the control program), the effect of the present embodiment can be obtained regardless of the order in which each optimization process is performed. However, in order to obtain the effect of this embodiment most effectively, it is desirable to perform the optimization according to this embodiment last. Here, when the optimization process of the present embodiment is performed last, the result of another optimization process may be changed, but such inconvenience can be prevented in step S100 (see FIG. 1). ) Dependency analysis phase. That is, in the directed graphs shown in FIGS. 8 and 9, the constraint may be set so as not to change the result of other optimization processing.

In the present embodiment described above, the optimization of the control program used in the information processing device having both 32-bit execution units and instruction buses is taken as an example. That is, the control program optimized in this embodiment is as shown in FIG.
It has been assumed that the instruction as shown in (a) is read one by one at a time and used to control the information processing apparatus for fetching, issuing, decoding, and executing. Therefore, the Hamming distance to be considered in the optimization process is the Hamming distance between adjacent instructions as shown in FIG.

However, as shown in FIG. 14B, many CPUs today are configured to read, fetch, and issue a plurality of instructions at once. When using such a CPU, the Hamming distance to be considered when performing optimization is not the Hamming distance between adjacent instructions but the Hamming distance between instructions assigned to the same field and the same bit position of the instruction bus. . That is, as shown in FIG. 14 (b), when optimizing the control program of the CPU configured to read out two instructions at a time, every other instruction as shown in FIG. 15 (b). Between instructions (for example, C301 and C303, C302 and C30
The optimization may be performed so that the Hamming distance of 4) is reduced. In such a case, if a bit string obtained by bit-combining (concatenating) two instructions at a time is created, the optimizing process can be performed using the optimizing device of this embodiment as it is.

FIG. 16A shows an apparatus configured to read four instructions at a time. Also in such a case, as shown in FIG. 16B, between every three instructions (for example, C301 and C305, C302 and C306).
The optimization may be performed so as to reduce the Hamming distance of (e.g.). If a bit string obtained by bit-combining four instructions each is created, the optimization processing can be performed using the optimization apparatus of this embodiment as it is.

Depending on the information processing device, the bandwidth of the internal instruction bus may differ from the bandwidth of the external instruction bus. In FIG. 17, the bandwidth of the internal instruction bus is 128 bits, but the bandwidth of the external instruction bus is 3 bits.
The case of 2 bits is shown. In such a case, for the internal bus, the Hamming distance may be reduced between every three instructions, and for the external bus, the Hamming distance may be reduced between adjacent instructions. Which is to be prioritized or compromised with each other may be appropriately determined according to the degree of involvement in reduction of power consumption.

(Embodiment 2) As Embodiment 2, an embodiment of the second invention (corresponding to claims 5 and 6) will be described.

Here, a case where both the execution unit and the instruction bus are 32 bits will be described as an example.

In the instruction sequence optimizing device of this embodiment,
The control program is optimized by paying attention to the variables that should be assigned to the registers. That is, the minimum register number is assigned by observing the bit change amount in a certain section of the instruction sequence in which the variable appears.

In the present embodiment, when c = ab, c = a / b, etc., a is a source, b is a target, and c is a destination, and a register holding the value of a is a source.
The register holding the value of b and the register holding the value of b will be called the target register, and the destination register holding the value of c will be called. Of the 32-bit instruction, counting from the left MSB, the 1st to 10th bits and the 21st to 27th bits are used as the field of the instruction code, and the 11th to 15th bits of the destination register. Field, 16th bit ~
The 20th bit is the source register field and 2
The 7th bit to the 32nd bit are the fields of the target register.

The effective range of the data stored in a certain register number is the instruction in which this stored data is required after the data is stored in the register by the instruction in which this register number appears as the destination register number, that is, This register number is up to the instruction that appears as the source register or the target register. Naturally, one register number is reused as a temporary storage location for a plurality of variables or data for efficiency. Therefore, in order to know the range in which one register data with one register number is stored in the program, analyze the register allocation table created when the register number is allocated by the optimization unit of the compiler It is necessary to create a range table.

The effective range table can be easily created from the register allocation table. Usually, a compiler generates a data flow graph or a dependency graph from a source program. And using this graph,
Registers are allocated to hold data of a variable or data showing an intermediate result of a temporary operation. Here, conventionally, a register is registered in an allocation table when a variable appears, and an entry is deleted from the register allocation table for a variable determined to be unnecessary from the data flow graph or the dependency graph. As a result, the data held in the register of a certain register number is in the range of valid addresses, that is, the valid data is written by writing a load instruction or operation result, and then the last data that requires that data. The valid period until the calculation instruction or the store instruction of appears appears.

When assigning register numbers, for example, if there is a source program of c = a + b c = c * d, a: register 0 b: register 1 c: register 2 d: register 3 May be defined as (1) add r0, r1, r2 mul r2, r3, r2, but only c as a multiplication result is registered in the register 5
May be stored in, that is, (2) add r0, r1, r2 mul r2, r3, r5. In this case, a plurality of register numbers will be assigned to the variable c of the source program. Conventionally, as in the above program (1), for example, S
Unless the register has a special meaning or function like the global register in the PARC register window, avoid allocation to multiple register numbers if it is not necessary to save data from the register due to register resource problems. ing. On the other hand, in this embodiment, allocation to a plurality of registers is performed as in the above program (2). As a result, the evaluation range of the evaluation target can be divided, so that the evaluation range can be narrowed and the evaluation target can be increased. on the other hand,
If a register has a special meaning and function as described above, it cannot be allocated to a register having the same function as the originally allocated register, so that the selection range becomes narrow and caution is required.

After the effective range table is created, the Hamming distance is obtained for the register number of interest, and another assignable register number is reallocated. When performing this reassignment, it is possible to divide the evaluation range by attempting to assign more registers.

In this embodiment, it is also possible to evaluate a plurality of register numbers at the same time. If the number of register numbers to be evaluated at the same time is limited to one, the number of register numbers that can be replaced is limited. However, by simultaneously evaluating a plurality of register numbers, these multiple register numbers can be replaced with each other. The replacement can be optimized as a register number.

Further, the step of reallocating the register file may be performed when register allocation is performed by the compiler, or after the allocation is performed once.

Next, a concrete example of the instruction sequence optimizing apparatus of this embodiment will be described with reference to FIGS.

FIG. 18 is a flow chart for explaining the procedure of the optimizing process performed by the instruction sequence optimizing apparatus of this embodiment.

First, an intermediate code (assembly code) is created by compiling a source program created in a high-level language or an assembly language and further performing another optimization process (step S1801). An example of the intermediate code program obtained in this way is shown in FIG.
9 (a).

Next, a register allocation table is prepared, and an effective range table is prepared from this register allocation table (step S1802). FIG. 20 shows the effective range table of the program shown in FIG.

Then, the data of interest in this trial is selected (step S1803), and the register number assigned to this data of interest is replaced with the register number that minimizes the Hamming distance (step S1804). At this time, the Hamming distance of the instruction at the boundary of the effective range is also taken into consideration, and optimization is performed so that the Hamming distance at this boundary is also small.

Here, consider a case where the data assigned to the register number 0x1c is the data of interest. From the valid range table of FIG. 20, it can be seen that the valid range of this data is from address 0101 to address 1000. That is, for such data, the addresses 0101 to 1000 may be evaluated. In addition, in the program of FIG.
Although new data is stored in the register number 0x1c by the instruction of 101, it is not evaluated because it is out of the evaluation target.

In the program of FIG. 19A, the sum of the Hamming distances before and after the register number 0x1c is 14. Here, by searching for another register number that minimizes the sum of the Hamming distances, it can be seen that the sum of the Hamming distances can be set to 8 by replacing the register numbers 0 and 2. Here, since the valid ranges of the register number 2 overlap, the register number 0x1c is replaced with the register number 0. As a result, FIG.
The program as shown in (b) can be obtained.

When the replacement of the program is completed, it is then determined whether the optimization has been completed for all the data (step S1805). Then, if there is data that has not been optimized, steps S1803 to S1805 are executed for that data.
On the other hand, if the optimization has been completed for all data, the program after the optimization processing is output and the optimization processing is terminated.

According to this embodiment, the control program optimized as described above is stored in the program memory of the information processing apparatus, and C is stored using this control program.
By controlling the PU or the like, it becomes possible to reduce the power consumption in the instruction bus.

In the present embodiment, the case where both the execution unit and the instruction bus are 32 bits has been described as an example, but the second invention is also applied to the case where addresses of a plurality of words are simultaneously transferred. Of course you can. For example, when transferring at a 4-word boundary, the Hamming distance between the instruction 4 words before and the instruction 4 words after the instruction of interest may be evaluated.

(Third Embodiment) Next, as a third embodiment, the third embodiment will be described.
An embodiment (corresponding to claim 7) of the invention will be described.

In this embodiment, the case where the third invention is applied to the "add" instruction will be described as an example.

When creating an instruction function code, for example, S
Referring to the instruction function code of PARC, the “add” instruction is “000000”, but since this “add” instruction and the like have a very high appearance frequency, in this embodiment, in addition to “000000” "111111" is also "a"
A command system is created so that it becomes the "dd" command. That is, in the information processing device that uses the control program optimized by the command sequence optimizing device of this embodiment, "000".
It is assumed that the instruction decoder of the CPU is configured to decode "000" and "111111" as the "add" instruction, so that the compiler can generate the instruction function code when the object code is created. "000000" or "111111" in the field
You can assign any of Where "ad
If the fields of the instruction function code of the instruction before and after the d "instruction are" 001110 "and" 110110 ", the instruction function code of the" add "instruction is" 00000 ".
The Hamming distance is 7 when "0" is selected.
The Hamming distance when "111111" is selected as the instruction function code of the d "instruction is 5. Therefore, in this case, the compiler selects" 111111 "as the instruction function code of the add" instruction.

Next, a concrete example of the instruction sequence optimizing apparatus of this embodiment will be described with reference to FIGS. 21 and 22.

FIG. 21 is a flow chart for explaining the procedure of the optimizing process performed by the instruction sequence optimizing apparatus of this embodiment.

First, an intermediate code (assembly code) is created by compiling a source program created in a high-level language or an assembly language and further performing another optimization process (step S2101). At this time, the instruction function code of the “add” instruction is “00000
It is assumed to be 0 ".

Next, it is determined whether or not each instruction is an instruction to which the present embodiment is applied, that is, an instruction to which a plurality of instruction function code fields are assigned (here, "ad
It is determined whether or not it is a "d" command (step S21).
02).

If it is determined that the instruction is one to which the present embodiment is applied, a bit pattern (“111111” in this case) that can be replaced is selected for this instruction (step S2103).

Furthermore, for all the bit patterns corresponding to this instruction, the Hamming distances between the preceding and succeeding instructions are calculated and compared with each other to select the bit pattern that minimizes the Hamming distance (step S2104). ). FIG. 22 shows an example of a program that has been optimized for the "add" instruction. In this example, in the "add" instruction that appears earlier, the instruction function code is set to "000000" because the Hamming distance is smaller, so replacement is not performed, and in the "add" instruction that appears later, the instruction function code is set to "111111". Since the Hamming distance is smaller in the case of, the replacement is performed.

When the program replacement is completed,
It is determined whether optimization has been completed for all data (step S2105). Then, if there is data that has not been optimized, steps S2103 to S2105 are executed for that data. On the other hand, if the optimization has been completed for all data, the program after the optimization processing is output and the optimization processing is terminated.

According to this embodiment, the control program optimized as described above is stored in the program memory of the information processing apparatus, and C is stored using this control program.
By controlling the PU or the like, it becomes possible to reduce the power consumption in the instruction bus.

(Embodiment 4) Next, as Embodiment 4, the fourth embodiment
An embodiment (corresponding to claim 8) of the invention will be described.

In the present embodiment, when there are a plurality of implementing methods for performing one type of operation, the instruction relating to the implementing method is selected so that the Hamming distance between the preceding and following instructions is minimized. For example, register 0x0d stores data “0”
In the case of writing, if the register number 0 is meaningless for writing like SPARC but reading is defined as a special register that outputs data “0”, the following implementation methods are available. . Among these implementation methods (that is, instructions), the instruction having the smallest Hamming distance from the preceding and succeeding instructions is selected and the instruction is replaced.

Mov r0, rd (instruction for moving data “0” to 0x0d) add r0, r0, rd (instruction for storing 0 + 0 in 0x0d) mul r? , R0, rd (instruction for storing a value obtained by multiplying 0 by 0x0d) mul r0, r? , Rd (instruction for storing a value obtained by multiplying 0 by 0x0d) xor r? , R? , Rd (instruction to store the result of the exclusive OR of a certain value and the same value in 0x0d) sll r0. r? , Rd (an instruction to store a value obtained by shifting 0 to the right by a certain value in 0x0d) srl r0, r? , Rd (instruction for storing a value obtained by shifting 0 to the left by a certain value in 0x0d) Further, as another specific example, there is an immediate addition instruction. Immediate subtraction with the immediate part as 2's complement to immediate addition is
The calculation functions are exactly the same. For example, a = b + 5 and a = b-(-5) are treated as the same calculation. Here, when the immediate addition and the immediate subtraction are replaced with each other, the field of the instruction representing the immediate data is inverted. Therefore, it may be possible to reduce the Hamming distance by replacing both expressions.

In the present embodiment, in order to select a replacement candidate, for example, a so-called library is prepared in advance, and when a certain instruction is evaluated, it is determined whether or not the replacement candidate is registered in this library. Just search. When the replacement candidate is found as a result of the search, the Hamming distance is compared with the case where the replacement candidate is adopted. Further, in order to replace the immediate addition and the immediate subtraction, the immediate subtraction may be registered in the library as a replacement candidate for the immediate addition. At this time, if the method or procedure for converting the immediate data is also registered in the library, the conversion method / procedure can be obtained by searching the immediate subtraction. For example, it is possible to adopt a procedure in which the instruction field is replaced with immediate subtraction and the immediate data is replaced with data obtained by interpolating 2.
Then, the instruction data obtained by such a procedure is adopted as a comparison target of the Hamming distance. Further, instead of simply searching the library, it may be possible to perform the search when it is possible after determining whether or not the search is possible.

Next, a concrete example of the instruction sequence optimizing apparatus of this embodiment will be described with reference to FIGS. 23 and 24.

FIG. 23 is a flow chart for explaining the procedure of the optimizing process performed by the instruction sequence optimizing apparatus of this embodiment.

First, an intermediate code (assembly code) is created by compiling a source program created in a high-level language or an assembly language and further performing another optimization process (step S2301).

Next, it is determined whether or not each instruction is an instruction to which the present embodiment is applied, that is, whether or not a replacement candidate is registered in the library (step S2302).

If it is determined that the instruction is one to which the present embodiment is applied, the library is searched to select a replaceable instruction (step S2303). Also,
At this time, the instruction operation may be analyzed to generate an equivalent instruction.

Further, for the instruction to which this embodiment is applied and the instruction retrieved by the library, the Hamming distance between the instruction before and after the instruction is calculated. Then, by comparing the respective calculation results with each other, the instruction that minimizes the Hamming distance is selected (step S2304). In FIG. 24, (a) is a program example before the optimization according to the present embodiment, and (b) is a program example after the optimization. By replacing the "addi" instruction (immediate addition instruction) with the "subi" instruction (immediate subtraction instruction) in the figure, the Hamming distance between the preceding and succeeding instructions can be reduced from 26 to 20.

When the replacement of the instruction is completed, it is then determined whether or not the optimization is completed for all the data (step S2305). Then, if there is data that has not been optimized, steps S2303 to S2305 are executed for that data. On the other hand, if optimization has been completed for all data,
The program after the optimization processing is output, and the optimization processing ends.

According to this embodiment, the control program optimized as described above is stored in the program memory of the information processing apparatus, and C is stored using this control program.
By controlling the PU or the like, it becomes possible to reduce the power consumption in the instruction bus.

(Fifth Embodiment) Next, as a fifth embodiment, the fifth embodiment will be described.
An embodiment (corresponding to claim 9) of the invention will be described.

In the present embodiment, when there are a plurality of implementation methods for performing one type of operation, the instructions relating to the implementation method are replaced so that the functional blocks that operate are small and the power consumption is small. That is, considering variations in data lines, power consumption of functional blocks used, etc.,
Instructions are replaced so that the total power consumption is minimized. As a replacement method, a library can be used as in the case of the above-described fourth embodiment. For example, when writing data “0” to register 0x0d,
Table 1 shows the relationship between the adopted instructions and the functional blocks used.
become that way. Of these instructions, the one with the lowest power consumption is selected and the instruction is replaced.

[0117]

[Table 1] Next, a specific example of the instruction sequence optimizing apparatus of this embodiment will be described with reference to FIG.

FIG. 25 is a flow chart for explaining the procedure of the optimizing process performed by the instruction sequence optimizing apparatus of this embodiment.

First, an intermediate code (assembly code) is created by compiling a source program created in a high-level language or an assembly language and further performing another optimization process (step S2501).

Then, it is determined whether or not each instruction is an instruction to which the present embodiment is applied, that is, whether or not the replacement candidate is registered in the library (step S2502).

If it is determined that the instruction is one to which the present embodiment is applied, the library is searched to select an instruction that can be replaced (step S2503). Also,
At this time, the instruction operation may be analyzed to generate an equivalent instruction.

Furthermore, the power consumption of the instructions to which the present embodiment is applied and the instructions retrieved by the library are calculated. Then, by comparing the respective calculation results with each other, the instruction having the lowest power consumption is selected (step S2504).

When the replacement of the instruction is completed, it is then determined whether or not the optimization is completed for all the data (step S2505). Then, if there is data that has not been optimized, steps S2503 to S2505 are executed for that data. On the other hand, if optimization has been completed for all data,
The program after the optimization processing is output, and the optimization processing ends.

According to this embodiment, the control program optimized as described above is stored in the program memory of the information processing apparatus, and C is stored using this control program.
By controlling the PU or the like, it becomes possible to reduce the power consumption in the instruction bus.

[0125]

As described in detail above, according to the present invention, an instruction sequence optimizing device capable of performing an optimizing process for reducing power consumption at the stage of creating a control program for an information processing device. Can be provided.

[Brief description of drawings]

FIG. 1 is a flowchart schematically showing the concept of the first embodiment.

FIG. 2 is a flowchart showing an example in which FIG. 1 is embodied.

FIG. 3 is a diagram showing an example of a program optimized by the instruction sequence optimizing apparatus according to the first embodiment.

FIG. 4 is a diagram showing an assembly source program list obtained by compiling the program shown in FIG.

5 is a diagram showing an assembly source program list obtained by compiling the program shown in FIG.

6 is a diagram showing an assembly source program list obtained by compiling the program shown in FIG.

7 is a diagram showing an assembly source program list obtained by compiling the program shown in FIG.

FIG. 8 is a directed graph showing the analysis result of the dependency relationship of the basic blocks in FIG.

9 is a directed graph showing an analysis result of dependency relationships of the basic blocks in FIG.

10 is a diagram showing a bit pattern of a basic block in FIG.

FIG. 11 is a diagram showing a bit pattern after optimization processing according to the first embodiment.

FIG. 12 is a reference diagram showing a bit pattern for explaining the effect of the optimization processing according to the first embodiment.

FIG. 13 is a flowchart for explaining a modified example of the first embodiment.

14A and 14B are conceptual diagrams showing an example of the configuration of an apparatus that uses the program optimized in the first embodiment.

15 (a) and 15 (b) are diagrams showing a bit pattern of a program used in the device shown in FIG.

16A is a conceptual diagram showing a configuration example of an apparatus using the program optimized in the first embodiment, and FIG. 16B is a bit pattern of the program used in the apparatus shown in FIG. FIG.

FIG. 17 is a conceptual diagram showing a configuration example of an apparatus using the program optimized in the first embodiment.

FIG. 18 is a flowchart illustrating a procedure of an optimization process performed by the instruction sequence optimization device according to the second exemplary embodiment.

19A is a diagram showing a program example of an intermediate code used in the optimization processing performed by the instruction sequence optimizing apparatus of the second embodiment, and FIG. 19B shows a result of optimizing the program of FIG. It is a figure.

20 is a diagram showing an effective range table of the program shown in FIG.

FIG. 21 is a flow chart for explaining a procedure of optimization processing performed by the instruction sequence optimization device of the third embodiment.

FIG. 22 is a diagram showing a program in which the optimization processing of the third embodiment is performed for the “add” instruction.

FIG. 23 is a flowchart for explaining a procedure of optimization processing performed by the instruction sequence optimization device of the fourth embodiment.

24A is a diagram showing an example of a program before optimization according to the fourth embodiment, and FIG. 24B is a diagram showing a program after optimization of the program of FIG.

FIG. 25 is a flowchart illustrating a procedure of optimization processing performed by an instruction string optimization device according to a fifth exemplary embodiment.

FIG. 26 is a block diagram showing a schematic configuration of a control unit of the portable information processing device.

[Explanation of symbols]

2610 CPU 2611 Execution unit 2612 I / O unit 2613 register section 2620 Program memory 2621 Storage 2631 address bus 2632 instruction bus

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-5-135187 (JP, A) JP-A-5-250269 (JP, A) JP-A-5-165727 (JP, A) JP-A-8- 101773 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 9/45 G06F 1/32

Claims (7)

(57) [Claims] 1. An instruction sequence optimization for optimizing the program for use by an information processing apparatus having a program memory for storing the program and an arithmetic processing unit for fetching the program from the program memory via an instruction bus. In the apparatus, for each instruction that constitutes the program, an instruction sequence analysis unit that analyzes mutual dependency relations, and the order of the instructions is changed within a range that does not affect the dependency relation analyzed by the instruction sequence analysis unit. As a result, when the instruction is transferred from the program memory to the arithmetic processing unit, an instruction string changing unit that reduces a Hamming distance between bit strings appearing on the instruction bus, and the program after dividing the program into basic blocks. Basic
Block division means for sending a block to the instruction sequence analysis means
When provided with a said instruction sequence changing means, performing an instruction sequence determination processing immediately before
Last bit sequence of basic block and current instruction order
Between the first bit string of the basic block that performs constant processing
Order within this block, taking into account the Hamming distance of
An instruction sequence optimizing device characterized by performing an order determination process . 2. When the instruction includes the bit string that is not considered when the program is executed by the arithmetic processing unit, the bit string is reduced so that the Hamming distance between the bit string and the bit string before and after the bit string is reduced. 2. The instruction sequence optimizing apparatus according to claim 1, wherein the signal value of is changed. 3. A plurality of registers for temporarily storing data, a program memory for storing a program, and an operation for writing / reading data to / from the register according to an instruction fetched from the program memory via an instruction bus. In an instruction sequence optimizing apparatus for optimizing a program for use by an information processing apparatus including a processing unit, register number recognizing means for recognizing a register number in each instruction constituting the program, and the register number Register valid range recognition means for recognizing the valid range of the register number recognized by the recognition means, and changing the register number within a range that does not affect the valid range recognized by the register valid range recognition means, An instruction including the register number is issued from the program memory to the arithmetic processing unit. Instruction sequence optimization apparatus being characterized in that and a instruction sequence changing means for reducing the Hamming distance bit Retsukan appearing on the instruction bus when transferring the part. 4. A register number that the instruction sequence changing means can replace, with respect to each register number recognized by the register number recognizing means, without affecting the valid range recognized by the register valid range recognizing means. A formulating means for formulating, and a selecting means for selecting, among the register numbers recognized by the register number recognizing means and the register numbers formulated by the formulating means, a register number having the smallest Hamming distance between bit strings appearing on the instruction bus. 4. The instruction sequence optimizing apparatus according to claim 3 , further comprising: a replacing unit that replaces a register number in the program with a register number selected by the selecting unit. 5. An instruction sequence optimization for optimizing the program for use by an information processing apparatus having a program memory for storing the program and an arithmetic processing unit for fetching the program from the program memory via an instruction bus. In the device, with respect to some or all of the respective instructions that form the program, a storage unit that stores another bit pattern that means the same instruction, and replaces the instruction in the program with the bit pattern stored in the storage unit. The instruction sequence changing means for reducing the hamming distance between the bit sequences appearing on the instruction bus when the instruction is transferred from the program memory to the arithmetic processing unit. Device. 6. An instruction sequence optimization for optimizing the program for use by an information processing apparatus having a program memory for storing the program and an arithmetic processing unit for fetching the program from the program memory via an instruction bus. In the apparatus, a selecting unit that selects another instruction or instruction sequence that can obtain the same processing result for the instruction or instruction sequence in the program, and the instruction or instruction sequence in the program is selected by the selecting unit. By substituting an instruction or sequence of instructions,
An instruction sequence changing means for reducing a Hamming distance between bit sequences appearing on the instruction bus when the instruction or the instruction sequence is transferred from the program memory to the arithmetic processing unit; apparatus. 7. An instruction sequence optimization for optimizing the program for use by an information processing apparatus having a program memory for storing the program and an arithmetic processing unit for fetching the program from the program memory via an instruction bus. In the apparatus, for the instruction or instruction sequence in the program, a selection unit that selects another instruction or instruction sequence that can obtain the same processing result, and an instruction or instruction sequence in the program and the selection unit Regarding an instruction or an instruction string, an arithmetic means for trial-calculating the power consumption in the instruction bus when the instruction or the instruction string is transferred from the program memory to the arithmetic processing unit, and the instruction or the instruction string selected by the selecting means Of the instructions or instruction sequences in the program, the power consumption calculated by the computing means Remote small ones, and the instruction sequence changing means for replacing the instruction or instruction sequence in the program, the instruction sequence optimization device characterized by comprising a.