JP2006004123A - Optimization device, optimization method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optimization device, an optimization method and a program capable of reducing the power consumption of a computer system by arresting bit transition of data outputted to a bus. <P>SOLUTION: This program inputs a command code string just before and a command code string to generate, calculates the bit transition numbers of the command code string just before and the command code string to generate, rearranges the alignment of command codes of the command code string to generate according to the calculated bit transition number, and outputs the command code string just before and the command code string to generate. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an optimization device, an optimization method, and a program, and more particularly, to an optimization device, an optimization method, and a program for optimizing an instruction code executed in a computer system that can process a plurality of instructions in parallel.

  2. Description of the Related Art In recent years, computer systems (computer systems) that are smaller than computers such as portable notebook personal computers and personal digital assistants and that have higher processing speed have become widespread. Such downsizing and speeding up of computer systems have been realized by miniaturizing semiconductor processes and increasing the operating frequency of circuits, etc., but with this, the power consumption of computer systems has increased. Reduction of this is strongly desired.

  FIG. 8 shows a configuration of a general computer system. As shown in the figure, the computer system 800 includes an instruction memory 801, an instruction decoder 802, a data memory 803, and an arithmetic unit 804. The instruction memory 801 and the instruction decoder 802 are connected via an instruction bus 805, and the data memory 803 and the arithmetic unit 804 are connected via a data bus 806.

  The instruction memory 801 stores an execution code in advance. This execution code is a code that can be executed by the computer system 800, and instruction codes are arranged in the execution order.

  For example, when execution code processing is executed, first, instruction codes included in the execution code are sequentially transferred from the instruction memory 801 to the instruction decoder 802 via the instruction bus 805. Next, the instruction decoder 802 decodes the instruction code transferred from the instruction memory 801, and outputs a control signal and an access address to the data memory 803 to the data memory 803 and the arithmetic unit 804. Next, the arithmetic unit 804 reads data from the data memory 803 via the data bus 806 in accordance with the control signal and access address from the instruction decoder 802, performs a predetermined operation, and outputs the operation result to the data via the data bus 806. Write to memory 803. Thus, the instruction code of the execution code is executed.

  In such a computer system, an instruction code is transferred from the instruction memory 801 to the instruction decoder 802 every clock cycle, and power (switching power) is generated in a switching circuit that outputs a signal to the instruction bus 805 when the instruction code is transferred. Will be consumed. Generally, the power consumption of a switching circuit that outputs a signal to a bus is proportional to the number of times of switching due to bit transition (bit inversion) of data to be transferred.

  Thus, for example, Patent Documents 1 and 2 are known as methods for suppressing bit transition of data to be transferred and reducing power consumption. In Patent Document 1, the data previously output to the bus is stored inside the computer system, and in the case of an instruction that does not use the bus, such as a NOP instruction, the stored previous data is stored in the bus. The power consumption is reduced by outputting and maintaining the state of the bus.

  Also, in Patent Document 2, in an apparatus that generates an execution code of a computer system, when a plurality of instruction codes are assigned to one instruction and an instruction code is generated, the number of bit transitions is compared with the immediately preceding instruction code. By selecting and generating one instruction code from among a plurality of assigned instruction codes so that (number of inverted bits) is reduced, the power consumption when this instruction code is executed in the computer system is reduced. Yes.

  However, the method of Patent Document 1 requires a new circuit for storing data in the computer system, a circuit for switching output to the bus, and the like. Further, in the method of Patent Document 2, since a plurality of codes are assigned to one instruction, the instruction bit width increases, the bus width of the instruction bus, the bus switching circuit, etc. increase, or the conversion table of the instruction decoder Etc. will increase. That is, in these methods, since the configuration of hardware and the like is made redundant, there is a problem that power consumption is increased as a result.

  On the other hand, a multiprocessor system is known that simultaneously uses a plurality of processors (calculators) to improve the processing capacity of a computer system. As a processing method of the multiprocessor system, MIMD (Multiple Instrucion / Multiple Data) in which a plurality of processors process a plurality of different data in parallel is mainly adopted.

  In a compiler that generates object code for a multiprocessor system, scheduling is performed so that different instruction codes are processed in parallel in each processor. The compiler also performs optimizations such as inserting a NOP instruction to synchronize instructions and threads, and replacing instruction slots of instructions that are processed in parallel within the same cycle depending on data dependency. ing.

In such a multiprocessor system, since the instruction code is transferred from the instruction memory to the instruction decoder via the instruction bus for each of the plurality of processors, the increase in power consumption of the bus as described above becomes a greater problem.
Japanese Patent Laid-Open No. 4-151755 Japanese Patent Laid-Open No. 9-62422

  As described above, in a computer system such as a conventional multiprocessor system, if the bit transition of data output to the bus is reduced, it is necessary to make the configuration of hardware etc. redundant, which increases power consumption. was there.

  The present invention was made to solve such problems, and the object of the present invention is to suppress bit transition of data output to the bus without making the configuration of hardware or the like redundant, It is to reduce the power consumption of the computer system.

  A program according to the present invention is a program for causing a computer to execute a process for optimizing an instruction code executed by a computer system (computer system) capable of processing a plurality of instructions in parallel. The process is executed in parallel. A plurality of instruction codes to be executed in parallel and a second instruction code string to be executed next to the first instruction code string; Calculating the number of bit transitions between the first instruction code string and the second instruction code string, and rearranging the instruction code array of the second instruction code string according to the calculated bit transition number; The first instruction code string and the rearranged second instruction code string are output. This makes it possible to suppress bit transitions of data output to the bus without making the hardware configuration redundant, thereby reducing the power consumption of the computer system.

  In the above program, the rearrangement may rearrange the instruction code array of the second instruction code string so that the calculated number of bit transitions is minimized. Thereby, the power consumption of the computer system can be further reduced.

  In the above-described program, the rearrangement prepares a first arrangement pattern which is an instruction code arrangement of a second instruction code string, and a second arrangement pattern different from the first arrangement pattern, The number of bit transitions according to the first array pattern is compared with the number of bit transitions according to the second array pattern, an array pattern with a small number of bit transitions is determined, and the output is when the number of bit transitions is small The second instruction code sequence including the determined first or second arrangement pattern may be output. Thereby, the power consumption of a computer system can be reduced effectively.

  In the above-described program, the rearrangement may change the instruction code arrangement by changing the assignment of instruction slots to instruction codes included in the second instruction code string. Thereby, the power consumption of a computer system can be reduced efficiently.

  The above-mentioned program has the first instruction code according to a thread number between the first instruction code included in the first instruction code string and the second instruction code included in the second instruction code string. And the second instruction code may be interchanged. Thereby, the power consumption of the computer system can be further reduced.

  An optimization method according to the present invention is an optimization method for optimizing an instruction code executed in a computer system capable of processing a plurality of instructions in parallel, and is a first method in which a plurality of instruction codes to be executed in parallel are arranged. A plurality of instruction codes to be executed in parallel with the first instruction code string, and a second instruction code string to be executed next to the first instruction code string, and the first instruction code string and the second instruction code string are input. The number of bit transitions with respect to the instruction code sequence of the second instruction code sequence is rearranged in accordance with the calculated number of bit transitions, and the first instruction code sequence and the rearrangement are rearranged. The second instruction code is output. This makes it possible to suppress bit transitions of data output to the bus without making the hardware configuration redundant, thereby reducing the power consumption of the computer system.

  An optimization device according to the present invention is an optimization device that optimizes an instruction code executed in a computer system capable of processing a plurality of instructions in parallel, and is a first in which a plurality of instruction codes to be executed in parallel are arranged. A plurality of instruction codes to be executed in parallel with the instruction code string, and an input unit for inputting a second instruction code string to be executed next to the first instruction code string; and the first instruction code string; A calculation unit that calculates the number of bit transitions with the second instruction code sequence, and a rearrangement unit that rearranges an instruction code array of the second instruction code sequence according to the calculated number of bit transitions; And an output unit that outputs the first instruction code string and the rearranged second instruction code. This makes it possible to suppress bit transitions of data output to the bus without making the hardware configuration redundant, thereby reducing the power consumption of the computer system.

  According to the present invention, an optimization device, an optimization method, and an optimization method capable of suppressing bit transition of data output to a bus and reducing power consumption of a computer system without making a hardware configuration redundant. A program can be provided.

Embodiment 1 of the Invention
First, the configuration of the computer system according to the first embodiment of the present invention will be described with reference to FIG. The computer system 100 is a system that can execute a plurality of instructions in parallel, and is, for example, a MIMD multiprocessor system. The computer system 100 may be a one-chip microcomputer or may be composed of a plurality of chips.

  As shown in the figure, the computer system 100 includes an instruction memory 101, instruction decoders 102a and 102b, a data memory 103, and arithmetic units 104a and 104b. The instruction memory 101 and instruction decoders 102a and 102b are connected via instruction buses 105a and 105b, respectively. The data memory 103 and the arithmetic units 104a and 104b are connected via data buses 106a and 106b, respectively.

  In this example, two instruction decoders and two arithmetic units are provided and two instructions can be executed in parallel. However, any other number of instruction decoders and arithmetic units may be provided. In this example, one instruction memory and one data memory are provided, but the same number of instruction memories and data memories as the instruction decoder and the arithmetic unit may be provided.

  The instruction memory 101 stores an execution code generated by the program optimization device 110. This execution code is stored in the instruction memory 101 via the instruction buses 105a and 105b by, for example, an input / output circuit (not shown) or directly written in the instruction memory 101 by a writer as a memory writing device.

  In the execution code, an instruction code sequence that can be executed in parallel in the computer system 100 is arranged in the execution order. This instruction code string has instruction slots corresponding to the number of processors (operation units), and one instruction code is assigned to one instruction slot. In this example, the instruction code string includes two instruction slots, that is, two instruction codes.

  For example, when execution code processing is executed, first, an instruction code string of execution code stored in the instruction memory 101 is fetched according to an address indicated by a program counter (not shown). The instruction code of one instruction slot of the instruction code string is transferred from the instruction memory 101 to the instruction decoder 102a via the instruction bus 105a, and the instruction code of the other instruction slot is transferred from the instruction memory 101 to the instruction decoder 102b via the instruction bus 105b. Transferred through. The present embodiment is characterized in that when the instruction code is fetched from the instruction memory as described above, the bit transition of the instruction code is suppressed and the power consumption of the instruction buses 105a and 105b is reduced.

  Next, the instruction decoder 102a decodes the transferred instruction code, and outputs a control signal and an access address to the data memory 103 to the data memory 103 and the arithmetic unit 104a. Similarly, the instruction decoder 102b outputs a control signal and an access address to the data memory 103 to the data memory 103 and the arithmetic unit 104b.

  Next, the arithmetic unit 104a reads data from the data memory 103 via the data bus 106a in accordance with the control signal and access address from the instruction decoder 102a, performs a predetermined operation, and outputs the operation result to the data via the data bus 106a. Write to the memory 103. Similarly, the calculator 104 b reads data from the data memory 103, performs a predetermined calculation, and writes the calculation result to the data memory 103. In this way, the instruction code sequence of the execution code is executed in parallel.

  Next, the configuration of the program optimization apparatus according to the present embodiment will be described using the block diagram of FIG. The program optimizing device 110 is an apparatus that generates an execution code by optimizing an object code obtained by compiling a source code such as a high-level language so that power consumption of a computer system that executes the code is reduced. is there.

  The program optimization apparatus 110 is configured by a computer system such as a personal computer or a server computer, and each block in the drawing is configured by hardware or software executed on the hardware. The program optimizing device 110 can be configured by a plurality of computers, not a single computer. For example, the compiler 111, the optimization unit 112, and the linker 113 may be separate devices, or the compiler 111 and the optimization unit 112 may be the same device, and the linker 113 may be separate devices. In this example, the optimization unit 112 is a separate block from the compiler 111 and the linker 113, but the optimization unit 112 may be built in the compiler 111 and the linker 113.

  As shown in the figure, the program optimization apparatus 110 includes a compiler 111, an optimization unit 112, a linker 113, a source code storage unit 114, an object code storage unit 115, an optimization code storage unit 116, and an execution code storage unit 117. I have. In addition, the program optimizing device 110 includes an input unit such as a keyboard and a mouse (not shown) and a display unit such as a CRT and an LCD, and inputs information from a user as necessary, execution results of each process, and the like. Can be displayed to the user.

  The compiler 111 and the linker 113 can be configured by, for example, a CPU or the like executing processing according to an application program stored in a storage device and cooperating with other hardware configurations. The source code storage unit 114, the object code storage unit 115, the optimization code storage unit 116, and the execution code storage unit 117 can be configured by an internal storage unit such as a hard disk or an external storage unit such as an optical disk. The configuration of the optimization unit 112 will be described later.

  The source code storage unit 114 stores source code written in a high-level language or the like. The source code is described in a high-level language such as C language or C ++ language, but is not limited thereto, and may be described in assembler language or the like. For example, the source code is input by the user via the input unit and stored in advance in the source code storage unit 114.

  The compiler 111 inputs the source code stored in the source code storage unit 114 and compiles it to generate an object code. For example, the compiler 111 generates assembler language assembler code based on the input source code, and converts the assembler code into machine language to generate object code. During this compilation, instruction codes that can be executed in parallel in the computer system 100 are scheduled, and instruction code strings are generated in the order of execution. The object code storage unit 115 stores the object code generated by the compiler 111. In this object code, an instruction code sequence that can be executed in parallel by the computer system 100 is described in the order of execution as described above.

  The optimization unit 112 inputs the object code stored in the object code storage unit 115, optimizes this so that the power consumption of the computer system 100 is reduced, and generates an optimization code. As will be described later, the optimization unit 112 rearranges the instruction codes so that the number of bit transitions in the instruction code string of the object code is smaller than that in the immediately preceding instruction code string. The optimization code storage unit 116 stores the optimization code generated by the optimization unit 112.

  The linker 113 receives the optimized code stored in the optimized code storage unit 116 and links it to generate an execution code. For example, the linker 113 generates an execution code by combining a plurality of optimization codes, calling a referenced library, and the like. The linker 113 can also link the object code generated by the compiler 111, and can also link the object code and the optimized code. The execution code storage unit 117 stores an execution code generated by the linker 113. The execution code is a code that can be directly executed by the computer system 100 and is also called a load module.

  Next, the configuration of the optimization unit of the program optimization apparatus according to the present embodiment will be described with reference to FIG. As described above, the optimization unit 112 is a block that optimizes the object code so that the power consumption of the computer system 100 is reduced.

  As shown in the figure, the optimization unit 112 includes an input unit 301, an instruction slot allocation unit 302, a bit transition number calculation unit 303, a bit transition number comparison / determination unit 304, an output unit 305, and an immediately preceding instruction code string storage unit. 306, a minimum bit transition number storage unit 307, and an instruction code string storage unit 308 for the minimum bit transition number.

  The input unit 301, the instruction slot allocation unit 302, the bit transition number calculation unit 303, the bit transition number comparison / determination unit 304, and the output unit 305 are similar to the compiler 111 in FIG. It is configured by cooperating with the wear. The immediately preceding instruction code string storage unit 306, minimum bit transition number storage unit 307, and minimum bit transition number instruction code string storage unit 308 are similar to the source code storage unit 114 in FIG. Consists of.

  The input unit 301 inputs an instruction code sequence in order from the object code stored in the object code storage unit 115. For example, the input unit 301 may read and acquire the instruction code sequence from the object code storage unit 115 one by one, or after reading the entire object code, acquire the instruction code sequence one by one. May be. In this example, the instruction code string “00110000,00011011” is input.

  The instruction slot assigning unit 302 assigns the instruction code string input by the input unit 301 to the instruction slot. That is, an instruction code array pattern of the instruction code string is prepared, and an array pattern obtained by rearranging the patterns is prepared. For example, first, the input instruction code string is assigned to the instruction slot, and next, the instruction code is replaced and assigned to the instruction slot. For example, the pattern of the instruction code string is first “00110000,00011011” and then “00011011 00110000”.

  The bit transition number calculation unit 303 (calculation unit) calculates the number of bit transitions between the instruction code sequence to which the instruction slot is allocated by the instruction slot allocation unit 302 and the immediately preceding instruction code sequence. The number of bit transitions is the number of bits in which the polarity of 1 and 0 of the code is inverted. That is, the number of bits that differ between codes. For example, the number of bit transitions between “00010011, 00010001” and “00011011 and 00110000” is “3”.

  The bit transition number comparison / determination unit 304 compares the bit transition number calculated by the bit transition number calculation unit 303 with the minimum bit transition number so far, and determines the smaller one as the minimum bit transition number. The output unit 305 outputs an instruction code string having the minimum number of bit transitions as an optimized code to the optimized code storage unit 116. For example, the output unit 305 may sequentially output the instruction code sequence determined to be the minimum number of bit transitions for each instruction code sequence, or may output the instruction code sequences of all object codes collectively. In this example, “00011011 and 00110000” are output.

  The immediately preceding instruction code string storage unit 306 stores the immediately preceding instruction code string output by the output unit 305. The immediately preceding instruction code string is an instruction code string immediately before the instruction code string being processed by the optimization unit 112. In this example, “00010011” is stored in the instruction slot 1 and “00010001” is stored in the instruction slot 2.

  The minimum bit transition number storage unit 307 stores the minimum bit transition number determined by the bit transition number comparison / determination unit 304. In this example, “3” is stored as the minimum number of bit transitions. The instruction code string storage unit 308 with the minimum number of bit transitions stores the instruction code string with the minimum number of bit transitions determined by the bit transition number comparison / determination unit 304. In this example, “00011011” is stored in the instruction slot 1, and “00110000” is stored in the instruction slot 2.

  Next, the program optimization process according to the present embodiment will be described with reference to FIGS. FIG. 4 is a flowchart showing the program optimization process, and FIG. 5 shows an example of data used in the program optimization process. This process is a process in the optimization unit 112 of the program optimization apparatus 110, and is executed by a predetermined application program in the CPU or the like, for example.

  First, it is determined whether there is an immediately preceding instruction code string (S401). In the input unit 301, the instruction code string of the object code stored in the object code storage unit 115 is input in order from the top, and processing is performed. An instruction code string that is currently input and subjected to optimization processing is referred to as an “instruction code string that is about to be generated”.

  For example, when an instruction code string is input, the input unit 301 refers to the immediately preceding instruction code string storage unit 306 and determines whether there is an immediately preceding instruction code string. In the example of FIG. 5, “00010001” is stored in the instruction slot 1 and “00011111” is stored in the instruction slot 2 of the immediately preceding instruction code string storage unit 306, and it is determined that there is an immediately preceding instruction code string.

  If it is determined in S401 that there is an immediately preceding instruction code string, the instruction code string that is about to be generated is optimized by the processes in and after S402. If it is determined in S401 that there is no immediately preceding instruction code string, the instruction code string to be generated is output as it is without being rearranged by optimization in the process of S408. At this time, the instruction code string to be generated is stored in the instruction code string storage unit 308 having the minimum number of bit transitions for output as it is in S408.

  Next, the instruction code string to be generated is assigned to the instruction slot (S402). The instruction slot allocation unit 302 allocates an instruction code included in the instruction code string to be generated to the instruction slot. That is, an instruction code array pattern of an instruction code string is prepared. This assignment is repeated in order to obtain the optimum combination of instruction code strings, and finally the instruction code strings of all combinations are assigned.

  It is only necessary that the instruction code strings are finally assigned to all combinations. First, the input instruction code strings may be assigned as they are, or may be switched in an arbitrary order. In the example of FIG. 5A, “00011110” is assigned to the instruction slot 1 and “00010001” is assigned to the instruction slot 2 as the instruction code string to be generated.

  Next, the number of bit transitions between the instruction code string to be generated and the immediately preceding instruction code string is calculated (S403). The bit transition number calculation unit 303 compares each instruction code with respect to the instruction code string assigned to the instruction slot in S402 and the immediately preceding instruction code string stored in the immediately preceding instruction code string storage unit 306, and compares the number of bit transitions. Calculate

  For example, the bit transition number calculation unit 303 calculates the exclusive OR of each instruction code and adds up the number of bits for which the exclusive OR is 1. The number of bit transitions may be calculated for each instruction code, a plurality of instruction codes may be collected, or the entire instruction code string may be calculated. In the example of FIG. 5A, the bit transition number of the instruction code in the instruction slot 1 is “4”, the bit transition number of the instruction code in the instruction slot 2 is “3”, and the total number of bit transitions is “7”. Become.

  Next, the number of bit transitions so far is compared (S404), and it is determined whether the number of bit transitions is smaller than the number of minimum bit transitions so far (S405). The bit transition number comparison / determination unit 304 compares the bit transition number calculated in S403 with the minimum bit transition number stored in the minimum bit transition number storage unit 307, and determines the magnitude relationship.

  When it is determined that the calculated number of bit transitions is smaller than the minimum number of bit transitions so far, the minimum bit transition number storage unit 307 is updated by the process of S406, and the calculated number of bit transitions is the minimum number thus far If it is determined that it is not smaller than the number of bit transitions (greater than or equal to the minimum number of bit transitions), the combination of the next instruction code sequence is not performed by updating the minimum number of bits transition storage unit 307 and the process of S407 Is calculated.

  Next, the minimum number of bit transitions is updated, and an instruction code string that minimizes the number of bit transitions is stored (S406). The comparison / determination unit 304 stores, in the minimum bit transition number storage unit 307, the bit transition number calculated in S403 and determined as the minimum bit transition number in S405. Further, the comparison / determination unit 304 stores the instruction code string having the number of bit transitions, that is, the instruction code string allocated in S402 and the number of bit transitions calculated in S403 in the instruction code string storage unit 308 having the minimum number of bit transitions. Store.

  In the example of FIG. 5A, when the minimum bit transition number storage unit 307 has not yet stored the minimum bit transition number, it is determined that “7” is the minimum bit transition number, and the minimum bit transition number storage unit 307. Stored in “00011110” is stored in the instruction slot 1 and “00010001” is stored in the instruction slot 2 of the instruction code string storage unit 308 having the minimum number of bit transitions.

  Next, it is determined whether the number of bit transitions has been checked for all combinations of instruction code strings (S407). In S402 to S406, the comparison / determination unit 304 assigns the instruction slot sequence to be generated to the instruction slots in all combinations, and determines whether the bit transition number is calculated or compared.

  If it is determined that the number of bit transitions has been checked for all combinations of instruction code strings, an instruction code string is output by the processing of S408. If it is determined that the number of bit transitions is not inspected for all combinations of instruction code strings, the processing after S402 is performed again, rearranged into the remaining combinations, and the number of bit transitions is calculated.

  In the example of FIG. 5, since there are remaining combinations after the process of FIG. 5A, the process of FIG. 5B is performed. In FIG. 5B, “00010001” is assigned to instruction slot 1 and “00011110” is assigned to instruction slot 2 as the instruction code string to be generated, that is, the instruction codes in instruction slot 1 and instruction slot 2 are rearranged. Yes. The number of bit transitions in this instruction code string is “1”. When “7” is stored in the minimum bit transition number storage unit 307, “1” is smaller, so “1” is stored in the minimum bit transition number storage unit 307, and the instruction of the minimum bit transition number is stored. The code string storage unit 308 stores instruction slot 1 “00010001” and instruction slot 2 “00011110”.

  Next, an instruction code string that minimizes the number of bit transitions is output, and the immediately preceding instruction code string is updated (S408). In S401 to S407, the output unit 305 outputs the instruction code string stored in the instruction code string storage unit 308 having the minimum number of bit transitions to the optimization code storage unit 116 as an optimization code. Then, the output unit 305 stores the output instruction code string in the immediately preceding instruction code string storage unit 306.

  In the example of FIG. 5, instruction slot 1 “00010001” and instruction slot 2 “00011110” which are the instruction code strings of FIG. 5B are output, and this instruction code string is stored in the immediately preceding instruction code string storage unit 306. The Then, optimization processing is performed for all instruction codes of the object code, and this processing ends.

  In this way, a computer that executes this instruction code by rearranging the instruction code array so that the bit transition between the instruction code string executed in the previous cycle and the instruction code string executed in the next cycle is reduced. When the instruction code is read out by the system, the bit transition of the instruction code flowing on the bus can be suppressed. Therefore, the power consumption of the instruction bus for transferring the instruction code can be reduced, and the power consumption of the computer system can be reduced. Further, since the instruction code array is rearranged, it is not necessary to provide a redundant hardware configuration in the computer system that executes the instruction code.

Embodiment 2 of the Invention
Next, a program optimization process according to the second embodiment of the present invention will be described using the flowchart of FIG. In the present embodiment, unlike the processing of FIG. 4, the number of bit transitions is calculated and compared at once for all combinations of instruction code strings.

  The computer system that executes the instruction code obtained by this processing, the configuration of the program optimization device that executes this processing, and the like are the same as those in FIGS. This process is a process in the optimization unit 112 of the program optimizing device 110 as in the process of FIG. Also, S601 to S604 and S401 to S404 in FIG. 4 and S605 and S408 in FIG. 4 are the same or similar processes, and description thereof will be omitted as appropriate.

  When an instruction code string is input, it is first determined whether there is an immediately preceding instruction code string (S601). If it is determined that there is an immediately preceding instruction code string, S602 is performed, and the immediately preceding instruction code string is determined. If it is determined that there is no, S605 is performed.

  Next, all combinations of instruction code strings to be generated are assigned to instruction slots (S602). The instruction slot assignment unit 302 obtains all combinations of instruction code strings and assigns instruction slots. That is, all array patterns of instruction codes in the instruction code string are prepared. For example, two instruction code strings shown in FIGS. 5A and 5B are assigned.

  Next, in all combinations of instruction code strings to be generated, the number of bit transitions between the instruction code string and the immediately preceding instruction code string is calculated (S603). The bit transition number calculation unit 303 calculates the number of bit transitions with the immediately preceding instruction code string stored in the immediately preceding instruction code string storage unit 306 for all combinations of instruction code strings assigned in S602. For example, “7” and “1” which are the number of bit transitions in FIGS. 5A and 5B are obtained.

  Next, the number of bit transitions of all combinations of instruction code strings is compared (S604). The bit transition number comparison / determination unit 304 compares the number of bit transitions of the instruction code strings of all combinations calculated in S603, and determines the magnitude relationship. For example, the number of bit transitions “7” and “1” in FIGS. 5A and 5B are compared, and it is determined that “1” is smaller, and the instruction code string in FIG. The instruction code string is the number of bit transitions.

  Next, an instruction code string that minimizes the number of bit transitions is output, and the immediately preceding instruction code string is updated (S605). The instruction code string determined as the minimum number of bit transitions in S601 to S604 is output as an optimization code.

  In this way, it is possible to calculate and compare the number of bit transitions at once for all combinations of instruction code strings, and the same optimized code as in FIG. 4 can be obtained efficiently.

Other Embodiments of the Invention
In the above example, the number of bit transitions of the previous instruction code string and the next instruction code string is sequentially obtained and the instruction codes are rearranged. In addition, the instruction codes are rearranged in consideration of other information. May be. For example, referring to the thread number to which the instruction code belongs, it may be controlled whether to rearrange by the thread number. In the case of the same thread, the instruction code execution order cannot be changed. However, in the case of a different thread, the instruction code execution order can be changed.

  An example of a hardware configuration for realizing the program optimization apparatus 110 described above is shown in FIG. The program optimizing device 110 can use a typical computer system and includes a central processing unit (CPU) 201 and a memory 204.

  The CPU 201 and the memory 204 are connected to a hard disk device 213 as an auxiliary storage device via a bus. Storage medium drive devices such as the flexible disk device 220, hard disk devices 213 and 230, CD-ROM drives 226 and 229, and MO drive 228 are connected via various controllers such as the flexible disk controller 219, IDE controller 225, and SCSI controller 227. Connected to the bus. A portable storage medium such as a flexible disk is inserted into a storage medium driving device such as the flexible disk device 220.

  The storage medium can store a computer program for giving instructions to the CPU 201 and the like in cooperation with the operating system and for executing the functions of the program optimization device 110. The computer program is executed by being loaded into the memory 204. The computer program can be compressed or divided into a plurality of pieces and stored in a storage medium. The hardware configuration typically comprises user interface hardware.

  Examples of user interface hardware include a display device 211 such as a pointing device (mouse 207, joystick, etc.) and a keyboard 206 for inputting, a liquid crystal display for presenting visual data to the user, and a CRT display. There are 212.

  It is also possible to connect a printer via the parallel port 216. This computer system can be connected to a modem via the serial port 215, and is connected to a network via the serial port 215 and the modem or token ring, communication adapter 218, etc., and communicates with other computer systems. It is carried out. In addition, the said structure can be abbreviate | omitted as needed.

It is a hardware block diagram of the computer system concerning this invention. It is a block diagram which shows the structure of the program optimization apparatus concerning this invention. It is a block diagram which shows the structure of the optimization part of the program optimization apparatus concerning this invention. It is a flowchart which shows the program optimization process concerning this invention. It is a figure which shows the example of data used by the program optimization process concerning this invention. It is a flowchart which shows the program optimization process concerning this invention. It is a hardware block diagram of the program optimization apparatus concerning this invention. It is a hardware block diagram of a general computer system.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Computer system 101 Instruction memory 102a, b Instruction decoder 103 Data memory 104a, b Operation unit 105a, b Instruction bus 106a, b Data bus 110 Program optimization apparatus 111 Compiler 112 Optimization part 113 Linker 114 Source code storage part 115 Object code Storage unit 116 Optimization code storage unit 117 Execution code storage unit 301 Input unit 302 Instruction slot allocation unit 303 Bit transition number calculation unit 304 Bit transition number comparison / determination unit 305 Output unit 306 Immediate instruction code string storage unit 307 Minimum bit transition Number storage unit 308 Instruction code string storage unit with minimum bit transition number

Claims (7)

A program for causing a computer to execute a process for optimizing an instruction code executed in a computer system capable of processing a plurality of instructions in parallel,
A first instruction code string in which a plurality of instruction codes to be executed in parallel are arranged and a second instruction code string to be executed next to the first instruction code string in which a plurality of instruction codes to be executed in parallel are arranged are input. And
Calculating the number of bit transitions between the first instruction code string and the second instruction code string;
According to the calculated bit transition number, the instruction code array of the second instruction code sequence is rearranged,
Outputting the first instruction code string and the rearranged second instruction code string;
program. The rearrangement rearranges the instruction code array of the second instruction code string so that the calculated number of bit transitions is minimized.
The program according to claim 1. The sort is
Preparing a first array pattern, which is an instruction code array of a second instruction code string, and a second array pattern different from the first array pattern;
Comparing the number of bit transitions according to the first array pattern with the number of bit transitions according to the second array pattern to determine an array pattern with a small number of bit transitions;
The output outputs the second instruction code string composed of the first or second arrangement pattern determined that the number of bit transitions is small.
The program according to claim 1 or 2. The rearrangement replaces an instruction code array by changing an assignment of an instruction slot to an instruction code included in the second instruction code string.
The program according to any one of claims 1 to 3. The first instruction code and the second instruction code according to a thread number between the first instruction code included in the first instruction code string and the second instruction code included in the second instruction code string. Replace the instruction code,
The program according to any one of claims 1 to 4. An optimization method for optimizing an instruction code executed in a computer system capable of processing a plurality of instructions in parallel,
A first instruction code string in which a plurality of instruction codes to be executed in parallel are arranged and a second instruction code string to be executed next to the first instruction code string in which a plurality of instruction codes to be executed in parallel are arranged are input. And
Calculating the number of bit transitions between the first instruction code string and the second instruction code string;
According to the calculated number of bit transitions, the instruction code array of the second instruction code sequence is rearranged,
Outputting the first instruction code string and the rearranged second instruction code string;
Optimization method. An optimization device that optimizes an instruction code executed in a computer system capable of processing a plurality of instructions in parallel,
A first instruction code string in which a plurality of instruction codes to be executed in parallel are arranged and a second instruction code string to be executed next to the first instruction code string in which a plurality of instruction codes to be executed in parallel are arranged are input. An input unit to
A calculation unit for calculating the number of bit transitions between the first instruction code string and the second instruction code string;
A rearrangement unit for rearranging the instruction code array of the second instruction code string according to the calculated number of bit transitions;
An output unit for outputting the first instruction code string and the rearranged second instruction code string;
An optimization device comprising:

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