JP3385716B2 - Control circuit for synchronous motor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of controlling a synchronous motor, and more particularly to a method of protecting it when it is abnormal.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a control circuit for a conventional synchronous motor. The drive circuit 3 of the synchronous motor 4 is supplied with the clock pulse signal MOTOR CLK-P which defines the rotation speed of the synchronous motor 4 from the reference clock generation circuit 1, and the drive power sources 2 to 26.
A DC voltage of 0V or 140V is supplied. The drive circuit 3 converts the DC voltage into an AC signal for driving the synchronous motor 4 by the MOTOR CLK-P signal, and drives the synchronous motor 4.

In the above conventional circuit, MOTORCLK-P
The rotation speed of the synchronous motor 4 is regulated by the frequency of the signal to prevent an excessive overcurrent from flowing through the motor winding due to the output voltage of the drive power source 2. For example, when rotating the synchronous motor 4 at 39000 rpm, the frequency of the MOTORCLK-P signal is set to 3
900HZ, set the driving voltage to 260V, and
To reduce the rotation speed to 25560 rpm, MOTOR
The frequency of the CLK-P signal is set to 2556 HZ, and the drive voltage is lowered to 140 V in order to prevent an increase in overcurrent in the motor winding.

[0004]

In the conventional synchronous motor control circuit described above, in order to prevent burnout of the motor winding or the like due to overcurrent, the output voltage of the drive western power supply 2 is adjusted in accordance with the frequency of the MOTORCLK-P signal. I had to switch appropriately. Therefore, it is necessary to constantly monitor the relationship between the reference clock and the drive voltage, and if this monitoring is erroneous, there is a risk of causing a motor burnout accident. For example, the motor 2
If you accidentally apply 260V at 5560 rpm,
The motor burns out, and the motor that switches the reference clock to 2556HZ burns out while driving at 260V.

However, it is difficult to completely prevent burnout of the motor winding because a method of detecting an abnormal overcurrent of the motor and reducing or stopping the current to the motor at the time of abnormality involves a response delay. There was a problem. An object of the present invention is to provide a control circuit for a synchronous motor capable of preventing the motor winding from being burnt out.

[0006]

In order to solve the above problems, a reference clock monitoring unit for detecting the reference clock frequency level, a drive voltage monitoring unit for detecting the drive voltage level, a reference clock monitoring unit, and The above-mentioned normal / abnormal state is provided with means for judging normal / abnormal of each combination of outputs of the drive voltage monitoring section, and a drive power source for controlling the drive signal of the synchronous motor according to the output of the normal / abnormal decision means. When the determination means outputs a signal indicating an abnormality, the drive power source is shut off. As a specific example, the reference clock frequency and the drive voltage are each of two types, the reference clock monitoring unit detects the magnitude relationship between the two types of reference clock frequencies, and the drive voltage monitoring unit is the two types. The normal / abnormality determining means outputs a normal or abnormal signal according to the detection results of the reference clock monitoring section and the drive voltage monitoring section. And a power source for controlling the drive signal of the synchronous motor, and the drive power source is shut off by the abnormal signal of the normality / abnormality determining means.

[0007]

When the combination of the reference clock frequency and the drive voltage level is normal, the normal drive signal is applied to the / synchronous motor, and when it is abnormal, the drive signal is cut off.

[0008]

1 is a block diagram of an embodiment of a synchronous motor control circuit according to the present invention. In FIG. 1, an abnormality detection unit 5 is provided between the reference clock generation circuit 1 and the drive power supply 2 and the drive circuit 3 of the conventional circuit shown in FIG.
The relationship between the TOR CLK-P signal and the output voltage of the driving power supply 2 is monitored, and if there is an abnormality, the output of the driving power supply 2 is stopped. As a result, the synchronous motor motor 4 can be stopped before an excessive overcurrent flows.

Reference clock monitor 6 in abnormality detector 5
Monitors the MOTORCLK-P signal which is the reference clock, and the drive voltage monitor 7 monitors the output voltage of the drive power supply 2. In the present embodiment, the MOTOR CLK-
The case where the P signal has two kinds of 3900 HZ and 25560 Hz and the output voltage of the driving power supply 2 has two kinds of 260 V and 140 V will be described.
It is needless to say that the same can be applied to the case where both the OTOR CLK-P signal and the output voltage of the driving power supply 2 are two or more.

The CLK-P from the oscillator 8 is input to the trigger terminal T of the counter 9 in the reference clock monitoring unit 6, and the MOTOR CLK-P signal is input to the reset terminal R of the counter 9. This MOTOR CLK-P signal is 3900 HZ when the rotation speed of the motor is 39000 rpm,
When it is set to 25560 rpm, it is 2556 HZ.

FIG. 2 is a timing chart for explaining the operation of FIG. The counter 9 outputs the output CLK-P of the oscillator 8.
Are counted and reset by the MOTOR CLK-P signal. The frequency of the output CLK-P of the oscillator 8 is an overflow when the frequency of the reset signal MOTOR CLK-P signal is 2556 Hz rpm, and an overflow when the frequency is 3900 Hz. It is set not to.

FIG. 2A shows the case where the frequency of MOTOR CLK-P is 2556 HZ and the drive voltage of the motor is 140V. This corresponds to the case where the driving condition of the synchronous motor 4 is normal. The counter 9 overflows (counts up) by CLK-P before the input of the reset signal, and the level "H" is supplied to the flip-flop 10 at the next stage.
, And the flip-flop 10 transmits the level “H” to the AND gate 11. Based on this result, the reference clock monitoring unit 6 recognizes that the frequency of MOTOR CLK-P is 2556HZ.

At this time, the drive voltage monitoring unit 7 determines whether the output voltage of the drive power source 2 is the drive voltage 140V corresponding to the above 2556 Hz. Therefore, in FIG. 1, the reference voltage (+ 5V) level divided by the resistors 14a and 14b is set to an intermediate value between the output voltages 260V and 140V of the driving power source 2 divided by the resistors 13a and 13b. . As a result, the motor drive voltage is 14
In the case of 0 V, the voltage level of the + input output terminal of the comparator 12 becomes lower than the voltage level of the − input output terminal thereof, so that the output voltage of the comparator 12, that is, the drive voltage monitoring signal becomes the level “L”. Is transmitted to AND gate 11.

The AND gate 11 receives the "H" reference clock monitor signal and the "L" drive voltage monitor signal from the reference clock monitor signal.
The ERR-P signal of level "L" indicating that there is no abnormality in the driving condition of the synchronous motor 4 is output. As a result, the motor drive circuit 3 receives the ERR-P "L" and drives the synchronous motor 4.

FIG. 2B is the same as FIG. 2A above.
It is a timing chart when a drive voltage of 260V is applied when the frequency of MOTOR CLK-P is 2566HZ. This case corresponds to the case where the driving condition of the synchronous motor 4 is abnormal. Drive voltage level is 26
Since it is 0V, the level of the output of the comparator 12 (driving voltage monitoring signal) becomes "H", and as a result, "H" is transmitted to the AND gate 11 and the ERR-P signal changes to "H", and the motor The drive circuit 3 cuts off the drive voltage of the synchronous motor 4.

As described above, in the present invention, the motor drive circuit 3 outputs the normal / abnormality determination signal ERR- from the abnormality detecting section 5.
Since the drive voltage is applied to the synchronous motor 4 after receiving P, an overcurrent does not flow in the synchronous motor 4, and the synchronous motor 4 can always be safely driven.

[0017]

According to the present invention, since the synchronous motor is driven only when both the reference clock for driving the synchronous motor and the drive voltage are normal, overcurrent driving of the synchronous motor is prevented in advance. Thus, it is possible to provide a synchronous motor control circuit that can always drive this safely.

[Brief description of drawings]

FIG. 1 is a block diagram of a synchronous motor control circuit according to the present invention.

FIG. 2 is a timing chart of FIG.

FIG. 3 is a block diagram of a conventional synchronous motor control circuit.

[Explanation of symbols]

1 ... Reference clock generation circuit, 2 ... Driving power supply, 3 ... Driving circuit, 4 ... Synchronous motor, 5 ... Abnormality detection section, 6 ...
Reference clock monitoring unit, 8 ... Oscillator, 9 ... Counter, 10
... flip-flops, 12 ... comparators.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-7-117793 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H02H 7/08 H02P 7/36

Claims (2)

(57) [Claims] 1. In a control circuit of a synchronous motor for switching a reference clock frequency and a drive voltage to drive a synchronous motor, a reference clock monitoring section for detecting the reference clock frequency level and a drive for detecting the drive voltage level. A voltage monitoring unit, a unit for determining normality / abnormality of a combination of outputs of the reference clock monitoring unit and the drive voltage monitoring unit, and a drive signal for the synchronous motor is controlled according to the output of the normality / abnormality determining unit. A synchronous motor control circuit comprising: a drive power supply; and when the normality / abnormality determination means outputs a signal indicating an abnormality, the drive power supply is shut off. 2. The drive voltage monitoring unit according to claim 1, wherein the reference clock frequency and the drive voltage are each of two types, and the reference clock monitoring unit detects a magnitude relationship between the two types of reference clock frequencies. To detect the magnitude relationship between the two types of drive voltage levels, and the normality / abnormality determination means outputs a normality or abnormality signal according to the detection results of the reference clock monitoring unit and the drive voltage monitoring unit. The drive power source is provided to control the drive signal of the synchronous motor.
A synchronous motor control circuit characterized in that the drive power source is shut off by an abnormality signal from an abnormality determining means.