JP3384756B2 - IIR digital low-pass filter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IIR type digital low pass filter.

[0002]

2. Description of the Related Art FIG. 1 shows a conventional IIR (Infinite Impulsion).
e Response) type digital low-pass filter.

This IIR type digital low-pass filter is composed of an adder 1, a delay device 2, a multiplier 3 of coefficient b and a multiplier 4 of coefficient a.

The input of this filter is X _n , the output is Y _n ,
When the output of the adder 1 is Q _n , the output Y _n is represented by the following formula 1.

[0005]

[Equation 1]

When a filter having a low cutoff frequency with respect to the sampling frequency is designed in the configuration of FIG. 1, the multiplier 3 of the coefficient b becomes large and the operation speed also decreases.
The coefficient b of this low-pass filter is b = 0.9999999851 and is a value close to 1.

If the coefficient b is 1, the multiplier 3 becomes unnecessary and the circuit structure is simplified, but the stability of the filter becomes a problem. For example, when a value biased to one of the codes is input, the value Q _n in this loop causes an overflow and the low pass filter does not operate properly.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide an IIR type digital low pass filter which can improve the operation speed.

[0009]

The IIR type digital low-pass filter according to the present invention has a cut-off frequency of the sun.
I applied when it is sufficiently lower than the pulling frequency
An IR type digital low-pass filter, wherein a first adder to which input data is input, a first delay device that delays the output of the first adder by one clock period and outputs the delayed output, and an output of the first delay device are input. A second adder, a multiplier that multiplies the output of the second adder by a predetermined coefficient and outputs the result as a filter output,
Comprising a bit shifter for bit shifting the output of the second delayer and the second delayer to output the output delay one clock period of the second adder, the first adder, the input data <br/> bit shifter to output the result by subtracting the output, the second adder, characterized in that is to output the added output of the first delay and the output of the second delay.

[0010] The input data is m bits wide, the first adder performs the operations in m-bit width, the second adder performs the operations in a large n-bit width from m bits wide, bit shifter second delay Out of the n-bit width data sent from the container, the data for the upper m bits are extracted and output.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

[1] IIR according to an embodiment of the present invention
Description of the configuration of the digital low-pass filter.

FIG. 3 is a block diagram of II according to the embodiment of the present invention.
The structure of an R-type digital low-pass filter is shown.

This filter is applied when the cutoff frequency is extremely lower than the sampling frequency.
It is an IR type digital low pass filter and includes a first adder 2
1, a first delayer 22 for delaying one clock cycle, a second adder 23, a second delayer 24 for delaying one clock cycle, a multiplier with a coefficient d = 1-b (see FIG. 1) It is composed of a bit shifter 25 and a multiplier 26 of a coefficient a (see FIG. 1).

In FIG. 3, n and m represent the bit width of the signal. n and m have a relationship of n> m,
For example, m is 8 bits and n is 32 bits. Immediately after reset, each register used to realize this digital low-pass filter is reset to 0, and a value in 2's complement notation is input to the register.

Data X _n having an m-bit width is input to the input terminal. This input data X _n is sent to the first adder 21, and the output from the bit shifter 25 (corresponding to d × Q _n−1 ) is subtracted. The data XX _n obtained by the first adder 21 is delayed by the first delay device 22 for one clock period.

Next, the data XX _n-1 is sent to the loop circuit 30 composed of the second adder 23 and the second delay device 24. The second adder 23 in the loop circuit 30 performs addition of XX _n-1 + Q _{n-1 using} all the data input immediately after reset as n-bit data.

The data Q _n after the addition is sent to the multiplier 26, multiplied by the coefficient a, and then output as output data Y _n . This output data becomes data from which high frequency components have been removed by this digital low pass filter.

On the other hand, the second delay device 2 in the loop circuit 30
The n-bit data Q _n−1 output from 4 is sent to the bit shifter 25. The bit shifter 25 extracts the upper m bits from the n-bit data and sends them to the first adder 21.

In this IIR type digital low-pass filter, a multiplier for multiplying the value b close to 1 is unnecessary, so that the operation speed can be improved.

[2] Description of how the IIR digital low-pass filter of FIG. 3 was designed

If a filter having a low cutoff frequency with respect to the sampling frequency is designed in the configuration of the conventional IIR type digital low-pass filter shown in FIG. 1, the multiplier of the coefficient b becomes large and the operating speed also decreases. Therefore,
Instead of multiplying Q _n-1 by the coefficient b, a method of performing the calculation shown in the following formula 2 was adopted.

[0023]

[Equation 2]

However, d = 1-b. FIG. 2 shows the configuration of a filter that performs such calculation.

In the filter of FIG. 2, the multiplier 13 of the coefficient d is used instead of the multiplier 3 of the coefficient b of FIG. Also, instead of the adder 1, a delay device 2 is provided at the input X _n.
The output Q _n-1 of the
An adder 11 is used to subtract the output d × Q _n−1 .

In this way, Q _n never overflows. Also, the multiplier 13 of the coefficient d
If the calculation accuracy does not matter, the upper bit can be taken out by bit shift, and the operation speed is improved.

However, since the adder 11 deals with three variables, there is a problem that it is necessary to perform two operations of addition and subtraction in one clock cycle.

Since the value of Q _n changes slowly in the upper bits, it is considered that there is little effect even if the configuration of FIG. 2 is changed to the configuration of FIG.

In the filter of FIG. 3, the output Y _n is expressed by the following equation (3).

[0030]

[Equation 3]

Here, with respect to the sampling frequency,
Since the shutoff frequency is low enough, Q _n≒ Q_n-1Is approximated by
You can Therefore, output Y_nIs the following Equation 4
expressed.

[0032]

[Equation 4]

Further, the output Y _n is the output of the low-pass filter, and its change is considered to be slow, so that the approximation of Y _n ≈Y _n-1 holds.

Therefore, the output Y _n is expressed by the following equation (5).

[0035]

[Equation 5]

Furthermore, when Formula 5 is rearranged, Formula 6 is obtained, which coincides with Formula 1 for calculating the output Y _n in the conventional IIR digital low-pass filter shown in FIG.

[0037]

[Equation 6]

[0038]

According to the present invention, an IIR type digital low pass filter which can improve the operation speed is realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a conventional IIR digital low-pass filter.

FIG. 2 is a block diagram showing a configuration of an IIR digital low-pass filter equivalent to FIG.

FIG. 3 is a block diagram showing the configuration of an IIR digital low-pass filter that is an embodiment of the present invention.

[Explanation of symbols]

21 first adder 22 First delay device 23 Second adder 24 Second delay device 25-bit shifter 26 Multiplier

Claims (2)

(57) [Claims] 1. A cutoff frequency is a sampling frequency
IIR type digital that is applied when it is sufficiently lower than
A low-pass filter, a first adder to which input data is input, a first delay device that delays the output of the first adder by one clock period, and outputs the second adder, and a second delay device to which the output of the first delay device is input An adder, a multiplier that multiplies the output of the second adder by a predetermined coefficient and outputs the result as a filter output, a second delay device that delays the output of the second adder by one clock period, and a second delay device A bit shifter for bit-shifting the output of, the first adder subtracts the output of the bit shifter from the input data and outputs it, and the second adder outputs the output of the first delay device and the output of the second delay device. It is characterized in that the output is added and output .
IIR-type digital low-pass filter that. 2. When the input data has an m-bit width, the first
The adder performs the above operation with an m-bit width, and the second adder uses m
Perform the above operation in a large n bit width than, bit shifter claims, characterized in that the output is taken out upper m bits of data among the data of n bits wide sent from the second delay IIR type digital low-pass filter described in 1.