JP3384694B2 - Image information processing apparatus and waveform shaping circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image information processing apparatus and a waveform shaping circuit used for the same, and more particularly to image information processing for separating a luminance component and a color component from an image signal to generate luminance data and color data. The present invention relates to a device and a waveform shaping circuit that shapes, amplifies, and outputs a waveform of a color synchronization signal extracted from an image signal.

[0002]

2. Description of the Related Art An image signal for reproducing a color image on a monitor screen includes a brightness component representing the shade of the image, a color component representing the color, and a synchronization component determining various timings. These respective components are separated from each other by utilizing the amplitude difference, the phase shift, etc., and are individually processed as a luminance signal, a color signal and a synchronization signal. In each signal processing, there is a tendency to be digitalized in order to make it easy to adjust by making it less susceptible to temperature changes and noise.

FIG. 7 is a block diagram showing the configuration of an image information processing apparatus which employs digital signal processing, and FIG. 8 is a waveform diagram of signals handled by the respective parts. Y / C separation circuit 1
Captures an image signal i containing a luminance component and a color component,
The phase difference of the color components is used to separate the components into the luminance signal y
And a color signal c. For example, in the case of the NTSC system, the image signal i is shifted by one horizontal scanning period and added to each other to extract the luminance component, and the color component is extracted from the difference between them.

The first amplifier 2 is a high frequency amplifier in the video band provided for the luminance signal y, and the luminance signal y
Is amplified to a predetermined amplitude. The first A / D conversion circuit 3 has
The amplified luminance signal y output from the amplifier 2 is quantized in response to the first sampling clock SC1 to generate luminance data YO. The second amplifier 4 is a high frequency amplifier equivalent to the first amplifier 2 provided for the color signal c, and amplifies the color signal c to a predetermined amplitude. Second A /
The D conversion circuit 5 quantizes the amplified color signal c output from the second amplifier 4 in response to the second sampling clock SC2 to generate color data CO.

The synchronous detection circuit 6 takes out the synchronous component of the image signal i and generates a horizontal synchronous signal HD and a vertical synchronous signal VD. In this synchronous detection, the mixed component of horizontal synchronization and vertical synchronization is first extracted by using the difference in amplitude between the synchronization component and other signal components, and then the horizontal synchronization component and vertical synchronization are utilized by using the difference in frequency. Separated into components.

The first phase locked loop (PLL) 7 is
The first sampling clock SC1 for the luminance signal y is generated based on the horizontal synchronizing signal HD extracted by the synchronous detection circuit 6. For example, in the NTSC system, the first
Of the sampling clock SC1 of 910 is synchronized with the horizontal synchronizing signal HD so as to synchronize with the first PL.
L5 is configured to generate 910 luminance data in one horizontal scanning period.

The burst detection circuit 8 selectively extracts the burst signal CB for synchronizing the phases of the color components from the image signal i. That is, the burst signal CB is a fixed pattern signal having a predetermined frequency (for example, 3.58 MHz), and is superimposed at a predetermined position of the image signal i, for example, at the beginning of each horizontal scanning period. Therefore, the burst signal CB can be obtained by selectively extracting the specific period at the beginning of each horizontal scanning period of the image signal I.

The second PLL 9 generates a second sampling clock SC2 for the color signal c with the burst signal CB as a reference. The second sampling clock SC2 is generated so as to have the same cycle as the first sampling clock SC1. For example, in the NTSC system, a clock obtained by dividing the second sampling clock CS2 by 4 is synchronized with the burst signal CB by the second P clock.
LL7 is configured and a burst signal CB of 3.58 MHz
On the other hand, the second sampling clock SC2 of 14.32 MHz is generated.

The image data processing circuit 10 includes first and second image data processing circuits.
The luminance data YO and the color data CO output from the A / D conversion circuits 3 and 5 of FIG. 1 are taken in for each data, and predetermined signal processing is performed to obtain new luminance data Y and a luminance component and a red component or a blue component. Color difference data U and V that represent the difference between and are generated. In the generation processing of the brightness data Y, the outline processing of the subject, the aperture processing for enhancing the contrast,
Gamma correction or the like for correcting visual non-linearity with respect to the brightness level is performed. Then, in the generation processing of the color difference data U and V, first, demodulation of the color components that have been subjected to balanced modulation, white balance adjustment, and the like are performed, and then the luminance component is subtracted from each color component.

In the image data processing circuit 10, one of the data is sampled again in consideration of the timing difference of the output of the luminance data YO and the color data CO from the first and second A / D conversion circuits 3 and 5. The timings of the two are matched by re-doing them. As a result, the luminance data Y and the color difference data U and V are collected at the same timing for each data and sent to the recording system or the reproducing system.

[0011]

The horizontal synchronizing signal HD extracted by the synchronous detection circuit 6 or the burst signal CB extracted by the burst detection circuit 8 is a sine waveform due to the characteristics of the detection circuits 6 and 8 operating in analog. Is close to. For this reason, the horizontal synchronizing signal HD and the burst signal CB taken out by the respective detection circuits 6 and 8 are directly applied to each P.
If the reference signals of the LLs 7 and 9 are used, the operations of the PLLs 7 and 9 may become unstable. Therefore, the horizontal synchronization signal HD
Also, it is considered to provide a waveform shaping circuit for shaping the burst signal CB into a rectangular wave with a duty ratio of 50%. This waveform shaping circuit is generally composed of a CMOS inverter or the like in which a P-channel MOS transistor and an N-channel MOS transistor are connected in series.

The gain in a normal CMOS inverter circuit is the product of its conductance gm and the source-drain resistance rds. Then, the conductance g of the inverter circuit during digital operation
Since m and the resistance rds are very high, the gain of the inverter circuit becomes very large, and a slight change in the gate voltage causes a large change in the output voltage.

On the other hand, the change in the current output from the inverter circuit changes at the threshold voltage (usually 1/2 of the power supply voltage) Vt of the inverter circuit. For example, a large current flows when the gate voltage becomes higher than the threshold voltage Vt, and conversely, a large current flows when the gate voltage becomes lower than the threshold voltage Vt. That is, the inverter circuit supplies a current as if the gate voltage (= input voltage) is integrated.

Therefore, as indicated by the solid line in FIG. 9, in the inverter circuit, the higher the frequency of the input signal like the burst signal CB, the poorer the followability of the output signal and the lower the gain. Then, when the amplitude of the input signal, that is, the burst signal CB, decreases, the burst signal C of the output signal
The delay time for B becomes long. The delay time is the second
The second sampling clock SC2 generated by the PLL 9 is delayed, and the first and second A / D conversion circuits 3,
There is a deviation between the data C0 and Y0 generated by the above method. In particular, in digital signal processing, the deviation between the luminance data Y and the color difference data U and V is easily emphasized on the reproduction screen, and the outline of the image is disturbed and color bleeding occurs.

Further, when the signal strength of the image signal i is lowered due to a weak electric field, deterioration of the propagation state, etc., the amplitude of the burst signal CB to be extracted becomes small. Then, since the gate voltage becomes small, the current flowing through the inverter circuit becomes small and the waveform of the output signal becomes gentle. as a result,
The output signal of the waveform shaping circuit is a sine wave delayed by 90 degrees from the input burst signal CB, as shown by the alternate long and short dash line in FIG.

Then, since the sine wave signal is input to the second PLL 9, the lock operation cannot be performed reliably, and the second sampling clock SC2 cannot be generated. As a result, the image signal processing circuit cannot generate each data.

The present invention has been made to solve the above problems, and its object is to provide a waveform capable of outputting a shaped rectangular wave regardless of a change in the amplitude of a high-frequency input signal. It is to provide a shaping circuit to stabilize the operation of the image information processing apparatus.

[0018]

According to a first aspect of the present invention, there is provided an image information processing apparatus for generating luminance data and color data by digital signal processing from an image signal including a luminance component and a color component and a synchronization component. A separation circuit for individually extracting a luminance component and a color component from the image signal to generate a luminance signal and a color signal; a detection circuit for extracting a color synchronization signal for obtaining the synchronization of the color component from the image signal; A waveform shaping circuit that takes in a synchronizing signal and shapes the waveform, a phase-locked loop that generates a reference clock with a constant period based on the waveform-shaped color synchronizing signal, and quantizes the color signal according to the reference clock to color The waveform shaping circuit includes an A / D conversion circuit that generates data and a color data processing circuit that performs a predetermined process on the color data. At the output of a CMOS circuit in which a pair of MOS transistors are connected in series between the power supply ground and a capacitor for transmitting the AC component of the color synchronization signal taken out in step 1, there is a connection point of a pair of resistors connected in parallel to the CMOS circuit. The gist is that it is composed of an amplifier circuit to be connected.

The invention described in claim 2 is the same as claim 1.
In the image information processing device described in the paragraph 1, the waveform shaping circuit is characterized in that a plurality of stages of the amplifier circuits are connected in series.

The invention according to claim 3 is the same as that of claim 2
The gist of the image information processing device described in (1) is that a resistor for returning the output of the first-stage amplifier circuit among the plurality of-stage amplifier circuits to the input is connected.

According to a fourth aspect of the present invention, a color locked signal for synchronizing the color components extracted from the image signal is used as a reference to generate a reference clock having a constant cycle. A waveform shaping circuit for inputting to a CMOS type inverter circuit in which a pair of MOS transistors are connected in series between power supply grounds, and the inverter circuit is connected in parallel, and the connection point is the output of the inverter circuit. An amplifier circuit including a pair of resistors connected to each other is provided, and a color synchronization signal coupled through a capacitor is input to an input terminal of the amplifier circuit, and an output signal of the amplifier circuit outputs a resistor. The gist is that it is fed back via the color-synchronization signal to generate a rectangular-wave-shaped signal and outputs the signal to the phase-locked loop.

According to a fifth aspect of the present invention, a color locked signal for synchronizing the color components extracted from the image signal is used as a phase locked loop for generating a reference clock having a constant cycle with reference to the color synchronized signal. Is a waveform shaping circuit for inputting to a plurality of stages of an amplifier circuit composed of a CMOS type inverter circuit and a resistor connected in parallel to the inverter circuit, and is connected in series to the input terminal of the first stage amplifier circuit. , The color synchronization signal coupled through the capacitor is input, the output signal of the amplifier circuit is fed back through the resistor, and the color synchronization signal is shaped into a rectangular wave from the final stage amplifier circuit. The gist is that it is generated and output to the phase locked loop.

Therefore, according to the invention of claim 1,
The separation circuit individually extracts the luminance component and the color component from the image signal to generate the luminance signal and the color signal, and the detection circuit
A color synchronization signal for synchronizing the color components is extracted from the image signal. The color synchronizing signal is taken into a waveform shaping circuit and waveform shaped, and a reference clock having a constant cycle is generated by a phase locked loop with the waveform shaped color synchronizing signal as a reference. Then, the A / D conversion circuit quantizes the color signal in accordance with the reference clock to generate color data, and the color data processing circuit performs a predetermined process on the color data. And
The waveform shaping circuit is connected in parallel to the output of a CMOS circuit in which a pair of MOS transistors are connected in series between a power supply ground and a capacitor for transmitting an AC component of the color synchronizing signal extracted by the detection circuit. And an amplifier circuit to which a connection point of a pair of resistors is connected.

According to the second aspect of the invention, the waveform shaping circuit is formed by connecting a plurality of amplifier circuits in series. According to the third aspect of the invention, a resistor is connected to the output of the amplifier circuit of the first stage among the amplifier circuits of the plurality of stages, and the input of the amplifier circuit is fed back.

According to a fourth aspect of the invention, in the amplifier circuit, a CMOS type inverter circuit in which a pair of MOS transistors are connected in series between the power supply grounds and the inverter circuit are connected in parallel and connected. The point is composed of a pair of resistors connected to the output of the inverter circuit. The output impedance of the amplifier circuit is a parallel component of the inverter circuit and the resistance, and is lower than that of the inverter circuit alone. A color sync signal coupled through a capacitor is input to the input terminal of the amplifier circuit, the output signal of the amplifier circuit is fed back through a resistor, and the color sync signal is shaped into a rectangular wave. Is generated and output to the phase locked loop.

According to the invention described in claim 5, the amplifying circuit serially connected in plural stages comprises an inverter circuit having a CMOS structure and a resistor connected in parallel to the inverter circuit. The output impedance of is a parallel component of the inverter circuit and the resistance, and is lower than that of the inverter circuit alone. The color synchronization signal coupled through the capacitor is input to the input terminal of the first-stage amplifier circuit, and the output signal of the amplifier circuit is fed back through the resistor. Then, a signal in which the color synchronization signal is shaped into a rectangular wave is generated from the amplifier circuit at the final stage and output to the phase locked loop.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. In the present embodiment, the same components as those in the conventional example shown in FIG. 6 are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 1 is a block diagram showing the arrangement of an image information processing apparatus adopting the digital signal processing of this embodiment. In FIG. 1, a waveform shaping circuit 21 is provided between the burst detection circuit 8 of the conventional example shown in FIG. 7 and the second PLL 9.
Is provided.

The waveform shaping circuit 21 inputs the burst signal CB extracted from the image signal i by the burst detection circuit 8 as in the conventional case. Then, the waveform shaping circuit 21
Generates a signal S1 obtained by waveform-shaping the burst signal CB. This waveform shaping is a rectangular wave required for generating a second clock signal SC2 by surely performing a lock operation in the second PLL 9, and a signal S having a duty of 50%.
1 is generated. That is, the normally input burst signal CB
Is an analog signal and has a substantially sinusoidal waveform.
If the sine wave is left as it is, the second PLL 9 cannot reliably perform the lock operation. Therefore, the waveform shaping circuit 21 waveform-shapes the burst signal CB and generates the amplified signal S1.

As shown in FIG. 2, the waveform shaping circuit 21 is provided with a plurality of stages (three stages in this embodiment) of amplification circuits (amplifiers) 22 connected in series. The input terminal of the amplifier 22 in the first stage is AC-coupled to the verse and the detection circuit 8 via the capacitor 23, and the burst signal CB excluding the DC component is input.

The input terminal of the first-stage amplifier 22 is connected to the output terminal thereof via the resistor 24.
The resistor 24 is provided to feed back the output signal of the amplifier 22 and set the center voltage to the input threshold voltage Vt of the amplifier 22. When the center voltage deviates from the threshold voltage Vt, the duty of the generated signal S1 deviates from 50%. Therefore, the output signal of the amplifier 22 is fed back by the resistor 24, the input threshold voltage Vt of the amplifier 22 is obtained from the burst signal CB and the output signal S1, and the center voltage is set to the obtained threshold voltage Vt.

Then, the waveform shaping circuit 21 waveform-shapes the input burst signal CB into a rectangular wave having a duty of 50% by the three-stage amplifier 22 and generates a signal S1 in which the amplitude of the rectangular wave is amplified. And output.

Each amplifier 22 comprises an inverter circuit 25 and resistors 26 and 27. As shown in FIG. 3, the inverter circuit 25 has a CMOS structure including a P-channel MOS transistor Tp and an N-channel MOS transistor Tn, and the resistors 26 and 27 are provided in both MOS transistors Tp and Tn of the inverter circuit 25. It is connected in parallel. That is, both MOS transistors T
The p and Tn and the resistors 26 and 27 are connected in series between the high potential side power source Vcc and the ground GND. The connection point between the MOS transistors Tp and Tn and the resistor 26,
The connection point between 27 is connected.

FIG. 4 shows both MOSs including resistors 24 and 25.
The characteristic diagram of the current with respect to the voltage of the transistors Tp and Tn, that is, the amplifier 22 is shown. As shown in FIG. 4, both MOS transistors Tp and Tn near the threshold voltage Vt
The source-drain resistances rdp and rdn have a gentler slope than in the case of a general inverter circuit. Therefore, the ratio of the change amount ΔVo of the output signal to the change amount ΔVi of the input voltage is determined by the inverter circuit 2 shown in FIG.
It is smaller than the case of 5 units alone.

That is, the gain of the amplifier 22 is smaller than that of the inverter circuit 25 alone. Furthermore, the output impedance of the amplifier 22 becomes a combined resistance of the resistance component of the inverter circuit 25 and the resistors 26 and 27 connected in parallel to the inverter circuit 25, and the inverter circuit 25
It will be smaller than when used alone.

Therefore, by operating the amplifier 22 in the vicinity of the threshold voltage Vt, the waveform of the output signal is not the conventional integral waveform but the output waveform of the output impedance R and its load capacitance C. The delay time of the amplifier 22 is determined by the time constant of the output impedance R of the amplifier 22 and the load capacitance C at the output terminal. Therefore, the delay time can be shortened by making the output impedance R sufficiently small, and the delay time does not depend on the amplitude of the input signal.

As a result, as shown in FIG. 5A, although the gain of the amplifier 22 as a whole is smaller than that of an amplifier composed of a normal inverter circuit, the cutoff frequency is the frequency f0 of the burst signal CB to be used. Will be higher than. Therefore, as shown in FIG. 5B, there is no phase shift between the input signal and the output signal at the frequency f0 of the burst signal CB. Further, since the output impedance of the amplifier 22 is determined by the resistors 26 and 27, the resistance value does not change even if the power supply voltage changes, so the delay time becomes constant.

Therefore, the waveform shaping circuit 21 can shape the waveform of the input burst signal CB into a rectangular wave with a duty of 50%, and also generate and output the signal S1 amplified to a sufficient amplitude. .

Since the second PLL 9 receives the signal S1 having a rectangular wave and a duty of 50%, the second PLL 9 can perform a reliable lock operation, and the second sampling clock SC2 serving as a reference clock. Can be generated. As a result, the image signal processing circuit can generate each data without deviation.

By the way, generally, as a method of lowering the output impedance of an inverter circuit having a CMOS structure, a PMOS transistor and an NMO forming an inverter circuit are used.
A method of reducing the source-drain resistance rds of the S transistor can be considered. In order to reduce the resistance rds, it is necessary to narrow the channel length of the transistor in order to increase the channel length modulation effect of the transistor. However, when a current constantly flows in the inverter circuit having a short channel length, the threshold voltage Vt is likely to change due to hot carriers. On the other hand, in the amplifier 22 of the present embodiment, the resistors 26 and 27 are connected in parallel with both MOS transistors Tp and Tn that form the inverter circuit 25, so that the channel length modulation effect is not used.
The output impedance can be lowered.

As described above, according to this embodiment, the following effects can be obtained. (1) The waveform shaping circuit 21 includes a CMOS inverter circuit and resistors 26 and 27 connected in parallel to the inverter circuit.
And an amplifier circuit 22 composed of
The output impedance of 2 is the inverter circuit 25 and the resistance 2
The number of parallel components is 6, 27, which is lower than that of the inverter circuit alone. The amplifier circuits 22 are connected in series in a plurality of stages, and the burst signal CB is input to the input terminal of the first stage amplifier circuit via the capacitor 23 and the output signal of the amplifier circuit 22 receives the resistance 24. Feedback via. Then, the color synchronizing signal from the amplifier circuit 22 at the final stage is a rectangular wave and its duty is 50%.
The signal S1 whose waveform is shaped into
Is output to.

As a result, since the second PLL 9 receives the signal S1 having a rectangular wave and a duty of 50%, a reliable lock operation can be performed, and the second sampling clock serving as a reference clock. SC2 can be generated. As a result, the image signal processing circuit can generate each data without deviation.

The present invention may be carried out as follows in addition to the above embodiment. (1) In the above embodiment, the three amplifiers 22 connected in series to the waveform shaping circuit 21 are provided.
That is, depending on the amplitude of the waveform-shaped signal S1,
Waveform shaping circuit 21 using one or four or more amplifiers
May be configured.

(2) The waveform shaping circuit 21 of this embodiment is
Although it is provided between the burst detection circuit 8 and the second PLL 9, it may be implemented by being used for other portions where waveform shaping is necessary, for example, between the synchronous detection circuit 6 and the first PLL 7. Good.

[0045]

As described above in detail, according to the present invention, there is provided a waveform shaping circuit capable of outputting a shaped rectangular wave regardless of the change in the amplitude of a high frequency input signal. The operation of the information processing device can be stabilized.

[Brief description of drawings]

FIG. 1 is a block diagram of an image information processing apparatus according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a waveform shaping circuit.

FIG. 3 is a circuit diagram of an amplifier used in a waveform shaping circuit.

FIG. 4 is a characteristic diagram of an amplifier included in the waveform shaping circuit.

5A is a gain characteristic diagram of an amplifier, and FIG. 5B is a phase characteristic diagram of the amplifier.

FIG. 6 is a characteristic diagram of a single inverter circuit.

FIG. 7 is a block diagram of a conventional image information processing apparatus.

FIG. 8 is a waveform diagram of an image signal and each synchronization signal.

FIG. 9 is a waveform diagram showing an output signal with respect to an input signal.

[Explanation of symbols]

1 separation circuit 5 A / D conversion circuit 8 Burst detection circuit 9 Phase-locked loop (second PLL) Image data processing circuit as 10 color data processing circuit 21 Wave shaping circuit 22 Amplification circuit (amplifier) 23 Capacitor 24 resistance 25 CMOS type inverter circuit 26,27 resistance CB burst signal S1 signal SC2 Second sampling clock signal

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 9/44-9/78

Claims (5)

(57) [Claims] 1. An image information processing apparatus for generating brightness data and color data by digital signal processing from an image signal containing a synchronization component together with a brightness component and a color component, wherein the brightness component and the color component are individually generated from the image signal. A separation circuit for generating a luminance signal and a chrominance signal by taking out the color synchronization signal, a detection circuit for extracting a color synchronization signal for obtaining the synchronization of the color components from the image signal, and a waveform shaping circuit for capturing the color synchronization signal and shaping the waveform, A phase-locked loop that generates a reference clock with a constant cycle based on the waveform-shaped color synchronization signal; an A / D conversion circuit that quantizes the color signal according to the reference clock to generate color data; A color data processing circuit for performing a predetermined process on the data, wherein the waveform shaping circuit is an AC generator of the color synchronization signal extracted by the detection circuit. And a capacitor to tell, a pair of MOS
CMOS with transistors connected in series between power supply ground
An image information processing apparatus comprising an amplifier circuit in which a connection point of a pair of resistors connected in parallel to the CMOS circuit is connected to an output of the circuit. 2. The image information processing apparatus according to claim 1, wherein the waveform shaping circuit has a plurality of stages of the amplifier circuits connected in series. 3. The image information processing apparatus according to claim 2, wherein, of the plurality of stages of amplifier circuits, a resistor for returning the output of the first stage amplifier circuit to the input is connected. 4. A waveform shaping circuit for inputting a color synchronization signal for synchronizing color components extracted from an image signal into a phase locked loop for generating a reference clock having a constant cycle with reference to the color synchronization signal. And a CMOS type inverter circuit in which a pair of MOS transistors are connected in series between power supply grounds, and a pair of resistors connected in parallel to the inverter circuit, the connection point of which is connected to the output of the inverter circuit. A color synchronization signal coupled through a capacitor is input to an input terminal of the amplification circuit, and an output signal of the amplification circuit is fed back through a resistor to obtain the color synchronization signal. A waveform shaping circuit configured to generate a signal whose waveform is shaped into a rectangular wave and output the signal to the phase locked loop. 5. A waveform shaping circuit for inputting a color synchronization signal for synchronizing color components extracted from an image signal to a phase locked loop for generating a reference clock having a constant period with reference to the color synchronization signal. Therefore, a plurality of stages of amplifier circuits each composed of a CMOS type inverter circuit and a resistor connected in parallel to the inverter circuit are connected in series, and the input terminal of the first stage amplifier circuit is coupled via a capacitor. A color synchronization signal is input and the output signal of the amplifier circuit is fed back through a resistor, and the final stage amplifier circuit generates a signal obtained by waveform-shaping the color synchronization signal into a rectangular wave and outputs the signal to the phase locked loop. Waveform shaping circuit.