JP3383404B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a region formed by filling a groove formed on the surface of a semiconductor substrate with an insulator is used for element isolation.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit typified by a memory and a logic, an element isolation technique for electrically isolating adjacent transistor regions is indispensable for operating each transistor or cell independently. Is.

As a conventional element isolation technique used for LSI manufacturing, a method of selectively forming a thick oxide film on an element isolation region to perform element isolation (LOCOS isolation method) and a semiconductor substrate surface corresponding to the element isolation region are used. There is a method (trench isolation method) of digging a groove and filling the groove with an insulator to perform element isolation. The LOCOS is shown in FIGS.
3A and 3B are cross-sectional views of element isolation regions formed by the isolation method and the trench isolation method, respectively.

In the LOCOS isolation method as shown in FIG. 23 (a), a region where an oxide film is made considerably thicker than the gate insulating film 102 is made by using silicon nitride deposited on a portion which becomes an element forming region on the silicon substrate 100 as a mask. (Element isolation insulating film) 101 is selectively formed to electrically separate one transistor from the other transistor.
This method has some problems that it is not suitable for high integration. One of the reasons is that a bird's beak-shaped oxide film (bird's beak) 103 is formed under the mask material at the time of selective oxidation, and a large gap is formed between the edge of the mask material and the edge of the element isolation region. Since there is a conversion difference, it is difficult to reduce the size of the element region to some extent or less. Another reason is that the oxidation of ions for a long time for forming the element isolation region diffuses the ion-implanted impurities on the element isolation region and promotes the narrow channel effect, so that the width of the element formation region is narrowed. Because it is difficult.

Further, in order to solve these problems, it is sufficient to reduce the amount of oxidation for forming the element isolation region. However, if the amount of oxidation is reduced, the film thickness of the oxide film for element isolation decreases and the element isolation region There is another problem that the inversion voltage is lowered.

As described above, the LOCOS separation method is limited in its application to submicron devices in the future.

On the other hand, the trench isolation method as shown in FIG. 23B is considered as a new element isolation method to replace LOCOS, and most of the problems that occur in the above LOCOS isolation are caused by this trench isolation method. It can be quite solved by introducing separation.

This trench isolation method is applied to the silicon substrate 10.
The groove 104 is formed by digging down the portion of the 0 surface which becomes the element isolation region.
Is formed, and an insulating material 105 such as SiO ₂ is embedded therein to isolate the elements. Below, an example of the process for forming the element isolation region by the conventional trench isolation method is shown.

First, 10 to 5 are formed on the silicon substrate 100.
A 0 nm thermal oxide film, a 100 to 500 nm polycrystalline silicon film, and a 100 to 500 nm CVD silicon oxide film are sequentially formed, and then resist patterning is performed, and vertical etching is performed by RIE to remove the resist. Then, using the remaining CVD silicon oxide film as a mask, the exposed portion of the silicon substrate 100 is subjected to RIE by 0.3 to
Etching is performed by 0.5 μm to form a groove (trench) 104 for element isolation. Next, in order to protect the side wall of the groove 104, thermal oxidation of 10 to 50 nm is performed to form an oxide film on the side wall of the trench. Here, after forming an oxide film for protecting the sidewalls of the trenches, impurities may be implanted to enhance the element isolation capability.

Next, the trench 104 is backfilled with a CVD silicon oxide (for example, a CVD film made of TEOS) 105. Thereafter, the CVD silicon oxide 105 is ground by resist etch back or polishing until the polycrystalline silicon is exposed, and is planarized. Then, the polycrystalline silicon and the buffer oxide film thereunder are removed.

An element isolation region is formed by the above manufacturing process. In the following steps, elements such as transistors are formed on the element region.

First, the silicon substrate 100 on the element region is oxidized by about 10 nm, and impurities are implanted through the oxide film for controlling the threshold value of the transistor. Then, once
The above oxide film is peeled off to form a gate oxide film, and polycrystalline silicon 120 to be a gate is deposited. Then, the gate 120 is patterned and a diffusion layer is formed to complete the transistor.

In the element isolation region formed by the trench thus formed, the width of the groove becomes the element isolation region as it is, so that the portion can be made small as long as the insulating material can be buried therein, and the LOCOS method can be applied. Compared with this, it is possible to save the area and solve the various problems of the LOCOS separation as described above.

On the other hand, however, some new problems arise.

One of the new problems is B in FIG.
It is a kink that appears in the subthreshold region of the transistor as shown in. In the element region formed by the above process, at the edge of the element region, that is, at the boundary between the gate oxide film portion of the transistor and the trench,
A corner portion (a portion indicated by A in FIG. 23 (b)) is generated. Then, electric field concentration occurs in this corner portion, so that the threshold value of the parasitic transistor in the corner portion becomes lower than the threshold value of the actual transistor. Because of this,
The kink as above appears. Although such a kink itself is not a problem for the circuit design itself, the increase in the subthreshold current due to the corner parasitic transistor causes problems such as an increase in standby current. It becomes an obstacle in design. In addition, the degree of electric field concentration on the corner portion largely changes depending on the shape of the corner portion. Therefore, it is difficult to generate kinks in the same way for all transistors. Therefore, the kink appearing in the subthreshold portion of the transistor described above causes variations in element characteristics, which is a serious problem in manufacturing an integrated circuit.

Another problem is that the electric field concentration occurs at the corners at the edges of the device region, which lowers the gate breakdown voltage of the transistor and lowers the reliability of the transistor. Further, as described above, it is difficult to cause the same degree of electric field concentration in all the elements. Therefore, such electric field concentration is caused in the EPROM and EEP.
In a device such as a ROM that exchanges charges through a gate oxide film, the threshold value varies during writing, and in an EEPROM, the threshold value varies during erasing.

[0017]

As described above, in the conventional LOCOS separation method, large bird's beaks are inevitably generated, and long-time oxidation causes impurity diffusion to promote the narrow channel effect. Therefore, there is a problem that it is difficult to reduce the size of the element region to a certain extent or less.

In the conventional trench element isolation technique,
Electric field concentration occurs at the corners of the edges of the element region, which causes problems such as a kink in the subthreshold characteristics of the transistor and a reduction in gate breakdown voltage, which lowers the reliability of the transistor.

The present invention has been made in consideration of the above circumstances, and makes it possible to manufacture a semiconductor device having an element isolation structure which enables high integration and is not affected by a corner portion of a trench .
The purpose is to provide a manufacturing method.

[0020]

[0021]

[0022]

[0023]

[0024]

A method of manufacturing a semiconductor device according to the present invention comprises a first mask layer and a second mask layer, which are sequentially stacked on a semiconductor substrate with a buffer oxide film interposed therebetween, to form an element isolation region. And the process of removing the
A step of performing beak oxidation, a step of removing an oxide film on a semiconductor substrate by RIE using the mask layer, a step of etching a semiconductor substrate using the mask layer to form a groove, and a step of forming a groove from the bottom of the groove. Depositing an insulator over the second mask layer, planarizing the deposited insulator until the upper end portion of the first mask layer is exposed, the first mask layer and the buffer The method is characterized by including a step of sequentially removing the oxide film and a step of forming a desired element in the element formation region.

Further, according to another method of manufacturing a semiconductor device of the present invention, element isolation is performed from the first mask layer and the second mask layer laminated on the semiconductor substrate with the buffer oxide film interposed therebetween. A step of removing a portion to be a region, a step of performing bird's beak oxidation, a step of forming an oxide film on a sidewall of a mask layer previously deposited, and an oxide film on a semiconductor substrate using the mask layer and the sidewall By RIE, etching the semiconductor substrate using the mask layer and sidewalls to form a groove, depositing an insulator from the bottom of the groove to above the second mask layer, and A step of planarizing the deposited insulator until the upper end portion of the first mask layer is exposed, a step of sequentially removing the first mask layer and the buffer oxide film, and a desired element in the element formation region. Forming process Characterized in that it has a.

[0026]

According to the present invention, the upper end portion (corner portion) of the semiconductor substrate material contacting the element isolation region is more than the gate oxide film.
Thick and gradually becomes closer to the element isolation region
Since it is protected by a thick oxide film , it is possible to effectively alleviate the electric field concentration at the corners, which was a problem in the conventional trench isolation.

As a result, it is possible to prevent the threshold value of the parasitic transistor at the corner from becoming lower than the threshold value of the actual transistor, so that it is possible to prevent the occurrence of kinks in the subthreshold region of the transistor and to prevent the gate of the transistor The breakdown voltage can be improved. This makes it possible to form a highly reliable element with a small leak current.

Moreover, since the trench structure is used in the main part of the element isolation region, the element can be miniaturized.

[0029]

Embodiments of the present invention will be described below with reference to the drawings.

1 (d) and 2 are schematic cross-sectional views of an element isolation region used in a semiconductor device according to an embodiment of the present invention.
(D), FIG. 3 (d) and FIG. 4 (d). In each of these element isolation regions, a groove 6 formed on the surface of the semiconductor substrate 1 is filled with an insulator 7, a portion formed by protruding the insulator 7 from at least the upper end surface of the groove 6, and the groove 6 Insulating film portions (5) (5, 8) formed on the upper end of the semiconductor substrate 1 in contact with the insulator 7 in which the
(15, 16) (15, 7), which is characterized in that the film thickness of this insulating film portion is made thicker than the film thickness of the gate oxide film formed in the element region. The insulating film portion is composed of a thermal oxide film or a thermal oxide film and a CVD oxide film.

FIGS. 5A and 5B are conceptual views of an element isolation region according to the present invention and a transistor element-isolated by using the element isolation region. In the figure, the region indicated by a is an element formation region, and the region indicated by i is an element isolation region.
It should be noted that the transistor is shown by the gate polycrystalline silicon 20. As can be seen from FIG. 5, by adopting the element isolation structure of the present invention, it is possible to enjoy the advantage of using the trench structure for element isolation, that is, the advantage that the element can be miniaturized, and the trench edge portion (FIG.
Since the film thickness tb of the oxide film 25 above the corner portion (indicated by E in the figure) is formed thicker than the film thickness tox of the gate oxide film 22, the corner E of the semiconductor substrate 1 is sufficiently protected by the thick oxide film 25. It As a result, the electric field concentration at the corners, which has been a problem in the conventional trench isolation method, is alleviated, which causes problems such as kink in the subthreshold region of the transistor and deterioration of reliability of the gate oxide film. There is no.

Next, FIG. 1 (d), FIG. 2 (d), and FIG.
The manufacturing process of the semiconductor device having the element isolation region shown in FIG. 4D and FIG. 4D will be sequentially described.

<Manufacturing Process 1> In order to form the element isolation region of FIG. 1D, the following manufacturing process is performed.

First, a buffer oxide film 2 is formed on a semiconductor (eg, silicon) substrate 1, and then a first mask layer (eg, polycrystalline silicon) 3 and a second mask layer (eg, CVD oxide film) 4 are formed. Film, trench lithography,
Mask RIE is performed to pattern the first mask layer 3 and the second mask layer 4 (FIG. 1A).

First mask layer 3 and second mask layer 4
Is used to selectively oxidize the semiconductor substrate 1 (hereinafter referred to as bird's beak oxidation), and a thermal oxide film such as LOCOS (for example, 100 n
m) 5 is formed (FIG. 1B).

After the oxide film 5 in the unmasked portion is etched and trench RIE is performed to form a trench 6 for element isolation on the surface of the semiconductor substrate 1, annealing / oxidation for protecting the sidewall of the trench is performed. (FIG. 1 (c)).

Insulating material (eg CVD with TEOS
A SiO ₂ film) 7 is deposited from the bottom of the groove 6 to above the second mask layer 4, and etch back or polishing is performed until the first mask layer 3 is exposed. Then, after performing the densification process, the first mask layer 3 is removed (for example, when the mask layer 3 is polycrystalline silicon, CDE is performed).
(FIG. 1 (d)).

As described above, the element isolation region of the present invention is formed. Then, the buffer oxide film 2 is removed, a gate oxide film and a tunnel oxide film are formed again, and a transistor and the like are formed by a known method.

<Manufacturing Process 2> In order to form the element isolation region of FIG. 2D, the following manufacturing process is performed.

First, after forming the buffer oxide film 2 on the semiconductor (eg silicon) substrate 1, film formation, trench lithography and mask RIE are carried out to form the first mask layer (eg polycrystalline silicon) 3 and the first mask layer 3 The mask layer 2 (for example, a CVD oxide film) 2 is patterned. afterwards,
An oxide film (for example, 10 nm) 8 is formed on the side wall of the first mask layer 3 by thermal oxidation (FIG. 2A).

Next, a nitride film 9 is deposited (for example, 25n
m), the nitride film 9 on the upper portion of the second mask layer 4 and on the element isolation region is removed by RIE so that the nitride film 9 remains only on the sidewalls of both mask layers. Then, bird's beak oxidation (for example, 100 nm) is performed (FIG. 2B).

After the oxide film 5 in the unmasked portion is etched and trench RIE is performed to form a trench 6 for element isolation on the surface of the semiconductor substrate 1, annealing / oxidation for protecting the sidewall of the trench is performed. . Then, the nitride film 9 on the sidewall of the mask layer is removed. (FIG. 2 (c)).

An insulating material (eg, TEOS) 7 is deposited from the bottom of the groove 6 to above the second mask layer 4, and etching back or polishing is performed until the first mask layer 3 is exposed. Then, after performing the densify process, the first
The mask layer 3 is removed (for example, when the mask layer 3 is polycrystalline silicon, it is removed by CDE) (FIG. 1D).

As described above, the element isolation region of the present invention is formed. Then, the buffer oxide film 2 is removed, a gate oxide film and a tunnel oxide film are formed again, and a transistor and the like are formed by a known method.

In this embodiment, since the silicon nitride film is deposited on the side wall of the mask layer, there is an advantage that finer device isolation can be achieved by controlling the mask shape by suppressing the oxidation of the side wall of the mask layer. .

<Manufacturing Process 3> In order to form the element isolation region shown in FIG. 3D, the following manufacturing process is performed.

First, after the buffer oxide film 2 is formed on the semiconductor (eg silicon) substrate 1, film formation, trench lithography and mask RIE are performed to form the first mask layer (eg polycrystalline silicon) 3 and the first mask layer 3 2 mask layer (for example, CVD oxide film) 4 is patterned, and then bird's beak oxidation (for example, 30 to 50 nm) is performed (FIG. 3).
(A)).

After depositing the oxide film 16 (for example, 50 nm), the oxide film on the upper part of the second mask layer 4 and the element isolation region is removed so that the oxide film 16 remains only on the sidewalls of both mask layers. (FIG. 3B).

After performing trench RIE to form a trench 6 for element isolation on the surface of the semiconductor substrate 1, annealing / oxidation is performed (FIG. 3C).

An insulating material (eg, TEOS) 7 is deposited from the bottom of the groove 6 to a position above the second mask layer 4, and etching back or polishing is performed until the first mask layer 3 is exposed. Then, after performing the densify process, the first
The mask layer 3 is removed (for example, CDE is used when the mask layer 3 is polycrystalline silicon) (FIG. 3D).

As described above, the element isolation region of the present invention is formed. Then, the buffer oxide film 2 is removed, a gate oxide film and a tunnel oxide film are formed again, and a transistor and the like are formed by a known method.

In the above manufacturing process, bird's beak oxidation may be omitted to simplify the process.

<Manufacturing Process 4> In order to form the element isolation region of FIG. 4D, the following manufacturing process is performed.

First, a buffer oxide film 2 is formed on a semiconductor (eg, silicon) substrate 1, and then a film is formed and a trench PE is formed.
P, mask RIE is performed to perform the first mask layer (eg, polycrystalline silicon) 3 and the second mask layer (eg, CVD).
The oxide film 4 is patterned, and then bird's beak oxidation (for example, 30 to 50 nm) is performed (FIG. 4A).

After the nitride film 26 is deposited (for example, 50 nm), the nitride film 2 is formed on the upper part of the second mask layer 4 and the element isolation region so that the nitride film 26 remains only on the sidewalls of both mask layers.
6 is removed, and the oxide film on the semiconductor substrate 1 is also removed. (FIG.4 (b)).

After performing trench RIE to form a trench 6 for element isolation on the surface of the semiconductor substrate 1, round annealing / round oxidation is performed. Then, the nitride film 26 on the sidewall of the mask layer is removed. (FIG.4 (c)).

An insulating material (for example, TEOS) 7 is deposited from the bottom of the groove 6 to above the second mask layer 4, and etch back or polishing is performed until the first mask layer 4 is exposed. Then, after performing the densify process, the first
Of the mask layer 3 is removed (for example, when the mask layer 3 is polycrystalline silicon, CDE is used) (FIG. 4D).

As described above, the element isolation region of the present invention is formed. Then, the buffer oxide film 2 is removed, a gate oxide film and a tunnel oxide film are formed again, and a transistor and the like are formed by a known method.

In the above manufacturing process, bird's beak oxidation may be omitted to simplify the process.

Next, the above-mentioned manufacturing steps 1 to 3 will be described in more detail. Since the manufacturing process 4 is almost the same as the manufacturing process 3, the following description will be omitted. In addition, description of steps such as the above-mentioned densification process that are not essential to the present invention will be appropriately omitted.

<Manufacturing Process 1> The manufacturing process 1 will be described in more detail with reference to FIGS.

First, 10 to 50 nm is formed on the silicon substrate 1.
Buffer oxide film 2 is formed, and 100-500 is formed on it.
nm thick polycrystalline silicon 3 and 100-500 n
m CVD silicon oxide film 4 is sequentially deposited. The polycrystalline silicon 3 and the CVD silicon oxide film 4 serve as a mask material in a trench etching process for forming a trench 6 which will be described later.

Next, after applying a resist 30 on this, a trench pattern is transferred and formed by photolithography (FIG. 6A).

Using the patterned resist 30 as a mask, the CVD silicon oxide film 4 and the polycrystalline silicon 3 are etched by RIE (FIG. 6).
(B)). In this etching, the CVD silicon oxide film 4 and the polycrystalline silicon 3 may be etched using the resist 30 as a mask and the resist 30 may be peeled off at the end, or the CVD silicon oxide film 4 may be etched using the resist 30 as a mask. Then, the resist 30 is peeled off,
After that, the polycrystalline silicon 3 may be etched by using the CVD silicon oxide film 4 as a mask.

Next, as shown in FIG. 6B, with the CVD silicon oxide film 4 and the polycrystalline silicon 3 patterned and the resist 30 peeled off, the amount of oxidation in the unmasked portion of the silicon substrate 1 is reduced. 30-150n
Thermal oxidation is performed under the condition of about m. By this thermal oxidation,
A thermal oxide film 5 similar to LOCOS selectively grows on the silicon substrate 1, the sidewalls of the polycrystalline silicon, the thermal oxide film, and the lower portion of the polycrystalline silicon (FIG. 7A). Before the selective oxidation, the oxide film 2 between the polycrystalline silicon 3 and the silicon substrate 1 is slightly etched from the side surface (see FIG. 10).
(A)), the bottom of the polycrystalline silicon 3 is slightly wedge-shaped etched (FIG. 10B), and a thermal oxide film is formed under the mask material composed of the CVD silicon oxide film 4 and the polycrystalline silicon 3. 5 may be easy to enter. By doing this, even if the amount of oxidation is reduced, birds with sufficient thickness
Beaks can be formed under the mask.

Thereafter, the entire surface of the wafer is etched by RIE to a degree sufficient to remove the silicon thermal oxide film 5 in the portion (on the substrate) where the polycrystalline silicon 3 is not present (FIG. 7 (b). )).

Since the silicon oxide film RIE is performed on the entire surface in this step, C which should be used as a mask material.
Since the VD silicon oxide film 4 is also etched,
It is desirable to set the thickness of the CVD silicon oxide film 4 so that even after the RIE process, the film thickness is sufficient to serve as a mask material in the subsequent process.

Next, the trench 6 which plays the role of element isolation is formed on the silicon substrate 1 by RIE (FIG. 7C). At this time, the CVD silicon oxide film 4 serves as a mask. The depth of the groove 6 formed on the silicon substrate 1 is
It is desirable to set it to 0.3 to 0.7 μm.

Next, thermal oxidation of 20 to 50 nm is performed in order to protect the side wall of the groove 6 and to round the corner at the entrance of the groove 6 on the surface of the silicon substrate 1 (this oxidation is called round oxidation). . At this time, impurity ions may be implanted through the thermal oxide film (not shown) to enhance the element isolation capability.

Next, after the thermal oxidation, a CVD silicon oxide film (for example, TEOS) 7 is deposited from the bottom of the groove 6 to above the CVD silicon oxide film 4 (FIG. 8A).

Next, etch back is performed until the polycrystalline silicon 3 of the mask material is exposed (FIG. 8B). For this etch back, an etch back technique using a resist may be used, or polishing may be used.

After the CVD oxide film 7 of the trench filling material is flattened as shown in FIG. 8B, next, the polycrystalline silicon 3 of the mask material is removed (FIG. 8C) and further on the element region. The thermal oxide film 2 is removed (FIG. 9). At this time,
At the same time, the bird's beak (the portion shown by b in FIG. 8C) on the element region formed by thermal oxidation (bird's beak oxidation) similar to the LOCOS formation described with reference to (a) is removed. Therefore, it is desirable to select the conditions for etching the silicon oxide film so that they will not end up.

After that, chI / I, gate oxide film formation,
A desired transistor is formed on the element region through processes such as gate polycrystal silicon film deposition, gate patterning formation, and transistor diffusion layer formation. A publicly known technique may be used for this transistor forming step, and thus detailed description thereof will be omitted.

In the transistor manufactured by the steps described above, the end of the element region (end of the groove) is protected by a thermal oxide film such as a bird's beak thicker than the gate oxide film. Therefore, as described above, problems such as the appearance of kinks in the subthreshold characteristics of the transistor and the deterioration of the gate breakdown voltage due to the electric field concentration at the corners of the element region edges do not appear.

In this embodiment, polycrystalline silicon and a CVD silicon oxide film are used as the mask material, but in addition, it functions as a mask during the selective thermal oxidation and functions as a mask during the silicon substrate RIE and the planarization process. Any thing may be used as long as it is a thing. For example, silicon nitride and C
A combination of VD silicon oxide films, a single layer film of silicon nitride, and the like are considered.

<Manufacturing Process 2> Next, the manufacturing process 2 will be described in more detail with reference to FIGS. 11 to 14.

First, 10 to 50 nm is formed on the silicon substrate 1.
Buffer oxide film 2 is formed, polycrystalline silicon 3 is deposited thereon to a thickness of about 100 to 500 nm, and CVD silicon oxide film 4 is further deposited to a thickness of about 100 to 500 nm.

Next, a resist 30 is applied on this, and a trench pattern is transferred / formed by photolithography (FIG. 11A).

Using the patterned resist 30 as a mask, the CVD silicon oxide film 4 and the polycrystalline silicon 3 are etched by RIE (FIG. 11).
(B)). In this etching, the CVD silicon oxide film 4 and the polycrystalline silicon 3 may be etched using the resist 30 as a mask, and the resist 30 may be peeled off at the end. Alternatively, the CVD silicon oxide film 4 is etched using the resist 30 as a mask, the resist 30 is peeled off,
After that, the polycrystalline silicon 3 may be etched by using the CVD silicon oxide film 4 as a mask.

Next, the polycrystalline silicon 3 is set to 10 to 30 nm.
Oxidation forms an oxide film 8 on the side wall (FIG. 11).
(C)). Alternatively, the CVD silicon oxide film may be replaced with 10 to 3
0 nm is deposited (FIG. 11D). After that, a silicon nitride film 9 is deposited (for example, 25 nm) (FIG. 12).
(A)).

Next, RIE is performed so as to leave only the portion of the deposited silicon nitride film 9 formed on the side wall of the mask material.
Then, the silicon nitride film is removed by RIE, and then the buffer oxide film 2 in the portion without the mask material is removed by RIE (FIG.
(B)).

Thermal oxidation (bird's beak oxidation) is performed so that the oxide film thickness of the exposed portion of the silicon substrate 1 becomes about 50 nm (FIG. 12C). At this time, the silicon nitride film 9 prevents the side wall of the polycrystalline silicon 3 from being oxidized.

Thereafter, the entire surface of the wafer is etched by RIE to a degree sufficient to remove the silicon thermal oxide film 5 in the portion where the polycrystalline silicon 3 is absent (FIG. 13A).

Since the silicon oxide film RIE is performed on the entire surface in this step, C which should be used as a mask material is used.
Since the VD silicon oxide film 4 is also etched,
It is desirable to set the thickness of the CVD silicon oxide film 4 so that even after the RIE process, the film thickness is sufficient to serve as a mask material in the subsequent process.

Next, trenches 6 which serve as element isolations are formed on the silicon substrate 1 by RIE (FIG. 13B).
At this time, the CVD silicon oxide film 4 serves as a mask. The depth of the groove 6 formed on the silicon substrate 1 is
It is desirable to set it to 0.3 to 0.7 μm.

Next, in order to protect the side wall of the groove 6 and to round the corner at the entrance of the groove 6 on the surface of the silicon substrate 1, thermal oxidation of 20 to 50 nm is performed.

Then, the silicon nitride film attached to the side wall of the mask material is removed by etching with CDE or hot phosphoric acid. At this time, etching may be required to remove the silicon oxide on the silicon nitride prior to the silicon nitride etching. Before and after the etching, impurity ions may be implanted through the thermal oxide film (not shown) to enhance the element isolation ability.

After that, a CVD silicon oxide film 7 is deposited to fill the groove (FIG. 13C). Then, etch back is performed by silicon oxide film RIE or CMP,
The polycrystalline silicon film 3 is exposed and planarized (FIG. 14A).

After removing the polycrystalline silicon 3 (see FIG.
4 (b)), the buffer oxide film 2 is etched (FIG. 1).
4 (c)). At this time, it is desirable to set etching conditions so that the trench edge is not exposed.

Then, a transistor is formed in the element forming region by a known technique.

The transistor thus manufactured is
Since the element region edge exists inside the trench edge, the appearance of a kink of the subthreshold characteristic of the transistor,
It is possible to prevent deterioration of the gate breakdown voltage due to electric field concentration at the end of the same region.

Further, in this embodiment, a finer device isolation can be achieved by depositing a silicon nitride film on the side wall of the mask and controlling the mask shape.

<Manufacturing Process 3> Next, the manufacturing process 3 will be described in more detail. First, a description will be given of the manufacturing process 3 omitting the bird's beak oxidation process described above.

FIG. 15 is a plan view of a transistor device using trench element isolation according to this embodiment.
FIG. 16 shows a cross-sectional view taken along the line AA ′ of FIG.

In each transistor, the gate is formed by the first-layer polycrystalline silicon film 20 of 50 to 400 nm formed on the P-type well via the gate insulating film 22 of the thermal oxide film of 5 to 40 nm. There is. A groove 6 having a depth of 0.3 to 0.7 μm is formed between the transistors, and a TEOS CVD film 7 which is an insulating material is embedded therein. A CVD thicker than the gate oxide film is formed on the upper portion of the edge portion (corner portion indicated by F in FIG. 16) of the trench.
A silicon oxide film 16 is formed, which protects the corners of the edge portion.

Next, a specific manufacturing process of this embodiment will be described with reference to FIGS.

According to a normal process, first, a P-type well is formed on the n-type silicon substrate 1. Then, after forming the thermal oxide film 2 as a buffer oxide film, for example, 100 to 500
A first layer polycrystalline silicon film 3 having a thickness of nm is deposited. And
A second-layer silicon oxide film 4 serving as a mask during trench RIE is deposited thereon, for example, to have a thickness of about 100 to 500 nm (FIG. 17A).

Then, the second layer silicon oxide film 4 and the first layer polycrystalline silicon 3 are patterned by photoresist processing (FIG. 17B).

Next, by LP-CVD, for example, 30 to
A silicon oxide film 16 having a film thickness of 100 nm is deposited (FIG. 17C).

After that, the film 16 is left only on the sidewalls of the first and second layers to be the mask by RIE (FIG. 17).
(D)).

Next, in this state, the substrate material 1 is etched to form a groove. Then, thermal oxidation of 20 to 50 nm is performed in order to protect the side wall of the groove 6. At this time, impurity ions may be implanted through the thermal oxide film 32 to enhance the element isolation capability.

Next, after the thermal oxidation, an insulating material 7 such as a CVD silicon oxide film (eg, TEOS) is deposited from the bottom of the groove 6 to above the CVD silicon oxide film 4. After that, for example, the entire surface of the substrate is flattened by etching or polishing to expose the polycrystalline silicon 3 of the first layer, and then the polycrystalline silicon 3 is removed by the CDE process. Then, after removing the buffer oxide film 2, a transistor is formed on the element region by a known method (FIG. 1).
8).

According to this embodiment, since the trench edge portion F in contact with the gate oxide film is protected by the thick silicon oxide film attached to the side wall, the subsequent NH
It is possible to prevent the exposure of the trench edge portion due to the ₄ F treatment. Further, it is possible to prevent the occurrence of electric field concentration at the trench edge portion F.

Next, an example in which the bird's beak oxidation step is carried out in the manufacturing step 3 will be described.

The plan view of the transistor device using the trench element isolation according to the present embodiment is similar to that of FIG. 15 described above and therefore omitted, and a sectional view taken along the line AA ′ corresponding to FIG. 19 is shown. A groove 6 having a depth of 0.3 to 0.7 μm is formed between the transistors, and TEOS 7 which is an insulating material is embedded therein. Edge of trench (F 'in FIG. 19
In addition to the CVD silicon oxide film 16 attached to the side wall of the polycrystalline silicon 20 of the gate, the bird's beak type oxide film 1 oxidized in the stage before the side wall is attached
5 covers the edge part.

Next, a specific manufacturing process of this embodiment will be described with reference to FIGS. Note that, here, a part different from the above-described process of omitting bird's beak oxidation will be described.

The first layer 3 and the second layer 4 are formed by the method as described above.
Is deposited, patterned, and then oxidized to a thickness of 30 to 150 nm. By this oxidation, the first layer 3, which is a mask,
A bird's beak type oxide film is formed in the region where the second layer 4 is etched (FIG. 20).

Then, by LP-CVD, for example, 30
A silicon oxide film 16 having a film thickness of ˜100 nm is deposited.
Next, the film 16 is left on the side walls of the first layer 3 and the second layer 4 which will be masks by RIE (FIG. 21).

Then, after removing the silicon oxide film 15 on the silicon substrate 1 by RIE, the silicon substrate material 1 is etched to form trenches 6.

The manufacturing is performed by the method as described above.

According to this embodiment, the trench edge in contact with the gate oxide film is protected by the CVD silicon oxide film or the bird's beak type oxide film attached to the side wall so as to protect the edge portions F and F '. It is thick and the NH ₄ F treatment thereafter can prevent the exposure of the trench edge portion. Further, it is possible to prevent electric field concentration from occurring at the trench edge.

Here, in the above description of each embodiment,
Although a single transistor structure is used, the trench element isolation structure according to the present invention can be applied not only to a logic semiconductor integrated circuit but also to a cell structure such as DRAM, SRAM, NOR type or NAND type EEPROM. is there.

In particular, FIG. 22 shows a schematic cross-sectional view when the present invention is applied to a cell of a nonvolatile memory. The present invention is further effective for a memory cell in which a high voltage is applied to the tunnel oxide film to write / erase. In this example, a floating gate, an ONO insulating film, and a control gate are stacked on the element region separated by the method shown in the embodiment relating to the above [Manufacturing Step 1] to form a memory cell. Since a known technique may be used to form this memory cell, it will not be described in detail here.

According to this embodiment (FIG. 22), the corner formed at the end of the element region is protected by the thick insulating film 5 and is isolated from the floating gate. Therefore, even if the potential difference between the floating gate and the substrate is increased by applying a high voltage to the control gate during writing / erasing, electric field concentration occurs at the edge of the element region, and the electric field at the edge of the element region is higher than the electric field at the center of the element region. Does not grow.

Therefore, the reliability of the gate oxide film can be improved as compared with the conventional example. Further, at the same time, charges can be exchanged at the time of writing / erasing by using the oxide film in the portion of which the quality is stable in the center of the element region.
It is possible to reduce the variation in the threshold voltage of the cell transistor during writing / erasing.

In the above description, the case where the method shown in the embodiment relating to the above [Manufacturing Step 1] is used is explained.
The same effect can be expected by using other embodiments.

Further, the present invention is not limited to the above-mentioned respective embodiments, and various modifications can be carried out without departing from the scope of the invention.

[0118]

As described above, according to the present invention, the upper end (corner) of the semiconductor substrate material in contact with the element isolation region is protected by the insulating film thicker than the gate oxide film. It is possible to effectively alleviate the electric field concentration at the corners, which was a problem with the trench isolation.

As a result, it is possible to avoid the kink in the subthreshold region of the transistor, and
The reliability of the gate oxide film can be improved.

Moreover, since the trench structure is used in the main part of the element isolation region, the element can be miniaturized.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method of manufacturing an element isolation region according to an embodiment of the present invention.

FIG. 2 is a process sectional view showing a method of manufacturing an element isolation region according to another embodiment of the present invention.

FIG. 3 is a process sectional view showing a method of manufacturing an element isolation region according to still another embodiment of the present invention.

FIG. 4 is a process sectional view showing a method of manufacturing an element isolation region according to still another embodiment of the present invention.

FIG. 5 is a conceptual diagram of an element isolation region of the present invention and a transistor element-isolated using the element isolation region.

FIG. 6 is a process sectional view showing a method for manufacturing an element isolation region according to an embodiment of the present invention.

FIG. 7 is a process sectional view showing the method of manufacturing the element isolation region.

FIG. 8 is a process sectional view showing the method of manufacturing the element isolation region.

FIG. 9 is a process sectional view showing the method of manufacturing the element isolation region.

FIG. 10 is a process sectional view showing the method of manufacturing the element isolation region.

FIG. 11 is a process sectional view showing a method of manufacturing an element isolation region according to another embodiment of the present invention.

FIG. 12 is a process sectional view showing the method of manufacturing the element isolation region.

FIG. 13 is a process sectional view showing the method of manufacturing the element isolation region.

FIG. 14 is a process sectional view showing the method of manufacturing the element isolation region.

FIG. 15 is a plan view of a transistor device using an element isolation region according to still another embodiment of the present invention.

16 is a cross-sectional view taken along the line AA ′ of the plan view shown in FIG.

FIG. 17 is a schematic sectional view in each forming step of the step sectional view showing the method for manufacturing the element isolation region.

FIG. 18 is a process sectional view showing the method of manufacturing the element isolation region.

FIG. 19 is a sectional view of a transistor device using an element isolation region according to still another embodiment of the present invention.

FIG. 20 is a process sectional view showing the method of manufacturing the element isolation region.

FIG. 21 is a process sectional view showing the method of manufacturing the element isolation region.

FIG. 22 is a cross-sectional view of a nonvolatile memory cell manufactured by using the element isolation method of the present invention.

FIG. 23 is a diagram for explaining conventional LOCOS isolation and trench isolation.

FIG. 24 is a diagram showing sub-threshold characteristics of a conventional trench isolation and a transistor which is element-isolated by trench isolation.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Buffer oxide film, 3 ... 1st mask layer, 4 ... 2nd mask layer, 5 ... Thermal oxide film, 6 ... Trench, 7
Insulator, 8 ... Thermal oxide film, 9 ... Nitride film, 16 ... Silicon oxide film, 20 ... Gate polycrystalline silicon, 22 ... Gate oxide film, 25 ... Oxide film, 26 ... Nitride film, 30 ... Resist,
31 ... CVD silicon oxide film, 41 ... Floating gate, 42
... ONO insulating film, 43 ... Control gate

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Toru Maruyama Toru Maruyama 1 Komukai Toshiba Town, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Toshiba Research and Development Center (72) Inventor Hiroshi Watanabe Komukai Toshiba Town, Kawasaki City, Kanagawa Prefecture No. 1 in Toshiba Research and Development Center Co., Ltd. (56) Reference JP-A-6-21208 (JP, A) JP-A-3-101147 (JP, A) JP-A-6-21210 (JP, A) JP-A 61-214446 (JP, A) JP-A-5-3246 (JP, A) JP-A-5-41526 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/70 -21/74 H01L 21/76-21/765 H01L 21/77

Claims (2)

(57) [Claims] 1. A step of removing a portion to be an element isolation region from a first mask layer and a second mask layer sequentially stacked on a semiconductor substrate with a buffer oxide film interposed therebetween, and a step of performing bird's beak oxidation. Removing the oxide film on the semiconductor substrate by RIE using the mask layer, etching the semiconductor substrate using the mask layer to form a groove, and removing the second mask layer from the bottom of the groove. Depositing an insulator to the upper part, planarizing the deposited insulator until the upper end portion of the first mask layer is exposed, and removing the first mask layer and the buffer oxide film sequentially. A method of manufacturing a semiconductor device, comprising: a step of forming a desired element in an element formation region. 2. A step of removing a portion to be an element isolation region from a first mask layer and a second mask layer laminated on a semiconductor substrate via a buffer oxide film, and a step of performing bird's beak oxidation. Forming an oxide film on the sidewall of the previously deposited mask layer; removing the oxide film on the semiconductor substrate by RIE using the mask layer and the sidewall ; and forming the semiconductor substrate using the mask layer and the sidewall. Etching to form a groove; depositing an insulator from the bottom of the groove to above the second mask layer; exposing the deposited insulator to the upper end portion of the first mask layer Manufacturing a semiconductor device, comprising: a step of planarizing; a step of sequentially removing the first mask layer and the buffer oxide film; and a step of forming a desired element in an element forming region. Law.