JP3382063B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a bipolar transistor or a BiCMOS type semiconductor device including a bipolar transistor and a MOS transistor, and more particularly to an element isolation technique.

[0002]

2. Description of the Related Art An element isolation technique in a conventional semiconductor device manufacturing method is shown in FIG.
A method is employed in which a field oxide film is formed by the COS method, a deep groove is formed in a silicon substrate, and the surface thereof is thermally oxidized to fill the inside of the groove with polysilicon. Alternatively, as shown in FIGS. 16 to 19, after forming a deep groove, the inside of the groove and the substrate surface are simultaneously oxidized by LOCOS oxidation, and polysilicon is embedded in the inside of the groove.

That is, the former manufacturing method is as follows.
As shown in FIG. 1, the main surface of the silicon substrate 11 is thermally oxidized to form the SiO ₂ film 12, and then the Si ₃ N ₄ film 13 which is an oxidation resistant film is formed on the SiO ₂ film 12 and patterned. And left on the element region. Next, as shown in FIG. 12, the field oxide film 14 is formed by thermally oxidizing the main surface of the substrate 11 using the Si ₃ N ₄ film 13 as a mask. After that, the Si ₃ N ₄ film 13 is removed, and S
Si ₃ N _{4 is formed} on the iO ₂ film 12 and the field oxide film 14.
The film 15 is formed. Then, when the CVD-SiO ₂ film 16 is formed on the Si ₃ N ₄ film 15, it becomes as shown in FIG.

Next, trenches 17-1 and 17-2 having a sufficient depth are formed in the substrate 11 by anisotropic etching such as RIE (see FIG. 14). An oxide film 18- is formed by thermally oxidizing the surface of the substrate 11 exposed in the grooves 17-1 and 17-2.
After forming 1 and 18-2, the trenches 17-1 and 17-2 are filled with polysilicon layers 19-1 and 19-2. Then, the polysilicon layer 19 in the grooves 17-1 and 17-2 is formed.
-1, 19-2 surface is thermally oxidized to SiO ₂ film 20-
1, 20-2 are formed, and the CVD-SiO ₂ film 16 and S are formed.
By removing the i ₃ N ₄ film 15, an element isolation structure as shown in FIG. 15 is obtained.

Thereafter, although not shown, a semiconductor element such as a bipolar transistor is formed in the element region separated by the field oxide film 14 and the grooves 17-1 and 17-2 by a known manufacturing method.

On the other hand, in the latter method, as shown in FIG. 16, first, the main surface of the silicon substrate 21 is thermally oxidized to Si.
After the O ₂ film 22 is formed and the Si ₃ N ₄ film 23 which is an oxidation resistant film is formed on the SiO ₂ film 22, it is patterned and left on the element region. A CVD-SiO ₂ film 24 is formed on the entire surface of the SiO ₂ film 22 and the Si ₃ N ₄ film 23. Next, C in the area where the field oxide film is to be formed
The VD-SiO ₂ film 24, the SiO ₂ film 22 and the substrate 21 are selectively etched by anisotropic etching such as RIE to form grooves 25-1 and 25-2 having a sufficient depth. Then, the CVD-SiO ₂ film 24 and Si ₃ N
_{When the} SiO ₂ film 22 which is not masked by the ₄ film 23 is removed, the surface of the substrate 21 is exposed as shown in FIG. Subsequently, the Si ₃ N ₄ film 23 is used as a mask to selectively oxidize the surface of the substrate 21 and the surface of the substrate 21 exposed in the grooves 25-1 and 25-2 to function as a field oxide film as shown in FIG. The SiO ₂ film 26 is formed. After that, the polysilicon layers 2 are formed in the grooves 25-1 and 25-2.
The polysilicon layer 27 is filled with 7-1 and 27-2.
-1 and 27-2 exposed surfaces are thermally oxidized to SiO ₂ film 28-
1, 28-2 are formed. Then, after removing the Si ₃ N ₄ film 23 remaining on the element region, a semiconductor element such as a bipolar transistor is formed in the element region by a known manufacturing method.

However, as described above, LOCOS
In the conventional method for manufacturing a semiconductor device in which the field oxide film is formed by using the method, a bird's beak having a length equivalent to the field oxide film is formed. It is an obstacle to integration. Further, if the bird's beak is large, the parasitic capacitance in this portion becomes large, which is also a factor that hinders the speedup of the device. Further, in the method of burying the polysilicon layer in the trench for element isolation, it is necessary to form an insulating film such as a thermal oxide film on the sidewall of the trench for element isolation, and the polysilicon embedded in the trench is buried. There is a problem that parasitic capacitance is formed between the layer and the silicon substrate, which hinders high-speed operation of the device.

[0008]

As described above, in the conventional method for manufacturing a semiconductor device, the existence of the element isolation region hinders high integration, or parasitic capacitance is formed in the element isolation region, which increases the speed. There was a problem that it became a hindrance factor.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of achieving high integration and high speed.

[0010]

[0011]

[0012]

[0013]

[0014]

[0015]

A method of manufacturing a semiconductor device according to claim 1 of the present invention comprises a step of forming a first film on a semiconductor substrate and a second film on the first film. Forming a first groove by selectively removing the first film, the second film, and the semiconductor substrate, and forming a third groove on the surface of the first groove. Film forming step, forming a fourth film over the entire surface, and using the second film as a stopper to flatten the fourth film and leave it in the first groove. A step of sequentially forming a fifth film and a sixth film on the entire surface, and the sixth, fifth and fourth steps
And a step of selectively removing the third film, a step of removing the semiconductor substrate in the removed region to form a second groove, a step of removing the sixth film, and a step of removing the second film. Forming a seventh film on the exposed surface of the groove, forming an eighth film on the entire surface, and using the fifth film as a stopper to flatten the eighth film to form the first film. The method is characterized by including a step of leaving the eighth film in the second groove and a step of removing the fifth, second, and first films.

According to a second aspect of the present invention, the method further comprises the step of forming a semiconductor element on the surface region of the semiconductor substrate exposed by removing the fifth, second and first films. And

Further, according to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the surface of a silicon substrate is thermally oxidized to form a first silicon oxide film, and the first silicon oxide film is formed on the first silicon oxide film. A step of forming a first silicon nitride film, which serves as a stopper for chemical mechanical polishing, and a step of forming the first silicon oxide film, the first silicon nitride film, and the silicon substrate in a region where an element isolation region is to be formed. Isotropic etching to form a first groove, a step of forming a second silicon oxide film on the surface of the silicon substrate exposed in the first groove, and a third silicon oxide film on the entire surface. And a step of forming the third silicon oxide film by chemical mechanical polishing to a depth reaching the first silicon nitride film to planarize the third silicon oxide film into the first trench. A step of leaving the recon oxide film, a step of sequentially forming a second silicon nitride film and a fourth silicon oxide film on the entire surface, and anisotropic etching to perform the fourth silicon in the first groove. Selectively removing an oxide film, the second silicon nitride film, the third silicon oxide film, and the second silicon oxide film;
A step of forming a second groove by performing anisotropic etching to remove the semiconductor substrate in the removed region; a step of removing the fourth silicon oxide film; and a step of removing the second trench in the second groove. Forming a fifth silicon oxide film on the exposed surface of the silicon substrate, forming a sixth silicon oxide film on the entire surface by a CVD method, and forming the sixth silicon oxide film on the second silicon. A step of leaving the sixth silicon oxide film in the second groove by chemical-mechanical polishing to a depth reaching the nitride film and leaving the sixth silicon oxide film, and the fourth silicon oxide film, the first silicon nitride film, And removing the first silicon oxide film to expose the surface of the element region of the silicon substrate, and forming a semiconductor element in the element region of the silicon substrate. It is characterized in that. Claim
As described in Item 4 , the depth of the first groove is shallower than 1.5 μm, and the depth of the second groove is at least 3.0 μm.

[0018]

[0019]

According to the above-described manufacturing method, since the LOCOS method is not used for forming the element isolation region, there is a problem in using the LOCOS method that the integration density is lowered due to bird's beak and the operating speed is reduced due to parasitic capacitance. No reduction occurs, and high integration and high speed can be achieved.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional configuration diagram of a semiconductor device according to an embodiment of the present invention. In FIG. 1, a bipolar transistor is shown as an example of the semiconductor device according to the present invention. In FIG. 1, 31 is a P-type silicon substrate, 32 is an N ⁺ -type buried layer, 33 is an N-type epitaxial layer, 36-1 and 36-2 are first grooves, and 37 is a second groove.
SiO ₂ film, 38 is the first CVD-SiO ₂ film, 41
-1, 41-2 is the second groove, 42-1 and 42-2 is the third groove
Thermal SiO ₂ film, 43-1 and 43-2 are the third CVD-
SiO ₂ film, 44 is an emitter region, 45 is a base region,
46 is a polysilicon layer, 47 is an emitter electrode, 48 is a polysilicon layer, 49 is a fourth CVD-SiO ₂ film, 50
Is a base electrode.

As shown in FIG. 1, the first grooves 36-1, 36 are formed.
-2, CVD formed in the grooves 36-1 and 36-2
-SiO ₂ film 38, second grooves 41-1, 41-2, and CVD-Si formed in the grooves 41-1 and 41-2.
The O ₂ films 43-1 and 43-2 function as element isolation regions.
The element isolation region isolates the bipolar transistor from other elements. Therefore, a bird's beak, which is a problem when the field oxide film is formed by the LOCOS method, is not formed, and it is not necessary to enlarge the element region, so that high integration can be achieved. Further, since the parasitic capacitance in the element isolation region is small, the speeding up of the device is not hindered.

2 to 10 sequentially show manufacturing steps of the semiconductor device shown in FIG. 1, which are formed by the following steps (1) to (10). (1) First, in the main surface region of the P-type silicon substrate 31,
A semiconductor wafer having an N ⁺ type buried layer 32 and an N type epitaxial layer 33 formed thereon is prepared. On this semiconductor wafer, a first thermal SiO ₂ film 34 and a CMP (Chemical Mechanical) in a later process are formed.
The first Si ₃ N that serves as a stopper for
_{4 The} film 35 is formed (see FIG. 2).

(2) A mask is formed by performing a photolithography process, and the first Si ₃ N ₄ other than the element forming region is formed.
The film 35 and the first thermal SiO ₂ film 34 are removed by the RIE method, and the epitaxial layer 33 is continuously etched by about 0.7 μm by the RIE method using this mask to form shallow trenches 36-1, 36-2. To form. This groove 36-1, 36
The depth of -2 needs to be set according to the element to be formed and the required characteristics, but normally the epitaxial layer 33 is used.
Is less than or equal to the film thickness (see FIG. 3).

(3) Then, in order to recover the damage caused by the RIE, the surfaces of the shallow grooves 36-1 and 36-2 are etched using a solution or CDE to remove the surface of the epitaxial layer 33 by about 10 nm. . After this,
The surface of the epitaxial layer 33 is thermally oxidized by about 10 nm,
A second SiO ₂ film 37 is formed. Next, CVD-Si
An O ₂ film 38 is formed on the entire surface of the wafer and flattened by CMP. At this time, the first Si ₃ N ₄ film 35 acts as a stopper, and the end of polishing can be determined. As a result, the shallow grooves 36-1 and 36-2 are completely formed by CVD-SiO.
It can be embedded with _two films 38 (see FIG. 4).

(4) Next, the CVD-SiO ₂ film 38 is formed.
Also, a second Si ₃ N ₄ film 39 serving as a CMP stopper film is formed on the first Si ₃ N ₄ film 35, and Si is used when a deep groove is formed on the Si ₃ N ₄ film 39. -RI
A second CVD-SiO ₂ film 40 serving as a mask material at the time of E is formed (see FIG. 5).

(5) A mask is formed by photolithography, and the second CVD-Si in a region where a deep groove is to be formed.
O ₂ film 40, second Si ₃ N ₄ film 39, first CVD-
The SiO ₂ film 38 and the second thermal SiO ₂ film 37 are etched by the RIE method (see FIG. 6).

(6) Next, the above-mentioned second CVD-SiO ₂
Using the film 40 as a mask, the epitaxial layer 33, the buried layer 32, and the silicon substrate 31 are etched by the RIE method to form the second trenches 41-1 and 41-2.
The depths of the second grooves 41-1 and 41-2 reach the silicon substrate 31. After this, the second CVD-S
In order to remove the iO ₂ 40 film and remove the damage due to RIE, the second groove 41-1 and
About 10 nm of silicon in 41-2 is removed (see FIG. 7).

After the shallow grooves 36-1 and 36-2 are formed in this way, they are flattened and then deep grooves 41-1 and 41- are formed.
2 is formed to form an element isolation region.
As shown in (1), the width in which the deep grooves 41-1 and 41-2 can be formed from the boundary between the shallow grooves 36-1 and 36-2 and the element region can be shortened to near the limit of the alignment accuracy of photolithography. If this width is wide, the element area is consequently increased and the advantage of high integration is lost.
With the method of manufacturing a semiconductor device according to the present invention, the alignment accuracy of photolithography can be shortened to near the limit, and it is effective for miniaturization and high integration of elements.

(7) After that, the second grooves 41-1, 41-
The third thermal SiO ₂ films 42-1 and 42-2 are formed in the wafer 2, and the third CVD-SiO ₂ film 43 is formed on the entire surface of the wafer. As a result, the second grooves 41-1 and 41-2 become S
It is filled with the iO ₂ film 43 (see FIG. 8).

(8) Third C on the wafer surface by CMP
The VD-SiO ₂ film 43 is removed, and the second grooves 41-1 and 4-4 are formed.
The third CVD-SiO ₂ films 43-1 and 4-4 are provided only within 1-2.
Remain 3-2. At this time, the second Si ₃ N ₄ film 39
Acts as a stopper for CMP (see FIG. 9).

(9) Next, the second and first Si ₃ N ₄ films 39 and 35 are etched and removed, and the thermal SiO ₂ film 34 in the element forming region is removed. Through the above steps, the N-type epitaxial layer 33 can be exposed only in the region where the element is formed, and the other regions can be completely separated by the insulating film (see FIG. 10).

(10) Thereafter, a normal bipolar transistor forming process is performed to form a bipolar transistor as shown in FIG. In the structure shown in FIG. 1, the emitter region 44 is formed using the polysilicon layer 46 as a diffusion source, and the emitter electrode 47 made of aluminum or the like is formed on the polysilicon layer 46. The polysilicon layer 48 is for leading out the base region 45, and is connected to a base electrode 50 made of aluminum or the like through a contact hole formed in the SiO ₂ film 49 on the polysilicon layer 48. The collector electrode is formed on the back surface side of the silicon substrate 31.

According to the manufacturing method described above, since a thick thermal SiO ₂ film such as a field oxide film formed by the LOCOS method is not formed, a large bird's beak does not occur in the element region, and the element region is the minimum required by the device. It is possible to reduce the area of the device, and high integration of the device can be achieved. Further, along with this, the parasitic capacitance also decreases, so that the operating speed can be increased.

Furthermore, the CVs are formed in the deep grooves 41-1 and 41-2.
Since the D-SiO ₂ films 43-1 and 43-2 are embedded, the width of the grooves 41-1 and 41-2 can be reduced as compared with the conventional manufacturing method in which the polysilicon layer is embedded, and the grooves 41-1 are formed. , 41-2 itself can also reduce the parasitic capacitance, and also in this respect, high integration and high speed can be achieved.

[0035]

As described above, according to the present invention, it is possible to obtain a method of manufacturing a semiconductor device which can achieve high integration and high speed.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the first manufacturing process of the semiconductor device shown in FIG. 1, for illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

3A and 3B are sectional views showing a second manufacturing process of the semiconductor device shown in FIG. 1, for illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention.

FIG. 4 is a cross-sectional view showing the third manufacturing process of the semiconductor device shown in FIG. 1, for illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

5A and 5B are cross-sectional views showing a fourth manufacturing process of the semiconductor device shown in FIG. 1, for illustrating a method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 6 is a cross-sectional view showing the fifth manufacturing process of the semiconductor device shown in FIG. 1, for illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 7 is a cross-sectional view showing the sixth manufacturing step of the semiconductor device shown in FIG. 1, for illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 8 is a cross-sectional view showing the seventh manufacturing step of the semiconductor device shown in FIG. 1, for illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

9 is a cross-sectional view showing the eighth manufacturing step of the semiconductor device shown in FIG. 1, for illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

10 is a cross-sectional view showing the ninth manufacturing step of the semiconductor device shown in FIG. 1, for illustrating the method for manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 11 is a cross-sectional view showing a first manufacturing process for explaining a conventional semiconductor device and a manufacturing method thereof.

FIG. 12 is a cross-sectional view showing a second manufacturing process for explaining the conventional semiconductor device and the manufacturing method thereof.

FIG. 13 is a cross-sectional view showing a third manufacturing step for explaining the conventional semiconductor device and the manufacturing method thereof.

FIG. 14 is a cross-sectional view showing a fourth manufacturing process for explaining a conventional semiconductor device and a manufacturing method thereof.

FIG. 15 is a cross-sectional view showing a fifth manufacturing process for explaining a conventional semiconductor device and a manufacturing method thereof.

FIG. 16 is a cross-sectional view showing the first manufacturing process for explaining another conventional semiconductor device and the manufacturing method thereof.

FIG. 17 is a cross-sectional view showing a second manufacturing process for explaining another conventional semiconductor device and a method for manufacturing the same.

FIG. 18 is a cross-sectional view showing a third manufacturing step for explaining another conventional semiconductor device and a method for manufacturing the same.

FIG. 19 is a cross-sectional view showing a fourth manufacturing process for explaining another conventional semiconductor device and the manufacturing method thereof.

[Explanation of symbols]

31 ... P type silicon substrate, 32 ... N ⁺ type buried layer, 3
3 ... N-type epitaxial layer, 34 ... First thermal SiO ₂
Film, 35 ... First Si ₃ N ₄ film, 36-1, 36-2 ...
Shallow groove (first groove), 37 ... Second SiO ₂ film, 38 ...
CVD-SiO ₂ film, 39 ... Second Si ₃ N ₄ film, 40
... second CVD-SiO ₂ film, 41-1, 41-2 ... Deep groove (second groove) 42-1, 42-2 ... third heat Si
O ₂ film, 43, 43-1, 43-2 ... Third CVD-S
iO ₂ film, 44 ... Emitter region, 45 ... Base region, 4
6 ... Polysilicon layer, 47 ... Emitter electrode, 48 ... Polysilicon layer, 49 ... Fourth CVD-SiO ₂ film, 50 ...
Base electrode.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 29/73 (56) Reference JP-A-5-315442 (JP, A) JP-A-2-90617 (JP, A) ( 58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/76 H01L 21/331 H01L 21/8222 H01L 21/8249 H01L 27/06 H01L 29/73

Claims (4)

(57) [Claims] 1. A step of forming a first film on a semiconductor substrate, a step of forming a second film on the first film, the first film, the second film, and A step of forming a first groove by selectively removing the semiconductor substrate, a step of forming a third film on the surface of the first groove, and a step of forming a fourth film on the entire surface, Using the second film as a stopper, planarizing the fourth film to leave it in the first groove; forming a fifth film and a sixth film sequentially on the entire surface; A step of selectively removing the sixth, fifth, fourth, and third films; a step of removing the semiconductor substrate in the removed region to form a second groove; and a step of removing the sixth film. A step of removing, a step of forming a seventh film on the exposed surface in the second groove, a step of forming an eighth film on the entire surface, and a step of removing the fifth film. A step of flattening the eighth film to leave the eighth film in the second groove by using it as a topper, and a step of removing the fifth, second and first films. A method for manufacturing a semiconductor device, comprising: 2. The method according to claim 1 , further comprising the step of forming a semiconductor device on a surface region of the semiconductor substrate exposed by removing the fifth, second and first films. A method for manufacturing a semiconductor device as described above. 3. A step of thermally oxidizing the surface of a silicon substrate to form a first silicon oxide film, and forming a first silicon nitride film on the first silicon oxide film to serve as a stopper for chemical mechanical polishing. And a step of anisotropically etching the first silicon oxide film, the first silicon nitride film, and the silicon substrate in a region where an element isolation region is to be formed to form a first groove, Forming a second silicon oxide film on the surface of the silicon substrate exposed in the first groove, forming a third silicon oxide film on the entire surface, and forming the third silicon oxide film on the surface of the silicon substrate. A step of leaving the third silicon oxide film in the first groove by chemical mechanical polishing to a depth reaching the first silicon nitride film and planarizing the silicon nitride film.
A step of sequentially forming a second silicon nitride film and a fourth silicon oxide film on the entire surface, and anisotropic etching to perform the fourth silicon oxide film and the second silicon nitride in the first trench. A step of selectively removing the film, the third silicon oxide film, and the second silicon oxide film; and a second step by performing anisotropic etching to remove the semiconductor substrate in the removed region. A step of forming a groove, a step of removing the fourth silicon oxide film, a step of forming a fifth silicon oxide film on the surface of the silicon substrate exposed in the second groove, and a CVD method. Forming a sixth silicon oxide film on the entire surface, planarizing the sixth silicon oxide film by chemical mechanical polishing to a depth reaching the second silicon nitride film, and then forming the first silicon oxide film in the second groove. 6 Leaving the silicon oxide film, and removing the fourth silicon oxide film, the first silicon nitride film, and the first silicon oxide film to expose the surface of the element region on the silicon substrate. And a step of forming a semiconductor element in the element region of the silicon substrate. 4. A depth of the first groove is shallower than 1.5 [mu] m, claims 1 to 3 any one of claims, wherein the depth of said second groove is at least 3.0μm A method of manufacturing a semiconductor device according to item 1.