JP3381230B2 - Discrete system simulator and discrete system simulation method - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to system design,
The present invention relates to a discrete system simulator that simulates a system state during test adjustment and operation / maintenance.

[0002]

2. Description of the Related Art It is difficult to model production equipment because it is extremely diverse, but it is possible to perform a simple simulation of discovery of a bottleneck in distribution, lead time, inventory control, operation rate, etc. It is possible.

A discrete system simulator has heretofore been widely used as a device for finding such a bottleneck in physical distribution and performing a simple simulation of the lead time.

In this conventional discrete system simulator, as shown in FIG. 9, an event list storage memory 5 for storing an event list in which events scheduled to occur are arranged in order of occurrence time.
1, an event processing routine memory 52 that stores an event processing routine that describes a processing rule when an event occurs, a state variable storage memory 53 that stores a state of the event, that is, a variable indicating the completion or state of the operation,
The event processing unit 54 executes event processing.

Now, the processing operation of this conventional discrete system simulator will be described with reference to the flowchart of FIG.

In this conventional discrete system simulator, first, the event processing unit 54 clears the event list storage memory 51 in order to execute the event processing, and the state variables stored in the state variable storage memory 53. Is initialized (step 510).

After that, the event processing section 54 refers to the processing routine and the processing program (not shown) stored in the event processing routine memory to judge whether or not there is an event to be activated (step 520). As a result, if there is no event to be activated (step 520; N), the process is terminated, while if there is an event to be activated (step 520; Y), the latest event is activated. (Step 530).

Next, when the event processing section 54 receives a simulation correction signal described later, the event processing section 54 changes the simulation clock based on the simulation correction signal (step 540).

Here, the simulation correction signal is
This is a signal for changing the simulation clock to be output when the processing program or the operator judges the processing content of the activated event and, as a result, it is determined that the processing takes time.

The event processing unit 54 executes the event after changing the simulation clock if necessary (step 550).

That is, the event processing section 54 executes a predetermined processing based on the routine stored in the event processing routine memory 52, and thereafter changes the state variable corresponding to this event to the "processing completed" state. , And even form new events.

Subsequently, the event processing unit 54 registers the formed new event in the event storage memory 51 (step 560) in order to use it as information for processing the next event, and returns the process to step 520, The same processing as that performed is executed.

That is, in the conventional discrete system simulator, for example, a time point at which a workpiece to be machined undergoes a positional or morphological change is regarded as an event, and the events caused by a plurality of workpieces are discretely traced in the order of occurrence time. In addition, the simulation clock advances to that time when an event occurs.

At this time, the type and time of occurrence of an event that newly occurs are determined according to the rules of the event processing routine and registered in the event list.

[0015]

However, in such a conventional discrete system simulator, the simulation clock is not continuous and is different from the real time clock of the controller such as PLC. The system with the simulator installed has a plurality of clocks, making event management difficult and impractical.

For example, when designing a controller such as a PLC (programmable controller) and the actual PLC and the conventional discrete simulator are used together, a system having a plurality of clocks results.

In the PLC program design,
Controlling I / O ON / OFF at a desired timing occupies 90% or more of the entire processing, but adjusting the program with a discrete system simulator requires processing timing executed by the PLC due to clock differences. Unlike
Therefore, there is a problem that it is difficult to reproduce the operation status of the implementation and it is difficult to put it into practice.

In view of the above problems, it is an object of the present invention to provide a discrete system simulator that facilitates the management of events that occur even when used with a controller such as a PLC when the clocks are different. .

[0019]

In order to achieve the above object, the invention of claim 1 simulates a system state when designing, testing and adjusting, and operating and maintaining the system, and includes a programmable controller and the like. In the discrete system simulator that can be used together ,
The emulator is an event that stores a group of event processing routines.
Module processing routine memory and programmable controller
A programmable controller that stores the control program
Control program memory and event processing
The vent processing part and the state variable showing the operating state of the event
A state variable storage memory for storing the
When the event clock reaches the event start time,
The event processing unit is located above the event processing routine memory.
When the event processing is executed based on the processing routine
Both the processed events in the above state variable storage memory
Discrete system simulation that changes the state variable corresponding to
The simulation clock is output in synchronization with the real-time clock of the programmable controller.

According to a second aspect of the present invention, in a discrete system simulator for simulating the system when designing, test adjusting, and operating and maintaining the system, a clock detecting means for detecting a simulation clock, a programmable controller, etc. A real time clock detecting means for detecting a real time clock output by the clock detecting means, and a clock difference detecting means for detecting a difference between the real time clock detected by the real time clock detecting means and the simulation clock detected by the clock detecting means. , If the difference between the real-time clock detected by the clock difference detection means and the simulation clock is less than a certain time, start / stop
Form a signal and the falling of this start-stop signal
Child the output of the simulation clock in place
Simulate the output of the simulation clock with
It is characterized by comprising a clock adjusting means for aligning with the lock .

The invention of claim 3 is to design and test a system.
Simulates system status during adjustment and maintenance
And the programmable controller, etc.
In a discrete system simulator that can be used together,
When the oscillation clock reaches the event start time,
Event processing based on the processing routine for the event
The steps that perform
Change the state variables that
And the programmable controller
Simulates in sync with Laura's real-time clock
It is characterized by outputting an option clock.

According to a fourth aspect of the invention, the system design and test are performed.
Simulate the system for adjustment and maintenance
In the discrete system simulation method
A clock detection step to detect the clock and a program
Detects the real-time clock output by the Mable controller etc.
Real-time clock detection step and the real-time clock
The real-time clock detected by the clock detection means and the clock
The difference from the simulation clock detected by the detection means
The clock difference detection step to detect and this clock difference detection
The real-time clock detected by the output means and the simulator.
If the difference from the operation clock is less than a certain time,
Forming a start-stop signal, this start-stop
At the point where the signal falls, the simulation clock
Simulation clock by outputting the clock
Clock adjustment step to align the output of
Is provided.

According to the present invention, since the simulation clock is output while synchronizing with the real-time clock of the programmable controller or the like, the simulation clock interval and the clock time interval of the program controller or the like become equal.

In particular, when the simulation clock is longer than the real time clock, the simulation process is stopped.

Further, since the shared memory shares the I / O information of the external equipment constituting the system with the programmable controller etc., the simulator and the actual machine can be mixed for the test operation.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a discrete system simulator according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a discrete system simulator according to the present invention.

The discrete system simulator of this embodiment includes an event list storage memory 11 including a RAM for storing an event list, an event processing routine memory 12 including a ROM for storing a group of event processing routines, and an operation state of an event. , A state variable storage memory 13 such as a RAM storing state variables, a PLC control program memory 14 storing a PLC control program for controlling an actual system, an event processing section 15 for executing event processing, and an event processing section. A start / stop control unit 16 that forms and outputs a start / stop signal that controls the reading of the event routine 15 and a simulation clock detection unit 17 that detects a simulation clock indicating that an event has occurred from the event processing unit 15.
, A real-time clock detection unit 18 for detecting the real-time clock of the PLC 30, and a clock comparison calculation unit 19 described later.
And a shared memory 20 for storing I / O information.

The clock comparison / calculation unit 19 is configured to calculate the difference between the simulation clock from the simulation clock detection unit 17 and the real-time clock from the real-time clock detection unit 18.

The shared memory 20 stores the I / O information of the external devices that make up the system. When the discrete system simulator and the PLC 30 of this embodiment access at the same time, only one of them will be processed first. It is designed to accept.

As shown in FIG. 2, the shared memory 20 is composed of a range A in which only the PLC 30 can be updated and a range B in which only the simulator itself can be updated.

Since the shared memory 20 has such a structure, as shown in FIG.
The information a is written in the above range A, and new I / O after the simulator reads this I / O information "a"
The O information "b" is written in the range B.

Therefore, even if the simulator and the PLC 30 are used together on the system, the I from the PLC 30 is used.
/ O information is not changed by the simulator, and PL
Information that is unnecessary for the C30 but is necessary for the simulator itself (including I / O information) is not changed by the PLC 30, so that no abnormal processing of the system occurs.

Here, regarding the adjustment contents of the clock timing processed by the discrete system simulator of this embodiment,
This will be described with reference to the timing chart of FIG.

Here, the PLC 30 controls the external device in a predetermined one scan time, and this one scan time is set to one unit time as shown in FIG. 4 (a).

The discrete system simulator of this embodiment has a P
When there is no synchronization with the LC, the occurrence of the event has nothing to do with the real time. Therefore, as shown in FIG. 4B, the simulation clock is generated at non-intervals according to the content of the activated event. become.

Therefore, the start / stop control unit 15
Based on the comparison difference between the real-time clock and the simulation clock received from the clock comparison / inspection unit 18, FIG.
As shown in (c), when the real-time clock is advanced by one unit time (next real-time clock), the start / stop signal is raised, and at the place where this signal having a predetermined pulse width falls, FIG. ), The simulation clock is output.

That is, the simulation clock is output on the basis of the synchronization of the start / stop signal and corresponds to the real time clock of the PLC.

If the simulation clock is sent to the real-time clock for a certain amount or more, the consistency of the I / O information is lost, so the clock comparison / detection unit stops the simulation itself as an exception process and restarts again. The execution is restarted from the value.

Next, the operation of the discrete system simulator of this embodiment will be described with reference to the flowcharts of FIGS.

In the discrete system simulator of this embodiment, first, the event processing section 15 initializes the state variables stored in the state variable storage memory 13 in order to execute the event processing (step 110).

After that, the event processing section 15 judges whether or not the simulation clock has reached the event activation time (step 120).

When the event processing unit 15 determines that the simulation clock does not reach the event activation time (step 120; N), this processing is repeated until the event activation time is reached, while the simulation clock reaches the event activation time. If it is determined that the event has been reached (step 120; Y), the processing routine stored in the event processing routine memory 12 and the PLC control program stored in the PLC control program memory are referred to and the event to be activated is determined. It is determined whether or not there is (step 130).

As a result, if the event processing unit 15 determines that there is no event to be activated (step 130; N), the process is terminated, while if there is an event to be activated (step 130), the process is terminated. 130; Y), and activates the latest event (step 140).

After that, the discrete system simulator of this embodiment executes a start / stop signal forming process described later (step 150).

When the start / stop signal forming process is completed, the event processing unit 15 of the discrete system simulator of this embodiment determines whether or not the exception process, that is, the simulation needs to be stopped in the start / stop signal forming process ( Step 160).

When the event processing unit 15 determines that the exceptional processing is necessary (step; Y), it stops the simulation and ends the processing, while when it determines that the exceptional processing is not necessary ( Step 160; N), it is judged whether or not the start / stop signal has fallen (step 170).

When the event processing unit 15 determines that the start / stop signal has not fallen (step 170; N), the same processing is repeated until the start / stop signal falls, while the start / stop signal falls. If it is determined that there is (Step 17
0; Y), execute event logic (step 18)
0).

That is, the event processing unit 15 executes a predetermined process based on the routine stored in the event processing routine memory 12, and then stores the state corresponding to this event stored in the state variable storage memory 13. Change the variable to the "completed" state and create a new event.

Subsequently, the event processing unit 15 registers the new event that has been formed in the event storage memory 11 in order to use it as information for processing the next event (step 190), and returns the processing to step 130 to perform the above-mentioned processing. The same processing as that performed is executed.

Here, the process of forming the start / stop signal in step 150 will be described.

The signal notifying that the simulation clock has been output is obtained from the event processing section 15, and the simulation clock detection section 17 detects that the simulation clock has been generated (step 151). It outputs to 19.

Next, the signal notifying that the real-time clock has been output is obtained from the PLC 30, and the real-time clock detecting section 18 detects that the real-time clock has been generated (step 152), and a clock comparison to that effect is made. Detector 1
Output to 9.

The clock comparison / detection unit 19 compares the simulation clock time detected by the simulation clock detection unit 17 with the real-time clock time detected by the real-time clock detection unit 18, and detects a comparison difference (step 153). .

The clock comparison / detection unit 19 judges whether or not the simulation clock is delayed from the real-time clock by a fixed time or more (step 154). As a result, if the simulation clock is delayed from the real-time clock by a fixed time or more. (Step 154; Y), the exception processing, that is, the simulation is stopped (step 15
6), while ending the formation process of the start stop signal,
If it is determined that the simulation clock has not delayed the real-time clock by more than a fixed time (step 15).
4; N), and it is further determined whether or not one unit time of the real time clock has elapsed (step 155).

When the clock comparison / detection unit 19 determines that one unit time of the real time clock has not elapsed (step 155; N), it waits until one unit time elapses, while one unit time of the real time clock When it is determined that the time has elapsed (step 155; Y), the fact is output to the start / stop control unit 16.

The start / stop control unit 16 forms a start / stop signal and outputs it to the event processing unit 15 (step 157), and ends the start / stop signal forming process.

Next, the usage of the discrete system simulator of this embodiment will be described.

<First Usage Mode> The discrete system simulator of this usage mode is a usage mode when used as a controller when designing a PLC program.

Usually, the designed PLC program is converted into the information format and then downloaded to the actual machine. In this case, the program is designed when there is no actual machine.

In the discrete system simulator of this embodiment, P
By controlling the I / O of the LC in sequence, the whole is controlled.

Incidentally, FIG. 7 shows the configuration of the control system to be designed, and FIG. 8 shows the I / O information table defined on the simulator. This I / O information table has I / O information of the actual machine.

Here, the robot (RO) and linear actuator (LA) of each equipment are defined as state variables as simulator models on the simulator. These operations are described as rules or program logic in the event processing routine as a control target operation description.

As the shared memory 20, a UNIX file having exclusive control is used. In this case, I / O
1-bit information is stored in one UNIX file.

The event processing routine is designed to access a UNIX file containing I / O information. It is assumed that the access speed is sufficient compared with the internal clock of the PLC in real time.

The PLC control program for accessing these is also described as an event processing routine.

It should be noted that by preparing and compiling a compiler capable of converting the format of the PLC control program into a format that can be executed by the actual PLC, a PLC control program of a format that can be executed on the PLC can be obtained. .

It is also possible to create a PLC control program of a type that can be directly executed on the actual PLC side without using the built-in PLC control program, by the same procedure.
In this case, the shared memory is constituted by a memory having an exclusive control mechanism such as a 2-port RAM chip and a high access speed.

By synchronizing the simulation clock and the real-time clock by the clock comparison and detection, it becomes possible to operate the controlled object on the simulator by the program on the PLC.

With the above procedure, a PLC control program that can be executed by the PLC can be designed on the simulator without the actual machine.

<Second Usage Mode> The discrete system simulator of this usage mode is a usage mode in the case of improving the efficiency of the adjustment test by the mixed operation.

First, the object to be controlled is modeled on the discrete system simulator. This is controlled from the actual PLC,
Perform an adjustment test. This is effective when some of the actual equipment are not available during the adjustment test.

In the discrete system simulator of this embodiment, P
The overall control is performed by controlling the I / O of the LC in sequence.

The robots, linear actuators, etc. of each equipment are defined as state variables in the simulator as simulator models, and these operations are described as rules or program logic in the event processing routine as controlled object operation description.

The shared memory is composed of a memory having an exclusive control mechanism such as a 2-port RAM chip. This is a memory that cannot be written to or read from the simulator and the actual machine at the same time.

In this case, an adjustment test of the PLC control program on the PLC side is required. In PLC,
The robot is connected, but no other device is connected. The other device synchronizes the model on the simulator with the simulation clock to the real-time clock by the function of the clock comparison and detection unit, and uses the shared memory between the virtual device of the simulator model and the actual device to perform accurate I / O.
/ O information can be delivered and received.

The workpiece is carried in, the linear actuator is activated, the simulator scans until the operation is completed, the actual machine operates from the robot startup to the operation completion, and the processing machine or the simulator scans to determine whether the program is normal or not. , You can check while watching the operation.

Since the simulator is synchronized in real time, it is possible to measure the correct timing.

Since the change of the state variable can be displayed as an output of the simulator by an animation display, the adjustment test can be carried out as if the operator were looking at the actual machine, and a sufficient effect of the test can be obtained. It is what makes up. By such mixed operation, the efficiency of the adjustment test can be improved.

[0080]

According to the present invention, the simulation clock is output in synchronization with the real-time clock of the programmable controller, so that the simulation clock time interval is equal to the clock time interval of the program controller etc. It becomes flexible. Therefore, the following effects can be obtained.

It is possible to design a control program that operates like an actual machine using only a discrete system simulator. The controlled object model on the simulator can be used for the test for the actual machine, and not only the accuracy is better than before but also the efficiency can be adjusted efficiently. Since the simulator can be used as a substitute for a part of the actual machine to adjust the program, an effect that a partial adjustment test can be performed even if the actual machine is not available is obtained. Changing the format of the controller program on the simulator can also operate on a controller such as a PLC, so that the program can be downloaded easily.
The effect is that design and adjustment can be performed efficiently. The event from the actual machine can be easily captured in the simulator, and the effect that the simulator can be easily used for changing the simulator model and operation maintenance can be obtained.

According to the third aspect of the present invention, when the simulation clock is longer than the real-time clock, the simulation process is stopped, so that it is possible to quickly eliminate the slow event process that is not useful for the process. it can.

According to the invention described in claim 4, since the shared memory shares the I / O information of the external equipment constituting the system with the programmable controller or the like, the simulator and the actual machine can be mixed for the test operation. The effect is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a discrete system simulator according to the present invention.

FIG. 2 is a block diagram showing a configuration of a shared memory in FIG.

FIG. 3 is an explanatory diagram of a writing process of I / O information to a shared memory.

FIG. 4 is a timing chart explaining the output timing of the simulation clock of the discrete system simulator according to the present embodiment.

FIG. 5 is a flowchart showing the operation of the discrete system simulator according to the present embodiment.

FIG. 6 is a flowchart showing a start / stop signal forming process in FIG.

FIG. 7 is an explanatory diagram of a usage pattern of the discrete system simulator according to this embodiment.

FIG. 8 is an explanatory diagram of an I / O information table defined on a discrete system simulator according to this usage pattern.

FIG. 9 is a block diagram showing the configuration of a conventional discrete system simulator.

FIG. 10 is a flowchart showing the operation of a conventional discrete system simulator.

[Explanation of symbols]

11 Event list storage memory 12 Event processing routine storage memory 13 State variable storage memory 14 PLC control program memory 15 Event processing section 16 star and stop control 17 Simulation clock detector 18 Real-time clock detector 19 Clock comparison section 20 shared memory 30 Programmable controller (PLC)

─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-63-291156 (JP, A) JP-A-61-289403 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G05B 19/04-19/05 G05B 23/00-23/02

Claims (4)

(57) [Claims] 1. System design, test adjustment, operation and maintenance
It simulates the system state when
Used in combination with a programmable controller, etc.Can
RuIn a discrete system simulator,The discrete simulator is Event processing routine that stores a group of event processing routines
Memory, Stores the programmable controller control program
A programmable controller control program memory, An event processing unit that executes event processing, State variable that stores the state variable that indicates the operating state of the event
Storage memory, Have Simulation clock reaches event start time
And the event processing unit uses the event processing routine
Event processing based on the above processing routine in memory
And the processing in the above state variable storage memory
Discrete to change the state variable corresponding to the triggered event
System simulator, Same as the real-time clock of the programmable controller
The simulation clock should be output in a timely manner.
A discrete system simulator characterized by. 2. A system for simulating a system in the design, test adjustment, and operation and maintenance of a system, in a discrete system simulator, a clock detection unit for detecting a simulation clock, and a real time clock for detecting a real-time clock output by a programmable controller or the like. A time clock detecting means, a clock difference detecting means for detecting a difference between the real time clock detected by the real time clock detecting means and a simulation clock detected by the clock detecting means, and a clock difference detecting means for detecting the difference. The difference between the real-time clock and the simulation clock is less than a certain time.
If it was below, it forms a start-stop signal and this
The simulation clock is output at the point where the start / stop signal falls.
Discrete system simulator, characterized by comprising: a click <br/> locking adjusting means for aligning the output of the Activation clock and real-time clock, a. 3. System design, test adjustment, operation and maintenance
It simulates the system state when
Can be used in combination with a programmable controller, etc.
Simulation clock reaches event start time in discrete simulator
And the event processing based on the processing routine for the event.
The steps to execute the logic and the steps to change the state variables corresponding to the processed event.
And a step of forming a new event, which is the same as the real-time clock of the programmable controller.
The simulation clock should be output in a timely manner.
And a discrete system simulating method. 4. System design, test adjustment, operation and maintenance
The discrete system simulation that simulates the system
Method, the clock detection step for detecting the simulation clock.
And the real-time clock output by the programmable controller, etc.
Clock detecting step for detecting a clock and the real time clock detected by the real time clock detecting means.
And the simulation detected by the clock detection means
A clock difference detecting step for detecting a difference from the clock, and the real time clock detected by the clock difference detecting means.
The difference between the clock and the simulation clock is within a certain time.
If it was below, it forms a start-stop signal and this
Simulate where the start / stop signal falls.
Simulation by outputting the synchronization clock.
The alignment clock output with the real-time clock.
Discrete characterized by comprising a lock adjustment step
System simulation method.