JP3380097B2 - Semiconductor device substrate, method of manufacturing semiconductor device substrate, method of manufacturing semiconductor device using semiconductor device substrate, and semiconductor device - Google Patents

Semiconductor device substrate, method of manufacturing semiconductor device substrate, method of manufacturing semiconductor device using semiconductor device substrate, and semiconductor device

Info

Publication number
JP3380097B2
JP3380097B2 JP28532795A JP28532795A JP3380097B2 JP 3380097 B2 JP3380097 B2 JP 3380097B2 JP 28532795 A JP28532795 A JP 28532795A JP 28532795 A JP28532795 A JP 28532795A JP 3380097 B2 JP3380097 B2 JP 3380097B2
Authority
JP
Japan
Prior art keywords
semiconductor device
circuit board
substrate
resin
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP28532795A
Other languages
Japanese (ja)
Other versions
JPH09129781A (en
Inventor
浩一郎 林
弘志 宮川
之治 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP28532795A priority Critical patent/JP3380097B2/en
Publication of JPH09129781A publication Critical patent/JPH09129781A/en
Application granted granted Critical
Publication of JP3380097B2 publication Critical patent/JP3380097B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Insulated Metal Substrates For Printed Circuits (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置用基板、
半導体装置用基板の製造方法半導体装置用基板を用い
た半導体装置の製造方法及び半導体装置に関し、とくに
内部に金属板を有する半導体装置用基板、半導体装置用
基板の製造方法半導体装置用基板を用いた半導体装置
の製造方法及び半導体装置に関する。
TECHNICAL FIELD The present invention relates to a semiconductor device substrate,
Method of manufacturing a substrate for a semiconductor device, a method of manufacturing a semiconductor device and the semiconductor device using a substrate for a semiconductor device, particularly a semiconductor device substrate having an internal metal plate, a method of manufacturing a substrate for a semiconductor device, a substrate for a semiconductor device The present invention relates to a semiconductor device manufacturing method and a semiconductor device used.

【0002】[0002]

【従来の技術】プリント基板は抵抗あるいはコンデンサ
といった回路部品を搭載する基板として一般に用いられ
てきたが、最近、PPGA(Plastic Pin Grid Array)
あるいはBGA(Ball Grid Array)といった製品のよう
に、プリント基板を半導体装置の回路基板に用いた製品
が製造されるようになってきた。これらの半導体装置は
半導体装置用基板上に半導体素子を搭載し、片面樹脂封
止あるいはポッティング等により半導体素子を封止し、
リードピンあるいははんだボール等の外部接続端子を取
り付けて製品としたものである。
2. Description of the Related Art A printed circuit board has been generally used as a substrate for mounting a circuit component such as a resistor or a capacitor, but recently, a PPGA (Plastic Pin Grid Array) has been used.
Alternatively, products such as BGA (Ball Grid Array) products in which a printed circuit board is used as a circuit board of a semiconductor device have been manufactured. In these semiconductor devices, a semiconductor element is mounted on a semiconductor device substrate, and the semiconductor element is sealed by one-side resin sealing or potting,
This is a product with external connection terminals such as lead pins or solder balls attached.

【0003】図5はこのような半導体装置の製造に使用
する半導体装置用基板の従来例を示す。この例は半導体
装置の個々の基板となる回路基板10、10、10をフ
レーム11で一体に支持して全体形状を短冊状に形成し
たものである。半導体装置用基板はこのように回路基板
を複数個連設して短冊状に形成したものの他、一つの回
路基板ごと1枚の半導体装置用基板としたものや、回路
基板を縦横に多数個連設した大判の基板として使用する
場合もある。
FIG. 5 shows a conventional example of a semiconductor device substrate used for manufacturing such a semiconductor device. In this example, circuit boards 10, 10 and 10 which are individual boards of a semiconductor device are integrally supported by a frame 11, and the whole shape is formed in a strip shape. As the semiconductor device substrate, a plurality of circuit boards are continuously formed in a strip shape as described above, one semiconductor device substrate is provided for each circuit board, and a large number of circuit boards are connected vertically and horizontally. It may be used as a large-sized board that has been installed.

【0004】ところで、半導体装置用基板はセラミック
パッケージ等と比較すると基板の反りやうねりが生じや
すく、また放熱性が劣ることから、とくに発熱量の大き
な半導体素子を搭載するような製品では、基板の内部に
コアメタル(銅等の金属板)を入れた半導体装置用基板
が使用される。このようなコアメタルを入れた半導体装
置用基板は基板の反りやうねりを防止でき、熱放散性を
向上させることができるという利点がある。
By the way, a semiconductor device substrate is more liable to warp or waviness than a ceramic package or the like, and its heat dissipation is inferior. A semiconductor device substrate having a core metal (copper or other metal plate) inside is used. The semiconductor device substrate containing such a core metal has an advantage that the substrate can be prevented from warping or waviness and the heat dissipation property can be improved.

【0005】図5に示す半導体装置用基板もコアメタル
を有するものであり、平面配置で半導体素子を搭載する
部位に合わせてコアメタル12を配置したものである。
図6はこの半導体装置用基板の断面図を示す。半導体装
置用基板はコアメタル12を内層に配置しフィルム状に
形成されたプリプレグ(接着性のプラスチックシート)
14a、14b、14cを積層し、加熱および加圧する
ことによって板体状に形成される。16は配線パターン
等の導体層を形成する銅箔、18はスルーホール、20
はスリット、22はソルダーレジストである。
The semiconductor device substrate shown in FIG. 5 also has a core metal, and the core metal 12 is arranged in a plane arrangement in accordance with the portion on which the semiconductor element is mounted.
FIG. 6 shows a cross-sectional view of this semiconductor device substrate. The semiconductor device substrate is a film-shaped prepreg (adhesive plastic sheet) in which the core metal 12 is arranged in the inner layer.
14a, 14b, 14c are stacked, and formed into a plate by heating and pressing. Reference numeral 16 is a copper foil forming a conductor layer such as a wiring pattern, 18 is a through hole, 20
Is a slit, and 22 is a solder resist.

【0006】[0006]

【発明が解決しようとする課題】上記の半導体装置用基
板を用いて半導体装置を製造する場合は、個々の回路基
板10上に半導体素子を搭載し、半導体装置用基板の半
導体素子搭載面を片面樹脂封止した後、個々の回路基板
10をフレーム11から分離して半導体装置とする。図
5、6で回路基板10をフレーム11から分離する位置
をA線で示す。この分離位置は最終的に半導体装置の基
板の端面となるもので、実際には切断刃で回路基板10
を切り落として切断する。
In the case of manufacturing a semiconductor device using the above semiconductor device substrate, semiconductor elements are mounted on each circuit board 10, and the semiconductor element mounting surface of the semiconductor device substrate is provided on one side. After resin sealing, the individual circuit boards 10 are separated from the frame 11 to form semiconductor devices. The position where the circuit board 10 is separated from the frame 11 is shown by line A in FIGS. This separation position finally becomes the end face of the substrate of the semiconductor device.
Cut off and cut.

【0007】ところで、回路基板10では搭載した半導
体素子の周囲に外部接続端子と接続するための配線パタ
ーンを設け、基板の外周縁部側にスルーホール18を配
置する。したがって、コアメタル12を配置する場合
は、これらのスルーホール18とコアメタル12が干渉
しないようにコアメタル12の外形寸法を設定する。ス
ルーホール18の配置位置にまでコアメタル12を広げ
たとするとスルーホール18を貫通させる孔を加工しな
ければならないが、スルーホール18の配置ピッチはき
わめて微小であるためこのような貫通孔を加工すること
は困難であるからである。このため、スルーホール18
を配置する部位ではまとめてコアメタル12を逃がすよ
うにしている。
By the way, in the circuit board 10, a wiring pattern for connecting to external connection terminals is provided around the mounted semiconductor element, and the through holes 18 are arranged on the outer peripheral edge side of the board. Therefore, when the core metal 12 is arranged, the outer dimensions of the core metal 12 are set so that the through holes 18 and the core metal 12 do not interfere with each other. If the core metal 12 is expanded to the position where the through holes 18 are arranged, holes for penetrating the through holes 18 must be processed. However, since the arrangement pitch of the through holes 18 is extremely small, it is necessary to process such through holes. Is difficult. Therefore, the through hole 18
The core metal 12 is made to escape collectively at the portion where the is arranged.

【0008】したがって、個々の回路基板10を切断し
て個片にする場合は、コアメタル12が存在していない
樹脂部分を切断することになり、この切断の際に基板の
端面にクラックが入ってしまったり、端面から樹脂くず
が出たりするといった問題が生じ、また、半導体装置と
しては基板の加工端面の密閉性が不十分で基板の端面か
ら水分が侵入するといった問題が生じる。これは、プリ
プレグ14a、14b、14cを固めて半導体装置用基
板としているため、加工端面で基板が構造的にもろいこ
とが原因している。
Therefore, when the individual circuit boards 10 are cut into individual pieces, the resin portion where the core metal 12 is not present is cut, and at the time of this cutting, a crack is formed on the end surface of the board. There is a problem that the end face of the semiconductor device may be crushed or resin scraps may come out from the end face. Further, as a semiconductor device, there is a problem that the processed end face of the substrate is insufficiently sealed and moisture enters from the end face of the substrate. This is because the prepregs 14a, 14b, and 14c are solidified to form a semiconductor device substrate, and therefore the substrate is structurally fragile at the processed end surface.

【0009】また、従来の回路基板10では上述した理
由から基板内に配置するコアメタル12の大きさも基板
に搭載する半導体素子と略同サイズ程度であり、熱放散
性の向上が不十分であったり、回路基板10全体の変形
を好適に抑えることができないといった問題点もあっ
た。本発明はこれらの問題点を解消すべくなされたもの
であり、基板の吸湿を抑える等の機能を有することによ
り信頼性が高く、外観的にも優れた回路基板を提供する
ことができる、半導体装置用基板、半導体装置用基板の
製造方法、半導体装置用基板を用いた半導体装置の製造
方法及び半導体装置を提供することを目的としている。
Further, in the conventional circuit board 10, the size of the core metal 12 arranged in the board is about the same as that of the semiconductor element mounted on the board for the above-mentioned reason, and the improvement of heat dissipation is insufficient. There is also a problem that the deformation of the entire circuit board 10 cannot be suppressed appropriately. The present invention has been made to solve these problems, and provides a circuit board having high reliability and excellent appearance by having a function of suppressing moisture absorption of the board.
Of semiconductor device substrate, semiconductor device substrate
Manufacturing method, manufacturing of semiconductor device using semiconductor device substrate
An object is to provide a method and a semiconductor device.

【0010】[0010]

【課題を解決するための手段】本発明は上記目的を達成
するため次の構成を備える。すなわち、樹脂板からなる
単数もしくは複数の回路基板が、孔の内周縁位置を回路
基板の外形に一致させた所定幅のスリットを隔てて樹脂
板からなるフレームに並設されており、該回路基板の四
隅に設けた連結部により前記フレームに支持された半導
体装置用基板において、前記回路基板と前記連結部と前
記フレームとを含む樹脂板の内部全体に、連続的に金属
板が配置され、前記回路基板の四隅部分を除く外周縁部
については、前記金属板が回路基板の端面よりも内側へ
後退して樹脂のみからなるスルーホール形成範囲に形成
され、該スルーホール形成範囲にスルーホールが設けら
れたことを特徴とする。また、前記半導体装置用基板が
複数の回路基板がフレームに支持されて短冊状に形成さ
れたことを特徴とする。また、半導体装置用基板におい
て、樹脂板からなる回路基板の内部全体に、連続的に金
属板が配置され、前記回路基板の四隅部分を除く外周縁
部については、前記金属板が回路基板の端面よりも内側
へ後退して樹脂のみからなるスルーホール形成範囲に形
成され、該スルーホール形成範囲にスルーホールが設け
られたことを特徴とする。また、前記回路基板の半導体
素子の搭載面にサーマルビアが設けられたことを特徴と
する。また、樹脂板からなる単数もしくは複数の回路基
板が、所定幅のスリットを隔てて樹脂板からなるフレー
ムに並設されており、該回路基板の四隅に設けた連結部
により前記フレームに支持された半導体装置用基板の製
造方法において、前記回路基板と前記連結部と前記フレ
ームとを含む樹脂板の内部全体に、連続的に金属板が配
置されるとともに、前記回路基板の四隅部分を除く外周
縁部については、前記金属板が回路基板の端面よりも
側へ後退して樹脂のみからなるスルーホール形成範囲に
形成された樹脂板を形成し、該樹脂板の表面に配線パタ
ーンを形成し、前記スルーホール形成範囲に複数のスル
ーホールを形成し、次いで、前記樹脂板にルータ加工を
施して、孔の内周縁位置を回路基板の外形に一致させた
所定幅のスリットを形成することを特徴とする。また、
半導体装置の製造方法において、前記半導体装置用基板
の回路基板に半導体素子を搭載し、半導体装置用基板の
半導体素子搭載面を片面樹脂封止した後、前記回路基板
と前記フレームとの連結部を切断して半導体装置を製造
することを特徴とする。また、前記半導体装置用基板の
回路基板に半導体素子を搭載し、半導体装置用基板の半
導体素子搭載面を片面樹脂封止して半導体装置を製造す
ることを特徴とする。また、樹脂からなる回路基板の半
導体素子の搭載面に半導体素子が搭載され、半導体素子
と外部接続端子とが回路基板に形成されたスルーホール
を介して電気的に接続された半導体装置において、前記
回路基板と前記連結部と前記フレームとを含む樹脂板の
内部全体に、連続的に金属板が配置され、前記回路基板
の四隅部分を除く外周縁部については、前記金属板が回
路基板の端面よりも内側へ後退して樹脂のみからなる
ルーホール形成範囲に形成され、該スルーホール形成範
囲にスルーホールが設けられたことを特徴とする。ま
た、前記回路基板の半導体素子の搭載面にサーマルビア
が設けられ、サーマルビアの端部に外部接続端子が設け
られたことを特徴とする。
The present invention has the following constitution in order to achieve the above object. That is, one or a plurality of circuit boards made of a resin plate are juxtaposed to a frame made of a resin plate with a slit having a predetermined width in which the inner peripheral edge position of the hole matches the outer shape of the circuit board. In the semiconductor device substrate supported by the frame by the connecting portions provided at the four corners of the resin plate, the metal plate is continuously arranged in the entire resin plate including the circuit board, the connecting portion, and the frame, In the outer peripheral edge portion except the four corners of the circuit board, the metal plate is formed in the through hole forming range made of only resin by retracting inward from the end surface of the circuit board, and the through hole is provided in the through hole forming range. It is characterized by being done. In addition, the semiconductor device substrate is formed in a strip shape in which a plurality of circuit boards are supported by a frame. Further, in the semiconductor device substrate, a metal plate is continuously arranged in the entire circuit board made of a resin plate, and the metal plate is an end surface of the circuit board except for the four corners of the circuit board. retracts inward than formed in the through hole forming range consisting only of resin, wherein the through hole is provided in the through-hole forming area. Also, a thermal via is provided on the surface of the circuit board on which the semiconductor element is mounted. Further, one or a plurality of circuit boards made of a resin plate are juxtaposed to a frame made of a resin plate with a slit having a predetermined width, and are supported by the frame by connecting portions provided at four corners of the circuit board. In the method for manufacturing a substrate for a semiconductor device, a metal plate is continuously arranged over the entire resin plate including the circuit board, the connecting portion, and the frame, and an outer peripheral edge of the circuit board excluding four corners. As for the parts, the metal plate is retracted inward from the end face of the circuit board to form a resin plate formed in a through hole forming area made of only resin, and a wiring pattern is formed on the surface of the resin plate. A plurality of through holes are formed in the through hole forming range, and then the resin plate is subjected to router processing to form a slit having a predetermined width in which the inner peripheral edge position of the hole matches the outer shape of the circuit board. Characterized in that it formed. Also,
In a method of manufacturing a semiconductor device, a semiconductor element is mounted on a circuit board of the semiconductor device substrate, and a semiconductor element mounting surface of the semiconductor device substrate is resin-sealed on one side, and then a connecting portion between the circuit board and the frame is formed. It is characterized in that the semiconductor device is manufactured by cutting. Further, a semiconductor device is manufactured by mounting a semiconductor element on a circuit board of the semiconductor device substrate, and resin-sealing a semiconductor element mounting surface of the semiconductor device substrate on one side. Further, in a semiconductor device in which a semiconductor element is mounted on a semiconductor element mounting surface of a circuit board made of resin, and the semiconductor element and an external connection terminal are electrically connected to each other through a through hole formed in the circuit board, A metal plate is continuously arranged in the entire resin plate including the circuit board, the connecting portion, and the frame, and the metal plate is an end surface of the circuit board in the outer peripheral edge portion except the four corners of the circuit board. retracts inward than formed on the scan <br/> Ruhoru forming range consisting only of resin, wherein the through hole is provided in the through-hole forming area. Further, a thermal via is provided on a mounting surface of the semiconductor element of the circuit board, and an external connection terminal is provided at an end of the thermal via.

【0011】[0011]

【発明の実施の形態】以下、本発明の好適な実施形態に
つき添付図面に基づいて説明する。図1は回路基板10
をフレーム11に連設して全体形状を短冊状に形成した
半導体装置用基板の一実施形態の全体構成を示す説明図
である。なお、本明細書では一つ一つの半導体装置で使
用する基板を回路基板10といい、図1のようにフレー
ム11で回路基板10を支持した全体の基板を半導体装
置用基板というものとする。図1の実施形態ではフレー
ム11に3つの回路基板10が連設されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a circuit board 10.
FIG. 3 is an explanatory diagram showing an overall configuration of an embodiment of a semiconductor device substrate in which the substrate is continuously connected to a frame 11 to form a strip shape. In this specification, a substrate used in each semiconductor device is referred to as a circuit substrate 10, and the entire substrate supporting the circuit substrate 10 with a frame 11 as shown in FIG. 1 is referred to as a semiconductor device substrate. In the embodiment shown in FIG. 1, three circuit boards 10 are continuously arranged on the frame 11.

【0012】図1で示す短冊状の半導体装置用基板は各
々の回路基板10の周囲に形成するスリット20の形状
および寸法を半導体装置の最終製品での基板の外形寸法
に一致させてあらかじめ孔空け形成し、回路基板10の
四隅の連結部10aでフレーム11に連結したことを特
徴とする。スリット20は最終製品の基板の外形寸法に
孔の内周縁位置を合わせるから、図5に示した従来例の
半導体装置用基板にくらべて幅広の長孔形状となってい
る。
The strip-shaped semiconductor device substrate shown in FIG. 1 is preliminarily perforated by matching the shape and size of the slit 20 formed around each circuit board 10 with the external dimensions of the substrate in the final product of the semiconductor device. It is characterized in that it is formed and connected to the frame 11 by the connecting portions 10a at the four corners of the circuit board 10. Since the slit 20 has the inner peripheral edge position of the hole aligned with the outer dimension of the substrate of the final product, it has a wider elongated hole shape as compared with the conventional semiconductor device substrate shown in FIG.

【0013】また、本実施形態では基板の内層に設ける
コアメタル(金属板)12を図1に示すように、回路基
板10の外周縁部のスルーホール18を形成する範囲を
除いて回路基板10の四隅でフレーム11まで連続的に
設けること、およびフレーム11部分にも設けることを
特徴とする。図2に一つの回路基板10についてのコア
メタル12の配置を示すが、このように回路基板10の
コーナー部については少なくとも連結部10aとの接続
部分にはコアメタル12を残すようにする。
Further, in this embodiment, as shown in FIG. 1, the core metal (metal plate) 12 provided in the inner layer of the board is excluded from the circuit board 10 except the area where the through hole 18 is formed in the outer peripheral edge portion. It is characterized in that it is continuously provided up to the frame 11 at the four corners, and is also provided in the frame 11 portion. FIG. 2 shows the arrangement of the core metal 12 for one circuit board 10. In this way, at the corners of the circuit board 10, the core metal 12 is left at least at the connecting portions with the connecting portions 10a.

【0014】図2に示すように、回路基板10の各辺の
外周縁部にはスルーホール18が配置されるから、この
範囲でコアメタル12は一定幅で内側に後退している。
このコアメタル12が後退している範囲はスルーホール
18が形成されている部位であり、回路基板10の内層
は樹脂14のみによって形成されている。これに対し、
回路基板10の四隅部分にはコアメタル12が端面まで
連続している。
As shown in FIG. 2, since the through holes 18 are arranged at the outer peripheral edge portions of the respective sides of the circuit board 10, the core metal 12 recedes inward with a constant width in this range.
The area where the core metal 12 is retracted is a portion where the through hole 18 is formed, and the inner layer of the circuit board 10 is formed only by the resin 14. In contrast,
The core metal 12 continues to the end faces at the four corners of the circuit board 10.

【0015】スリット20は内周縁を製品の基板寸法に
合わせて形成するため実施形態では半導体装置用基板に
加工用の小孔をあけた後、ルータ加工等の切削加工によ
って孔を広げるようにしてスリット20の内周縁を加工
する。このルータによる加工では従来のように後工程で
回路基板10を部分的に切断して基板寸法を決める方法
にくらべて基板の端面が樹脂であっても損傷を与えるこ
とが少なく、端面にクラックを生じさせたり、樹脂くず
を生じさせることなく加工できるという利点がある。
Since the slit 20 has its inner peripheral edge formed in accordance with the size of the substrate of the product, in the embodiment, a small hole for processing is made in the substrate for the semiconductor device and then the hole is expanded by cutting such as router processing. The inner peripheral edge of the slit 20 is processed. Compared to the conventional method of partially cutting the circuit board 10 in the subsequent step to determine the board size, the processing by this router causes less damage even if the end surface of the board is resin, and cracks on the end surface. There is an advantage that processing can be performed without causing or causing resin scrap.

【0016】実際にルータ加工した端面と切断によって
形成した端面とを観察すると、ルータ加工による場合
は、切断した場合に比較して端面がはるかにスムーズに
仕上がり、外観的に優れた基板が得られるとともに、端
面から樹脂くずなどが発生しにくい構造になる。また、
ルータ加工によることから樹脂とルータとの摩擦によっ
て樹脂が若干融着し端面での密閉性が向上して、基板の
端面から水分が侵入するといったことを防止することが
可能になる。なお、ルータ加工は半導体装置用基板に配
線パターンを形成した後に行ってもよいし、配線パター
ンを形成する前に行ってもよい。
When observing the end surface actually processed by router and the end surface formed by cutting, the end surface is much smoother than that in the case of cutting by router processing, and a substrate excellent in appearance is obtained. At the same time, the structure makes it difficult for resin scraps to be generated from the end faces. Also,
Since the router is processed, it is possible to prevent the resin from being slightly fused due to the friction between the resin and the router to improve the airtightness at the end face, and prevent moisture from entering from the end face of the substrate. The router processing may be performed after the wiring pattern is formed on the semiconductor device substrate or before the wiring pattern is formed.

【0017】また、本実施形態ではルータ加工によって
回路基板10の外周縁のうちスルーホール18を配置す
るための樹脂14が露出する部分についてはあらかじめ
孔空けしてあるから、後工程では連結部10aのみを切
断すればよい。連結部10aの切断は容易であると同時
に、連結部10aについてはコアメタル12を残すよう
にしているから、連結部10aを切断しても樹脂部分を
切断する場合とは異なり、端面にクラックが入ったり、
端面が荒れたりすることなく確実に切断することが可能
になる。これによって、回路基板10の信頼性を向上さ
せることができ、合わせて半導体装置全体の信頼性を向
上させることができる。
Further, in this embodiment, since the portion of the outer peripheral edge of the circuit board 10 where the resin 14 for arranging the through hole 18 is exposed is preliminarily punched by the router processing, the connecting portion 10a is formed in a later step. Only cut off. The connecting portion 10a is easily cut, and at the same time, the core metal 12 is left in the connecting portion 10a. Therefore, even if the connecting portion 10a is cut, unlike the case where the resin portion is cut, the end face is cracked. Or
It is possible to reliably cut without causing the end face to be rough. As a result, the reliability of the circuit board 10 can be improved and, in addition, the reliability of the entire semiconductor device can be improved.

【0018】図3はルータ加工によってあらかじめスリ
ット20を形成した半導体装置用基板の断面図を示す。
図でB線は最終的に製品となる基板の端面位置を示す。
スリット20はルータ加工によって孔内周縁をこの端面
位置(B線)に合わせて孔あけ加工を施すものである。
コアメタル12はスルーホール18を形成する部位と干
渉しない範囲で最も大きな寸法に設定する。また、フレ
ーム11部分までコアメタル12を広げるようにする。
FIG. 3 is a sectional view of a semiconductor device substrate in which slits 20 are formed in advance by router processing.
In the figure, the line B shows the position of the end surface of the substrate which is the final product.
The slit 20 is formed by router processing so that the inner peripheral edge of the hole is aligned with the end surface position (line B).
The core metal 12 is set to have the largest dimension within the range where it does not interfere with the portion where the through hole 18 is formed. Further, the core metal 12 is extended to the frame 11 portion.

【0019】コアメタル12を内層に配置した半導体装
置用基板を作製する場合は図3の例で説明すると、下層
のプリプレグ14aの上にコアメタル12を挿入するた
めの孔をあけた中間層のプリプレグ14bを配置し、プ
リプレグ14bにあけた孔にコアメタル12を落とし込
むようにしてセットし、さらに上層のプリプレグ14c
をのせて全体を加圧および加熱することにより、コアメ
タル12がはいった半導体装置用基板が得られる。この
半導体装置用基板の表面に銅箔の接着や銅スパッタリン
グ等で導体層を設け、導体層をエッチングして配線パタ
ーンを形成し、ドリル加工等で基板に貫通孔をあけて裏
面の配線パターンと接続したり、外部接続端子を接続す
るためのスルーホールを形成することができる。これら
の加工方法は従来の半導体装置用基板の製法と同様であ
る。なお、半導体装置用基板の樹脂層はガラスエポキシ
基板やプリプレグの積層(貼層)でもよいし、ポリイミ
ド、エポキシ等の樹脂を塗布して形成してもよい。
In the case of manufacturing a semiconductor device substrate in which the core metal 12 is arranged in the inner layer, an example of FIG. 3 will be described. An intermediate layer prepreg 14b in which a hole for inserting the core metal 12 is formed on the lower layer prepreg 14a. And set it so that the core metal 12 is dropped into the hole formed in the prepreg 14b.
A substrate for a semiconductor device having the core metal 12 is obtained by applying pressure and heating the whole on top. A conductor layer is provided on the surface of this semiconductor device substrate by adhesion of copper foil, copper sputtering, etc., the conductor layer is etched to form a wiring pattern, and a through hole is formed in the substrate by drilling or the like to form a wiring pattern on the back surface. Through holes can be formed for connection or for connecting external connection terminals. These processing methods are the same as the conventional method for manufacturing a semiconductor device substrate. The resin layer of the semiconductor device substrate may be a glass epoxy substrate or a prepreg laminate (paste layer), or may be formed by applying a resin such as polyimide or epoxy.

【0020】上記の半導体装置用基板を用いて半導体装
置を製造する場合は、上記の半導体装置用基板の各々の
回路基板10に半導体素子24を搭載し、半導体素子搭
載面を片面樹脂封止した後、外部接続端子30を接合
し、フレーム11と回路基板10とを連結する連結部1
0aを切断して半導体装置製品を得る。図4はこうして
得られた半導体装置の断面図を示す。26は封止樹脂で
ある。半導体装置の熱放散性を向上させるため、図示例
では半導体素子24の搭載面にサーマルビア32を設
け、サーマルビア32の端部に外部接続端子34を設け
て、外部接続端子34を実装基板に接続するように構成
した。外部接続端子34としてははんだボールの他、リ
ードピンを使用することもできる。また、半導体素子は
キャップ封止することもできる。
When a semiconductor device is manufactured using the above semiconductor device substrate, the semiconductor element 24 is mounted on each circuit board 10 of the above semiconductor device substrate, and the semiconductor element mounting surface is resin-sealed on one side. After that, the external connection terminal 30 is joined to connect the frame 11 and the circuit board 10 to each other.
0a is cut to obtain a semiconductor device product. FIG. 4 shows a sectional view of the semiconductor device thus obtained. 26 is a sealing resin. In order to improve the heat dissipation of the semiconductor device, in the illustrated example, the thermal via 32 is provided on the mounting surface of the semiconductor element 24, the external connection terminal 34 is provided at the end of the thermal via 32, and the external connection terminal 34 is mounted on the mounting substrate. Configured to connect. As the external connection terminal 34, a lead pin can be used instead of the solder ball. Further, the semiconductor element may be cap-sealed.

【0021】本実施形態の半導体装置は、回路基板10
の端面がルータ加工によって形成されることにより、ク
ラックが生じたり、樹脂くずが生じたりすることがな
く、外観的にも良好な製品として得ることができる。ま
た、ルータと樹脂との摩擦により基板の端面が若干融着
され、基板の端面から水分が侵入するといったことを防
止し、従来のメタルコア半導体装置用基板を使用した製
品にくらべてより信頼性の高い半導体装置となってい
る。また、回路基板10の内層に配置したコアメタル1
2のサイズを大きくしたことによって半導体装置の熱放
散性を向上させることが可能になる。
The semiconductor device of the present embodiment has a circuit board 10
Since the end surface of is formed by the router processing, cracks and resin scraps do not occur, and a product with good appearance can be obtained. In addition, it prevents the end face of the substrate from being slightly fused due to the friction between the router and the resin, and prevents moisture from entering from the end face of the substrate, which is more reliable than the product using the conventional metal core semiconductor device substrate. It is an expensive semiconductor device. In addition, the core metal 1 arranged on the inner layer of the circuit board 10
By increasing the size of 2, it is possible to improve the heat dissipation of the semiconductor device.

【0022】本実施形態では半導体装置用基板を作製す
る際にフレーム11部分までコアメタル12を設けて、
フレーム11と回路基板10のほぼ全範囲にコアメタル
12を配置したから、コアメタル12によって補強され
短冊状のフレーム全体としての反り等の変形を防止する
ことができるという利点もある。また、回路基板10に
部分的にコアメタル12を設けた場合と比較して、短冊
状のフレーム全体としての厚さが均等化され、回路基板
10を金型でクランプして片面樹脂封止するといった際
に確実にクランプ力が作用し、的確な樹脂封止が可能に
なるといった利点もある。
In this embodiment, the core metal 12 is provided up to the frame 11 when the semiconductor device substrate is manufactured.
Since the core metal 12 is arranged in almost the entire range of the frame 11 and the circuit board 10, there is also an advantage that deformation such as warpage of the strip-shaped frame as a whole reinforced by the core metal 12 can be prevented. Further, as compared with the case where the core metal 12 is partially provided on the circuit board 10, the thickness of the strip-shaped frame as a whole is equalized, and the circuit board 10 is clamped by a mold and resin-sealed on one side. At that time, there is an advantage that the clamping force is surely applied to enable accurate resin sealing.

【0023】なお、上記実施形態では、回路基板10を
フレーム11で支持して短冊状に形成した半導体装置用
基板について説明したが、一つの回路基板のみをフレー
ムで支持した半導体装置用基板や、縦横に多数個の回路
基板10を配列した大判の半導体装置用基板を用いる場
合も上記実施形態と同様な方法により信頼性の高い回路
基板を得ることができる。
In the above embodiment, the semiconductor device substrate in which the circuit board 10 is supported by the frame 11 and formed in a strip shape has been described. However, a semiconductor device substrate in which only one circuit board is supported by the frame, Even when using a large-sized semiconductor device substrate in which a large number of circuit boards 10 are arranged vertically and horizontally, a highly reliable circuit board can be obtained by the same method as in the above embodiment.

【0024】[0024]

【発明の効果】本発明に係る半導体装置用基板および半
導体装置用基板の製造方法によれば、上述したように、
基板の端面にクラックが発生せず、基板内への水分の侵
入を防止するといった優れた特徴を有する製品として提
供することができ、この半導体装置用基板を用いること
によって、より信頼性の高い半導体装置を得ることがで
きる。また、本発明に係る半導体装置の製造方法によれ
ば、容易に信頼性の高い半導体装置を得ることができる
等の著効を奏する。
According to the substrate for a semiconductor device and the method for manufacturing a substrate for a semiconductor device according to the present invention, as described above,
It can be provided as a product having excellent characteristics such that cracks do not occur on the end surface of the substrate and moisture can be prevented from entering the substrate. By using this semiconductor device substrate, a semiconductor with higher reliability can be provided. The device can be obtained. Further, according to the method of manufacturing a semiconductor device of the present invention, it is possible to easily obtain a highly reliable semiconductor device, and so on.

【図面の簡単な説明】[Brief description of drawings]

【図1】フレームに回路基板を支持した短冊状の基板の
全体形状を示す説明図である。
FIG. 1 is an explanatory diagram showing an overall shape of a strip-shaped board in which a circuit board is supported by a frame.

【図2】フレームから分離した単体の回路基板の構成を
示す説明図である。
FIG. 2 is an explanatory diagram showing a configuration of a single circuit board separated from a frame.

【図3】回路基板の断面図である。FIG. 3 is a cross-sectional view of a circuit board.

【図4】回路基板に半導体素子を搭載した半導体装置の
断面図である。
FIG. 4 is a cross-sectional view of a semiconductor device in which a semiconductor element is mounted on a circuit board.

【図5】フレームに回路基板を支持した従来例の全体形
状を示す説明図である。
FIG. 5 is an explanatory diagram showing an overall shape of a conventional example in which a circuit board is supported by a frame.

【図6】従来の回路基板の断面図である。FIG. 6 is a cross-sectional view of a conventional circuit board.

【符号の説明】[Explanation of symbols]

10 回路基板 10a 連結部 11 フレーム 12 コアメタル 14 樹脂 14a、14b、14c プリプレグ 16 銅箔 18 スルーホール 20 スリット 22 ソルダーレジスト 24 半導体素子 26 封止樹脂 30 外部接続端子 32 サーマルビア 34 外部接続端子 10 circuit board 10a connecting part 11 frames 12 core metal 14 resin 14a, 14b, 14c prepreg 16 copper foil 18 through holes 20 slits 22 Solder resist 24 Semiconductor element 26 Sealing resin 30 External connection terminal 32 Thermal via 34 External connection terminal

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平5−67694(JP,A) 実開 平1−47053(JP,U) (58)調査した分野(Int.Cl.7,DB名) H01L 23/12 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References Japanese Patent Laid-Open No. 5-67694 (JP, A) Actual Development 1-47053 (JP, U) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/12

Claims (9)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 樹脂板からなる単数もしくは複数の回路
基板が、孔の内周縁位置を回路基板の外形に一致させた
所定幅のスリットを隔てて樹脂板からなるフレームに並
設されており、該回路基板の四隅に設けた連結部により
前記フレームに支持された半導体装置用基板において、 前記回路基板と前記連結部と前記フレームとを含む樹脂
板の内部全体に、連続的に金属板が配置され、 前記回路基板の四隅部分を除く外周縁部については、前
記金属板が回路基板の端面よりも内側へ後退して樹脂の
みからなるスルーホール形成範囲に形成され、該スルー
ホール形成範囲にスルーホールが設けられたことを特徴
とする半導体装置用基板。
1. A single or a plurality of circuit boards made of a resin plate are juxtaposed to a frame made of a resin plate, with a slit having a predetermined width that matches the inner peripheral edge position of the hole with the outer shape of the circuit board. In a substrate for a semiconductor device supported by the frame by connecting portions provided at four corners of the circuit board, a metal plate is continuously arranged inside the entire resin plate including the circuit board, the connecting portion, and the frame. In the outer peripheral edge portion excluding the four corners of the circuit board, the metal plate recedes inward from the end surface of the circuit board and is made of resin.
A substrate for a semiconductor device, characterized in that it is formed in a through-hole formation area consisting of only one , and a through-hole is provided in the through-hole formation area.
【請求項2】 複数の回路基板がフレームに支持されて
短冊状に形成されたことを特徴とする請求項1記載の半
導体装置用基板。
2. The substrate for a semiconductor device according to claim 1, wherein a plurality of circuit boards are supported by a frame and are formed in a strip shape.
【請求項3】 樹脂板からなる回路基板の内部全体に、
連続的に金属板が配置され、 前記回路基板の四隅部分を除く外周縁部については、前
記金属板が回路基板の端面よりも内側へ後退して樹脂の
みからなるスルーホール形成範囲に形成され、該スルー
ホール形成範囲にスルーホールが設けられたことを特徴
とする半導体装置用基板。
3. The entire inside of the circuit board made of a resin plate,
Metal plates are continuously arranged, and at the outer peripheral edge portion excluding the four corners of the circuit board, the metal plate recedes inward from the end surface of the circuit board and is made of resin.
A substrate for a semiconductor device, characterized in that it is formed in a through-hole formation area consisting of only one , and a through-hole is provided in the through-hole formation area.
【請求項4】 回路基板の半導体素子の搭載面にサーマ
ルビアが設けられたことを特徴とする請求項1、2また
は3記載の半導体装置用基板。
4. The substrate for a semiconductor device according to claim 1, wherein a thermal via is provided on a surface of the circuit board on which the semiconductor element is mounted.
【請求項5】 樹脂板からなる単数もしくは複数の回路
基板が、所定幅のスリットを隔てて樹脂板からなるフレ
ームに並設されており、該回路基板の四隅に設けた連結
部により前記フレームに支持された半導体装置用基板の
製造方法において、 前記回路基板と前記連結部と前記フレームとを含む樹脂
板の内部全体に、連続的に金属板が配置されるととも
に、前記回路基板の四隅部分を除く外周縁部について
は、前記金属板が回路基板の端面よりも内側へ後退して
樹脂のみからなるスルーホール形成範囲に形成された樹
脂板を形成し、 該樹脂板の表面に配線パターンを形成し、前記スルーホ
ール形成範囲に複数のスルーホールを形成し、 次いで、前記樹脂板にルータ加工を施して、孔の内周縁
位置を回路基板の外形に一致させた所定幅のスリットを
形成することを特徴とする半導体装置用基板の製造方
法。
5. A single or a plurality of circuit boards made of a resin plate are juxtaposed to a frame made of a resin plate with a slit having a predetermined width, and the frame is connected to the frame by connecting portions provided at four corners of the circuit board. In the method for manufacturing a supported substrate for a semiconductor device, a metal plate is continuously arranged in the entire resin plate including the circuit board, the connecting portion, and the frame, and four corner portions of the circuit board are provided. Except for the outer peripheral edge, the metal plate retracts inward from the end surface of the circuit board.
A resin plate is formed in a through hole forming area made of resin only , a wiring pattern is formed on the surface of the resin plate, a plurality of through holes are formed in the through hole forming area, and then the resin plate is formed. A method of manufacturing a substrate for a semiconductor device, which comprises performing a router process to form a slit having a predetermined width such that the inner peripheral edge position of the hole matches the outer shape of the circuit board.
【請求項6】 請求項1または2記載の半導体装置用基
板の回路基板に半導体素子を搭載し、 半導体装置用基板の半導体素子搭載面を片面樹脂封止し
た後、 前記回路基板と前記フレームとの連結部を切断して半導
体装置を製造することを特徴とする半導体装置の製造方
法。
6. A semiconductor device is mounted on the circuit board of the semiconductor device substrate according to claim 1 or 2, and a semiconductor device mounting surface of the semiconductor device substrate is resin-sealed on one side, and then the circuit board and the frame are formed. A method of manufacturing a semiconductor device, which comprises manufacturing a semiconductor device by cutting a connecting part of the semiconductor device.
【請求項7】 請求項3記載の半導体装置用基板の回路
基板に半導体素子を搭載し、 半導体装置用基板の半導体素子搭載面を片面樹脂封止し
て半導体装置を製造することを特徴とする半導体装置の
製造方法。
7. A semiconductor device is manufactured by mounting a semiconductor element on the circuit board of the semiconductor device substrate according to claim 3, and sealing the semiconductor element mounting surface of the semiconductor device substrate on one side with a resin. Manufacturing method of semiconductor device.
【請求項8】 樹脂からなる回路基板の半導体素子の搭
載面に半導体素子が搭載され、半導体素子と回路基板に
形成された外部接続端子とが回路基板に形成されたスル
ーホールを介して電気的に接続された半導体装置におい
て、 前記回路基板の内部全体に、連続的に金属板が配置さ
れ、 前記回路基板の四隅部分を除く外周縁部については、前
記金属板が回路基板の端面よりも内側へ後退して樹脂の
みからなるスルーホール形成範囲に形成され、該スルー
ホール形成範囲にスルーホールが設けられたことを特徴
とする半導体装置。
8. A semiconductor element is mounted on a semiconductor element mounting surface of a circuit board made of resin, and the semiconductor element and an external connection terminal formed on the circuit board are electrically connected through a through hole formed on the circuit board. In the semiconductor device connected to, a metal plate is continuously disposed on the entire inside of the circuit board, and the outer peripheral edge portion excluding the four corners of the circuit board has the metal plate inside the end surface of the circuit board. Back to the resin
It is formed in the through hole forming range consisting only, the semiconductor device characterized by through holes provided in the through-hole forming area.
【請求項9】 回路基板の半導体素子の搭載面にサーマ
ルビアが設けられ、サーマルビアの端部に外部接続端子
が設けられたことを特徴とする請求項8記載の半導体装
置。
9. The semiconductor device according to claim 8, wherein a thermal via is provided on a mounting surface of the semiconductor element of the circuit board, and an external connection terminal is provided at an end of the thermal via.
JP28532795A 1995-11-01 1995-11-01 Semiconductor device substrate, method of manufacturing semiconductor device substrate, method of manufacturing semiconductor device using semiconductor device substrate, and semiconductor device Expired - Fee Related JP3380097B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28532795A JP3380097B2 (en) 1995-11-01 1995-11-01 Semiconductor device substrate, method of manufacturing semiconductor device substrate, method of manufacturing semiconductor device using semiconductor device substrate, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28532795A JP3380097B2 (en) 1995-11-01 1995-11-01 Semiconductor device substrate, method of manufacturing semiconductor device substrate, method of manufacturing semiconductor device using semiconductor device substrate, and semiconductor device

Publications (2)

Publication Number Publication Date
JPH09129781A JPH09129781A (en) 1997-05-16
JP3380097B2 true JP3380097B2 (en) 2003-02-24

Family

ID=17690118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28532795A Expired - Fee Related JP3380097B2 (en) 1995-11-01 1995-11-01 Semiconductor device substrate, method of manufacturing semiconductor device substrate, method of manufacturing semiconductor device using semiconductor device substrate, and semiconductor device

Country Status (1)

Country Link
JP (1) JP3380097B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100760952B1 (en) * 2001-03-30 2007-09-21 앰코 테크놀로지 코리아 주식회사 Strip with holding part to put together
JP3905041B2 (en) 2003-01-07 2007-04-18 株式会社日立製作所 Electronic device and manufacturing method thereof
JP5151158B2 (en) * 2007-01-23 2013-02-27 富士通セミコンダクター株式会社 Package and semiconductor device using the package
KR101169686B1 (en) 2008-11-07 2012-08-06 에스케이하이닉스 주식회사 Substrate for semicondouctor package and methode thereof
JP5543125B2 (en) * 2009-04-08 2014-07-09 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device and manufacturing method of semiconductor device

Also Published As

Publication number Publication date
JPH09129781A (en) 1997-05-16

Similar Documents

Publication Publication Date Title
US7098407B2 (en) Non-solder mask defined (NSMD) type wiring substrate for ball grid array (BGA) package and method for manufacturing such a wiring substrate
JP3726985B2 (en) Manufacturing method of electronic parts
US5012386A (en) High performance overmolded electronic package
KR100596549B1 (en) Semiconductor device and its manufacturing method and semiconductor package
JP4412439B2 (en) Memory module and manufacturing method thereof
US5897334A (en) Method for reproducing printed circuit boards for semiconductor packages including poor quality printed circuit board units and method for fabricating semiconductor packages using the reproduced printed circuit boards
JPH09162322A (en) Surface-mount semiconductor device and manufacture thereof
US20010005042A1 (en) Method of manufacturing a surface mount package
EP0509065A4 (en)
JPH08330473A (en) Printed circuit board with installation groove of solder ball and ball grid array package using it
JPH07147379A (en) Semiconductor device and its manufacture
JP2799472B2 (en) Substrate for mounting electronic components
US6426468B1 (en) Circuit board
JP3380097B2 (en) Semiconductor device substrate, method of manufacturing semiconductor device substrate, method of manufacturing semiconductor device using semiconductor device substrate, and semiconductor device
US5177591A (en) Multi-layered fluid soluble alignment bars
EP3982405A1 (en) Semiconductor package with improved board level reliability
KR100326834B1 (en) Wire-bonded semiconductor device and semiconductor package
US5528457A (en) Method and structure for balancing encapsulation stresses in a hybrid circuit assembly
JPH0452623B2 (en)
US4531285A (en) Method for interconnecting close lead center integrated circuit packages to boards
JPH09116045A (en) Resin-sealed semiconductor device of bga type using lead frame and its manufacture
JP3398580B2 (en) Semiconductor device manufacturing method and substrate frame
JP4677152B2 (en) Semiconductor device
JPH0786459A (en) Semiconductor device
JPH0997964A (en) Printed-wiring board and its manufacture

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20081213

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091213

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091213

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101213

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111213

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121213

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121213

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131213

Year of fee payment: 11

LAPS Cancellation because of no payment of annual fees