JP3376979B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a low resistance layer such as a refractory metal silicide layer on the surface of an impurity diffusion layer having a relatively high resistance value, and a manufacturing method thereof.

[0002]

BACKGROUND ART Master slice type semiconductor integrated circuits such as gate arrays and embedded arrays are manufactured using unfinished wafers (master slices) that have been manufactured before the metal wiring process. A completed wafer is obtained by forming a wiring and a protective film on this master slice according to the circuit function from the user. By keeping the unfinished wafer as an inventory, the delivery time of the semiconductor integrated circuit to the user can be shortened.

In manufacturing this master slice type semiconductor integrated circuit, an unfinished wafer in which basic cells are spread in a matrix is prepared in advance. The placement and wiring of through-holes and metal wiring layers for this unfinished wafer are automatically placed and routed (Automatic Placing & Routin).
g Apparatus).

Each transistor forming a plurality of basic cells formed on an unfinished wafer usually has a channel length of
The channel width is constant. On the other hand, it may be necessary to provide a capability difference between logic cells formed by wiring a plurality of basic cells.

As a countermeasure, it is conceivable to connect transistors in series to form a logic cell having a small driving capability.

However, this measure increases the number of transistors used and hinders high integration.

As another countermeasure, there is one in which a resistor is connected to the output stage of the logic cell of which the capability is lowered to apparently reduce the capability of the logic cell.

As this type of resistance, there is one that utilizes the diffusion resistance of the impurity diffusion layer itself for forming the source and drain of the transistor.

However, in recent years, in order to reduce the resistance between the source / drain and the contact, a low resistance layer such as refractory metal silicide tends to be formed on the surface of the impurity diffusion layer. In this case, even if a diffusion resistance exists in the impurity diffusion layer itself, a current flows through the low resistance layer of the high melting point metal silicide on the surface thereof, so that the diffusion resistance cannot be used.

Therefore, conventionally, as shown in FIG. 12, a P + diffusion region 210 is provided in a region outside the source and drain regions of a plurality of transistors forming a logic cell 200, and a refractory metal except for the region 220 is formed on the surface thereof. It formed a silicide. Thus, in the high melting point metal silicide removal region 220, the diffusion resistance of the P ⁺ diffusion region can be utilized.

In FIG. 12, contacts 23 are formed on the refractory metal silicide layers on both sides of the diffusion resistance region 220.
0, 232 are connected. The drain wiring 240 of the output stage transistor of the logic cell is connected to the contact 230, the output wiring 242 is connected to the contact 232, and thereby the diffusion resistance region 220 is connected to the output stage of the logic cell 200.

The above countermeasures are also effective for a custom IC other than the master slice type semiconductor device, for example. However, in the case of a custom IC, it is possible to make a difference in the driving capability of the logic cell by changing the transistor size. For example, as shown in FIG. 13, a transistor 250 having a narrow channel width can be used, or a transistor 260 having a long channel length can be used as shown in FIG. 14 to reduce the driving capability of a logic cell.
However, the measure for changing the transistor size as shown in FIG. 13 or 14 cannot be adopted in the master slice type semiconductor device.

[0013]

In the prior art shown in FIG. 12, the resistance forming P ⁺ diffusion region 210 and the diffusion resistance region 2 are formed.
It is necessary to secure 20 separately from the transistor formation region, which hinders realization of a highly integrated semiconductor device. Particularly, in the master slice type semiconductor device, since the layout of the logic cells whose drive capability is desired to be lowered is determined later, the resistance forming P ⁺ diffusion regions 210 and the diffusion resistance regions are provided outside the transistor formation regions corresponding to all the transistors. 220 and 220 must be formed on the unfinished wafer. This is
This greatly hinders high integration in the basic cell region formed in the central region of the IC chip.

Therefore, an object of the present invention is to provide a semiconductor device in which a resistance element and a transistor can be formed together without increasing the layout area, and a manufacturing method thereof.

[0015]

According to one embodiment of the present invention, in a semiconductor device in which a logic cell is formed by wiring a plurality of transistors, each of the transistors has a source formed of an impurity diffusion layer, A drain region, a channel region provided between the source and the drain, a gate electrode disposed at a position facing the channel region via a gate insulating layer, and a low resistance formed on the surface of the impurity diffusion layer. And at least one of the transistors has a high resistance region obtained by partially removing the low resistance layer on the surface of the impurity diffusion region in the transistor formation region in the channel width direction of the transistor. It is characterized by

According to one aspect of the present invention, the high resistance region obtained by partially removing the low resistance layer (for example, the refractory metal silicide layer) on the surface of the impurity diffusion region is arranged in the transistor formation region. As shown in FIG. 12, the area is not occupied only to obtain the high resistance region. In order to arrange the high resistance region in the transistor formation region, it may be arranged between the two gate electrodes separated in the channel length direction or between the gate electrode and the element isolation region. Further, by partially removing the low resistance layer in the high resistance region in the channel width direction, it can be used as a resistance element for a current flowing in the channel width direction on the low resistance layer.

In order to use the high resistance region as a resistance element, two contacts connected to the low resistance layer on both sides of the high resistance region, and a first contact connected to one of the two contacts. Wiring may be performed so as to have one wiring layer and the second wiring layer connected to the other one. By doing so, the high resistance region having the diffusion resistance is connected in series as a resistance element in the middle of the first and second wiring layers.

When the high resistance region is not used as a resistance element, the common wiring layer may be connected to the two contacts connected to the low resistance layer on both sides of the high resistance region. In this case, the current flowing through the common wiring layer becomes dominant, and the high resistance region does not function as a resistance element.

The high resistance region may be formed by being divided into a plurality in the channel width direction. To use only one of the divided high resistance regions as a resistance element, two contacts connected to the low resistance layers on both sides of the one high resistance region and one of the two contacts are used. Wiring may be performed using the first wiring layer connected to the second wiring layer and the second wiring layer connected to the other wiring layer. In this way, the degree of freedom for selecting the high resistance region to be used is secured by changing the position of the contact.

When all of the divided high resistance regions are not used as resistance elements, a common wiring is provided for all of the plurality of contacts connected on the low resistance layers on both sides of each high resistance region. Just connect the layers.

When the high resistance region is used as a resistance element, the wiring layer may be connected via a contact directly connected to the high resistance region.

When one embodiment of the present invention is applied to a master slice type semiconductor device, high resistance regions are formed in all basic cells. In this way, the high resistance region in any basic cell can be used as a resistance element according to the wiring result determined later.

Therefore, in the master slice type semiconductor device, the first inter-logical cell wiring in which the high resistance region is connected in series in the middle of the wiring connecting the two logic cells and the middle of the wiring connecting the other two logic cells. Will include the second inter-logic cell wiring in which the high resistance regions are not connected in series.

By connecting the above-mentioned high resistance region to the output stage of the logic cell, the capacity of the logic cell can be lowered without changing the channel length and channel width of the transistor, and for that reason, the area is reduced. Since it is not exclusively used, it is particularly effective for a master slice type semiconductor device.

The high resistance region can be formed by removing the low resistance layer over the entire width in the channel length direction.
Thereby, the high resistance region can be secured as an effective resistance element for the current flowing in the channel length direction. In addition, the high resistance region may be formed by leaving a relatively narrow low resistance layer on the gate electrode side. In this case, when the impurity diffusion layer in which the high resistance region is formed is used as the source or the drain, the source resistance or the drain resistance can be reduced. If the width of the remaining low resistance layer is narrow, the high resistance region can function as a resistance element.

According to another aspect of the present invention, the first step of forming a substrate having a plurality of basic cells each formed of a predetermined number of transistors, and then the arrangement of logic cells and the basic elements required therefor. A second step of determining a wiring connecting the cells and the basic cells, a third step of wiring the plurality of transistors on the substrate based on the determined placement / wiring results, and cutting the substrate. And a fourth step of shredding into a plurality of semiconductor devices. In the first step, a source region and a drain region formed of an impurity diffusion layer, and a channel region provided between the source and the drain are formed. Forming a plurality of transistors each having a gate electrode arranged at a position facing the channel region through a gate insulating layer and a low resistance layer formed on the surface of the impurity diffusion layer. And in all the basic cells, forming at least one high resistance region in which the low resistance layer on the surface of the impurity diffusion layer in the transistor formation region is partially removed in the channel width direction of the transistor, The wiring formed in the third step includes a first inter-logical cell wiring in which the at least one high resistance region is serially connected in the middle of a wiring connecting the two logic cells, and the other two logic cells. The second logic inter-cell wiring in which the at least one high resistance region is not connected in series is included in the wiring connecting the cells.

In the master slice type semiconductor device formed by this semiconductor device manufacturing method, even if all transistor sizes are the same, the capacity of some logic cells is changed only by wiring without increasing the area. can do.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments in which the present invention is applied to a master slice type semiconductor device will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a partial plan view of an IC in which a resistor R (= R1 + R2) is connected to an output stage of an inverter 100 as an example of a logic cell having a small driving capability. 2 is a sectional view taken along the line AA of FIG. 1, FIG. 3 is a sectional view taken along the line BB of FIG. 1, and FIG. 4 is a sectional view taken along the line CC of FIG.
FIG. 5 is an equivalent circuit diagram of FIG.

In FIGS. 1 and 5, the inverter 100
Is the power supply voltage (VDD) wiring layer 110 and the ground voltage (VS
S) It has a P-type MOS transistor 120 and an N-type MOS transistor 130 connected in series with the wiring layer 112.

As shown in FIG. 1, in the first basic cell column 122 in which the P-type MOS transistor 120 is formed, one basic cell has, for example, three gate electrodes 120A.
P ⁺ diffusion regions 124 are formed on both sides of 120 C. Similarly, in the second basic cell row 132 in which the N-type MOS transistor 130 is formed, in one basic cell, for example, N ⁺ diffusion regions 134 are formed on both sides of three gate electrodes 130A to 130C. There is.

As shown in FIG. 2, a channel region 123 is formed between the P ⁺ diffusion regions 124 to be the source or the drain, and the gate insulating layer 1 is formed on the channel region 123.
Gate electrodes 120 </ b> A to 120 </ b> C are formed via 25. Element isolation regions 127 and 127 are formed next to the P ⁺ diffusion regions 124 and 124 at the outermost ends.

Similarly, as shown in FIG. 4, the channel region 1 is formed between the N ⁺ diffusion regions 134 to be the source or the drain.
33 is formed, and gate electrodes 130A to 130C are formed on the channel region 133 via the gate insulating layer 135. In addition, the N + diffusion region 134 at the outermost end,
Element isolation regions 137 and 137 are formed adjacent to 134.

As shown in FIG. 2, the P-type MOS transistor 120 has a gate electrode 120C, a drain 126 and a source 128. Similarly, the N-type MOS transistor 130, as shown in FIG.
It has a drain 136 and a source 138. Further, as shown in FIGS. 2 and 4, a refractory metal silicide layer 140 as a low resistance layer is formed on the surface of the P ⁺ diffusion region 124 and the N ⁺ diffusion region 134, and its source resistance and drain resistance are It is low.

These P-type and N-type MOS transistors 1
A plurality of contacts 160 are provided to connect 20, 130 to various wiring layers.

P-type and N-type MOS transistors 120,
Each of the gate electrodes 120C and 130C in FIG.
As shown in FIGS. 2, 4 and 5, a plurality of contacts 1
Input signal (IN) via 60 and wiring 170, 172
Is commonly input. The drain 126 of the P-type MOS transistor 120 and the drain 136 of the N-type MOS transistor 130 have a plurality of contacts 160 and wirings 17.
4 are connected. The above wiring configures the inverter 100 shown in FIG.

As shown in FIG. 1, the gate electrodes 120A,
The refractory metal silicide layer 140 on the surface of the P ⁺ diffusion region 124 between 120B is removed in a plurality of, for example, two regions divided in the channel width direction D, and the first and second high resistance regions are formed. Diffusion resistance regions 150A and 150B are provided.

Each of the diffusion resistance regions 150A and 150B
Is the gate electrodes 120A, 120B as shown in FIG.
It is formed by removing the refractory metal silicide layer 140 along the channel length direction E in between.

To form the diffusion resistance regions 150A and 150B, the refractory metal silicide layer once formed may be partially etched, or the diffusion resistance region 15 may be formed.
The refractory metal silicide forming step may be performed in a state where the regions to be 0A and 150B are covered with a mask such as SiO ₂ . The high melting point silicide forming step is
A full silicide process for forming silicide in all regions such as on the gate electrode or a field silicide process for forming silicide only in the field region may be used.

As shown in FIG. 1, the contacts 1 are formed at two positions on both sides of the region including the first and second diffusion resistance regions 150A and 150B and separated in the channel width direction D.
60A and 160B are provided, respectively. One contact 160A is connected to the wiring layer 174, and the other contact 160B is connected to the wiring layer 176. With this wiring, the output of the inverter 100 is connected via the first diffusion resistance region 150A (resistance value R1) and the second diffusion resistance region 150B (resistance value R2), so the equivalent circuit as shown in FIG. Is configured.

As described above, according to the present embodiment, the diffusion resistance region 150 is formed in the transistor formation region while forming the refractory metal silicide on the surface of the impurity diffusion region.
Since A and 150B are provided, it does not hinder high integration of the transistor.

(Second Embodiment) In the above-described first embodiment, a master slice in which a large number of basic cells are formed in advance is subjected to wiring determined by an automatic placement and routing apparatus, and thereafter, 1 illustrates one mode of a semiconductor device obtained by cutting a master slice.

In the second embodiment, a semiconductor device obtained by applying different wiring to the same master slice will be described.

FIG. 6 shows all the contacts 16 shown in FIG.
0 (including 160A and 160B) and all wiring 11
It shows one basic cell in a master slice (unfinished wafer) in a state where 0, 112, 170 to 176 are not formed.

The basic cell shown in FIG. 6 is different from the conventional one.
The diffusion resistance regions 150A and 150B are formed in the basic cell, and the diffusion resistance regions 150A and 150B are formed.
Are formed in all basic cells.

The master slice type semiconductor device is manufactured through the steps shown in FIG. First, a large number of master slices having a large number of basic cells shown in FIG. 6 are manufactured and stocked (step 1). Next, the netlist defining the connections between the basic cells is input to the automatic placement and routing apparatus in which the library is registered in advance (step 2). Thereafter, the automatic placement and routing apparatus determines the placement of the logic cells and the wiring within and between the basic cells for obtaining the placement (step 3). Thereafter, wiring and a protective film are applied to the master slice (step 4), and the master slice is further shredded to obtain a semiconductor device (step 5).

Here, it is possible to manufacture various semiconductor devices desired by the user by changing the definition in the netlist used in step 2 of FIG. 7 while using the same master slice. .

Therefore, by changing the definition of the netlist, in addition to the semiconductor device shown in FIG.
Connect only one of the resistors R1 or R2 to the output stage of
Alternatively, both of them may not be connected.

FIG. 8 shows a wiring state in which only the resistor R1 is connected to the output stage of the inverter 100. The difference from FIG. 1 is that the position of the contact 160B is provided between the first and second diffusion resistance regions 150A and 150B.

In this way, the output of the inverter 100 is
It can be obtained only through the first diffusion resistance region 150A and not through the second diffusion resistance region 150B.

9 and 10 show a wiring state in which neither the resistors R1 nor R2 are connected to the output stage of the inverter 100. Note that, unlike FIG. 1, in FIG. 9, the P ⁺ diffusion regions 124 on both sides of the gate electrode 120B are formed in the P-type MOS.
Used as the source and drain of the transistor 120,
Although the N ⁺ diffusion regions 134 on both sides of the gate electrode 130B are used as the source and drain of the N-type MOS transistor 130, there is no difference in that the inverter 100 can be configured as in FIG.

9 is essentially different from FIG. 1 in that the contacts 160A to 160C are provided on both sides of each of the first and second diffusion resistance regions 150A and 150B, and that the contacts 160A to 160C are provided. That is, it is connected to the common wiring layer 178.

Also in FIG. 10, contacts 160A to 160C are provided on both sides of the first and second diffusion resistance regions, and the contacts 160A to 160C are connected to the common power supply layer 110.

In both FIGS. 9 and 10, the inverter 10 is used.
The output of 0 can be obtained without passing through either the first diffusion resistance region 150A or the second diffusion resistance region 150B, and the performance of the inverter 100 is not deteriorated.

The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the gist of the present invention.

For example, in the above-described embodiment, the P ⁺ diffusion region 1 between the gate electrodes 120A and 120B in the basic cell is formed.
Although two diffusion resistance regions 150A and 150B are provided in 24, one or three or more diffusion resistance regions 150A and 150B may be provided. However,
Providing a plurality of diffusion resistance regions is preferable in that the degree of freedom of the resistance value selectable by the wiring increases.

The diffusion resistance region is not necessarily provided between the gate electrodes 120A and 120B, and is provided in the N ⁺ diffusion region 134 in addition to the other regions of the P ⁺ diffusion region 124 as long as it is in the transistor formation region. May be. Therefore, the position where the diffusion resistance region of the present invention is formed is not limited to the position between the gate electrodes as in the above-described embodiment, but may be between the gate electrode and the element isolation region.

Further, as the wiring when the diffusion resistance region is used as a resistance element, as shown in FIGS. 1 and 8,
The contact is not limited to the contact provided in the low resistance layer 140 on both sides of the diffusion resistance region 150A and / or 150, and a contact may be provided in the diffusion resistance region and a wiring layer may be connected to the contact.

The diffusion resistance region is not limited to the one formed by removing the refractory metal silicide over the entire length in the channel length direction E as shown in FIG. 4, but as shown in FIG. The refractory metal silicide layer 140 may be left on the 120B side. In this way, for example
As in 0, when the impurity diffusion region 124 in the portion where the diffusion resistance regions 150A and 150B are formed is used as the source, the source resistance can be reduced. Similarly, when the impurity diffusion region is used as the drain, the drain resistance can be reduced. The refractory metal silicide layer 14 is formed on the gate electrode side.
Even if 0 is left, if the width of the remaining refractory metal silicide layer 140 is narrowed to, for example, the minimum width that can be formed by microfabrication, the diffusion resistance regions 150A and 150B.
Can be used as a resistance element.

When the present invention is applied to a master slice type semiconductor device, the structure of the basic cell is as shown in FIG.
It is not limited to those shown in. The basic cell shown in FIG. 6 has a maximum of three P-type MOS transistors and a maximum of three N-type MOS transistors.
Although it is formed of transistors, the number of transistors can be variously changed. The basic cell shown in FIG. 6 has three gate electrodes 1 in the first basic cell column 122.
20A to 120C, and a separate gate type having three gate electrodes 130A to 130C in the second basic cell column 132, but as an integrated gate type sharing the gate electrode in the first and second basic cell columns 122 and 132 Good.

The present invention can be applied not only to the transistors of the logic cell formation portion but also to the transistors of the input / output cells around it.

Needless to say, the present invention can be applied not only to the master slice type semiconductor device but also to other semiconductor devices such as a custom IC.

[Brief description of drawings]

FIG. 1 is a partial plan view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA of FIG.

FIG. 3 is a sectional view taken along line BB of FIG.

FIG. 4 is a sectional view taken along line CC of FIG.

5 is an equivalent circuit diagram of a circuit configured by the wiring shown in FIG.

FIG. 6 is a partial plan view of a master slice used in the second embodiment of the present invention.

FIG. 7 is a flowchart showing steps of manufacturing a master slice type semiconductor device.

8 is a partial plan view of a semiconductor device obtained by applying wiring different from that in FIG. 1 to the master slice shown in FIG.

9 is a partial plan view of a semiconductor device obtained by providing the master slice shown in FIG. 6 with wiring different from those in FIGS. 1 and 8. FIG.

FIG. 10 shows the master slice shown in FIG.
FIG. 10 is a partial plan view of a semiconductor device obtained by providing wiring different from those in FIGS. 8 and 9.

FIG. 11 is a cross-sectional view showing a modified example of the BB cross section of FIG. 1.

FIG. 12 is a partial plan view of a conventional semiconductor device in which a diffusion resistance region is formed outside a transistor formation region.

FIG. 13 is a partial plan view of a conventional semiconductor device in which the channel width is narrowed to reduce the capacity of a logic cell.

FIG. 14 is a partial plan view of a conventional semiconductor device in which the channel length is increased to reduce the capacity of a logic cell.

[Description of Reference Signs] 100 inverter (logic cell) 110 power supply voltage wiring layer 112 ground voltage wiring layer 120 P-type MOS transistors 120A to 120C gate electrode 122 first basic cell column 123 channel region 124 P ⁺ diffusion region 125 gate insulating layer 126 drain 127 element isolation region 128 source 130 N-type MOS transistors 130A to 120C gate electrode 132 second basic cell column 133 channel region 134 N ⁺ diffusion region 135 gate insulating layer 136 drain 137 element isolation region 138 source 140 refractory metal silicide Layer (low resistance layer) 150A, 150B Diffusion resistance region (high resistance region) 160, 160A, 160B, 160C Contact 170-178 Wiring layer

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Claims (10)

(57) [Claims] 1. A semiconductor device in which a logic cell is formed by wiring a plurality of transistors, wherein each of the transistors is provided between a source / drain region formed of an impurity diffusion layer and the source / drain. And a low resistance layer formed on the surface of the impurity diffusion layer, and a gate electrode disposed at a position facing the channel region via a gate insulating layer, and a low resistance layer formed on the surface of the impurity diffusion layer. The transistor has a high resistance region formed by partially removing the low resistance layer on the surface of the impurity diffusion region in the transistor formation region in the channel width direction of the transistor, and the high resistance region on both sides sandwiching the high resistance region. Connected on low resistance layer
Two contacts and a first wiring layer connected to one of the two contacts
And a second connection connected to the other one of the two contacts.
And a line layer . 2. The method of claim 1, at least one other of said transistors, said high resistance region, and the other two contacts connected on the low-resistance layer of both sides of the high resistance region, And a common wiring layer connected to the other two contacts. 3. The high resistance region according to claim 1, wherein the high resistance region is divided into a plurality in the channel width direction, and the at least one transistor has two or more.
The two low resistance layers on both sides of the high resistance region.
A semiconductor device in which contacts of are connected . 4. The high resistance region according to claim 3 , wherein at least one of the other transistors is divided in the channel direction.
And a plurality of contacts connected to the low resistance layer on both sides of each of the divided high resistance regions, and a wiring layer commonly connected to the plurality of contacts. Characteristic semiconductor device. 5. The device according to claim 1 , wherein at least one of the other transistors has the high resistance region, a contact connected to the high resistance region, and a wiring layer connected to the contact. Characteristic semiconductor device. 6. In any one of claims 1 to 5, each of the basic cells in a predetermined number of the transistors is configured, at least one of said by between basic cells within or basic cell of said each is a wiring A semiconductor device in which logic cells are formed and the high resistance regions are formed in all the basic cells. 7. The method of claim 6, wiring for connecting the between the first logic cell, wherein the high-resistance region in the middle wiring connecting between two of said logic cells are connected in series interconnection, between the other two of said logic cells A second inter-logic-cell wiring in which the high resistance region is not connected in series is provided in the middle of the semiconductor device. 8. In any one of claims 1 to 7, wherein the high resistance region is a semiconductor device, characterized in that connected in series to the output stage of the logic cell. 9. In any of claims 1 to 8, wherein the high resistance region is a semiconductor device characterized by being formed by removing across the low-resistance layer to the entire width of the channel length direction . 10. A first step of forming a substrate having a plurality of basic cells each formed of a predetermined number of transistors, and thereafter arranging logic cells and the inside and the basic cells necessary therefor. A second step of deciding a wiring connecting the two, a third step of arranging the plurality of transistors on the substrate based on the determined arrangement / wiring results, and cutting the substrate into a plurality of semiconductor devices. A fourth step of chopping, and in the first step, the source and drain regions formed of the impurity diffusion layer, the channel region provided between the source and the drain, and the channel region are opposed to each other. Forming a plurality of transistors each having a gate electrode disposed at a position via a gate insulating layer and a low resistance layer formed on the surface of the impurity diffusion layer, and In the basic cell, at least one high resistance region is formed by partially removing the low resistance layer on the surface of the impurity diffusion layer in the transistor formation region in the channel width direction of the transistor. The wiring formed in the process includes a first inter-logical cell wiring in which the at least one high resistance region is connected in series in the middle of a wiring connecting the two logic cells and another two logic cells. A method of manufacturing a semiconductor device, comprising: a second inter-logic cell wiring in which the at least one high-resistance region is not connected in series in the middle of wiring.