JP3372873B2 - Microprocessor with main memory prefetch mechanism - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly, to a necessary part of data on the main memory required for transaction processing such as packet data processing. Pre-stored in a high-speed accessible memory device provided inside the microprocessor chip (hereinafter,
This pre-storing operation is prefetched (pre-fet).
(ch)), the present invention relates to a microprocessor equipped with a prefetch mechanism for the main memory, which can significantly reduce the program waiting time for accessing the main memory.

[0002]

2. Description of the Related Art A conventional cache (cac) is used as a main memory access device for preliminarily storing a portion of data in the main memory expected to be needed in a high-speed accessible memory element provided inside a microprocessor chip.
he) A memory mechanism is known. However, in the conventional cache memory mechanism, access to the main memory can be omitted if the data stored in the cache memory in advance can be read (that is, if the data is hit), but the data of the address to be read There (If you that mishit) when not being copied into the cache memory, requires reading processing of the necessary data block to access the main memory, during which,
Internal processing is delayed.

For this reason, in a general-purpose microprocessor, various measures have been taken to increase the cache hit rate in order to improve the average processing performance on the premise of the occurrence of a mishit.

[0004]

Even in transaction processing, if a sufficiently large buffer memory can be prepared before the processor, such cache memory mechanism can improve the average processing performance. (AsynchronousTran
In a process such as a sfer mode) switch that requires strict real-time processing, the buffer size is limited due to the problem of data delay in addition to the problem of hardware size. There is a risk that it will drop significantly and the system will collapse.
Therefore, in such processing with strong real time,
It was not possible to make the microprocessor perform high-load processing assuming the cache memory mechanism.

The object of the present invention is sufficient for transaction processing that requires severe real-time processing, such as packet data processing, which can replace or be used together with the conventional cache memory mechanism having such problems. By providing a microprocessor having an efficient main memory memory access function that can be supported, even in such a process, other processes are prevented from waiting during the access to the main memory. Therefore, the efficiency of the processor is improved, and the processing time of the processed data in the processor is shortened comprehensively.

Another object of the present invention is to provide a highly versatile microprocessor in which the user can freely program the access process to the main memory.

Further, in comparison with the processing such as the hit or miss hit of the cache memory mechanism which largely depends on the data content, the processing time can be predicted sufficiently accurately according to the processing content at the time of programming, and the design of the processing having a strong real time property is performed. An object of the present invention is to provide a microprocessor that can be applied easily and surely.

[0008]

In the present invention, a pipe line processing mechanism is used for processing the processed data. That is, assuming that the processed data arrives continuously, each processed data processing circuit of an arbitrary number of processed data processing circuits is provided with four buffer memories, and the unit processed data of the incoming processed data string is The processing data is written to the buffer memory, and the buffer memory transits the state stepwise according to the progress of the processing of the unit processed data to be stored, and the data required for the processing in the latter stage is I tried to read it from the memory.

That is, a bus control unit for arbitrating the bus usage for an access request to an main memory which is commonly accessed by the arbitrary number of processed data processing circuits and the processed data processing circuits. And before
Installed inside each of the arbitrary number of processed data processing circuits.
In a microprocessor having a main memory memory prefetch mechanism according to the present invention, each of the arbitrary number of processed data processing circuits of the microprocessor has a plurality of buffer memories and From the input control circuit for writing the processed data sequentially input to the processed data processing circuit to the connected one of the plurality of buffer memories, and the processed data written to the connected one of the plurality of buffer memories. A prefetch control unit for prefetching the data of the main memory memory, which is specified as being necessary for the required processing of the processed data, into the internal memory; Regarding the processed data, the prefetch control unit pre-processes the processed data into the internal memory. A processor core section for performing the required processing using the Etchi the data of the main storage memory has been,
An output control circuit for outputting processed data written in one of the plurality of connected buffer memories to an output port, each of the input control circuit, the prefetch control unit, the processor core unit, and the output control circuit To
A buffer memory for controlling pipeline processing of processed data sequentially input to the processed data processing circuit by sequentially connecting the plurality of buffer memories in consideration of respective processing states of asynchronous processing. And a state management unit.

Further, the buffer memory state management section is
Regarding the plurality of buffer memories, a state of waiting for connection to the input control circuit is set to state 0, a state of being connected to the input control circuit and containing processed data is set to state 1, and processing to be performed by the input control circuit is set. After the data entry is completed, the state waiting for connection to the prefetch control unit is set to 1.5.
The state connected to the prefetch control unit is state 2, the state connected to the processor core unit is state 3, and the state connected to the output control circuit and the data to be processed is output. When 4 is set, one of the buffer memories in the state 0 is transited to the state 1 when the preceding buffer memory finishes the state 1 and the processed data input to the input control circuit becomes 1 unit or more. ,
The head of the queue of the buffer memory in the state 1.5 when the buffer memory in the state 1.5 is added to the end of the queue of the buffer memory in the state 1.5 and the preceding buffer memory finishes the state 2 To the state 2, the preceding buffer memory finishes the state 3, and the buffer memory in the state 2 is changed to the state on condition that the prefetch of the specified data in the main memory to the internal memory is completed. 3, the buffer memory in the state 3 is transited to the state 4 on condition that the preceding buffer memory finishes the state 4 and the data writing to the main memory generated by the required processing is completed. , The buffer memory which has completed the state 4 is controlled to be incorporated into the state 0.

Further, the internal memory has a prefetch memory and a queuing buffer which are composed of two sides, A side and B side, and the prefetch control section performs the required processing of the respective processed data of the connected buffer memory. Data of the main memory specified as necessary for prefetching by alternately using the front side and the B side, and the processor core section uses the prefetch control section of the A side and the B side. By performing the required processing with reference to a non-existing surface and accumulating the write data to the main storage memory, which is generated due to this, in the queuing buffer, the reference is required for the first time according to the result of the required processing. Executing the required processing without being affected by the usage state of the memory bus, except for reading data from the main memory. And it features.

Therefore, the required processing in the processor core unit can be executed asynchronously with the access to the main memory, and even in the transaction processing such as packet data processing which requires strict real time, the main memory is required. During the access to, the other processing that does not require access to the other main storage memory does not wait for processing, and the processing time of the processed data in the processor can be shortened as a whole.

Further, even if a memory element having a large access time or a long latency is used, it does not directly lead to an increase in the program execution waiting time, so that an inexpensive memory element can be used for the main memory.

Further, the prefetch control unit of the microprocessor having the prefetch mechanism of the main memory according to the present invention has a prefetch address memory composed of CAM and is necessary for the required processing of the processed data. A prefetch address, which is a read destination of the data of the main memory specified to be present, and a storage destination address of the prefetch memory in which this data is to be stored are calculated and stored in the same address of this prefetch address memory And waiting for the end of the calculation of the prefetch address and the storage destination address of the preprocessor unit for the processed data,
A process of issuing a prefetch request to the bus control unit, reading the data of the main memory from the prefetch address with permission to use the memory bus, and storing the data in the storage destination address of the prefetch memory,
A memory access unit for executing all prefetch addresses stored in the prefetch address memory, wherein the processor core unit performs the required processing on the processed data by the preprocessor unit. When the prefetch address of the data to be processed next is finished prior to the end of the calculation, a priority write request is issued to the bus control unit and the use permission of the memory bus is obtained and stored in the queuing buffer. The process of writing the written data to the main memory to the main memory is executed for all the data accumulated in the queuing buffer, and the end of the calculation of the prefetch address of the next processed data is the required process. If the process is completed prior to Issues a non-priority write request to the bus control unit, and issues a priority write request to the bus control unit after the required processing is completed, and is stored in the queuing buffer with permission to use the memory bus. At the same time that the write data to the main memory is written to the main memory, the prefetch address memory is searched through the memory access unit, and the data of the address matching the write address to the main memory is prefetched. Queuing for executing a process of updating the prefetch memory with the write data to the main memory using the storage destination address obtained from the search result for all the data stored in the queuing buffer A buffer control unit, wherein the bus control unit When the required processing for the processed data of the Sassacor unit is completed prior to the end of the calculation of the prefetch address of the next processed data, the bus is used for the priority write request with priority over the prefetch request. When permission is given and the end of the calculation of the prefetch address of the next processed data precedes the required processing for the processed data of the processor core unit, the priority write request is given priority over the priority write request. It is characterized by performing bus use arbitration for giving a bus use permission to the prefetch request.

Therefore, even if the required processing is performed asynchronously with the access to the main memory, the consistency of the data in the main memory can be maintained.

Further, the processor core unit of the microprocessor having the main memory prefetch mechanism according to the present invention has an instruction memory, and the required processing is stored in the instruction memory by the user through the external CPU bus. The prefetch address of the data of the main memory which is executed according to the program and which is specified by the prefetch control unit as having the instruction memory and necessary for the required processing is stored in this instruction memory by the user via the external CPU bus. It is characterized in that it is calculated according to a stored program.

Therefore, the user can freely program the access process to the main memory and a microprocessor with high versatility can be provided. In addition, compared to the processing that greatly depends on the data content such as hit and miss hit of the cache memory mechanism, the processing time can be predicted sufficiently accurately according to the processing content at the time of programming, and it is easy to design the processing with strong real time, Further, it is possible to provide a microprocessor that can be reliably applied.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of a main memory access device of the present invention. This main memory access device includes an arbitrary number of processed data processing circuits 108 and an arbitrary number of processed data processing circuits 108.
Bus control for arbitrating access requests from the main storage memory 112 from any number of the processed data processing circuits 108 and for interfacing with the main storage memory 112, which is shared as a work memory when processing the processed data. And a section 111. In the circuit to be processed the data processing circuit 108 for processing any length of data to be processed represented by the packet data, because the circuits of any number of the processed data processing circuit 108 are mutually identical construction, the left end of the drawing is shown only structure of the treated data processing circuit 108.

The treated data processing circuit 108 is a buffer memory 105 for storing the output port 102, one of the processed data, respectively to output the processed data to the input port 101, which is processed to receive the processed data sequence is 4, a buffer memory status management unit 107 that manages the status of each buffer memory 105, an input control circuit 104 for writing data to be processed from the input port 101 to the buffer memory 105 in status 1 (described later), The output control circuit 106 that reads the buffer memory 105 in the state 4 (described later) in which processed data is stored, the processor core unit 110 that processes the processed data, and the processor core unit 110 stores the processed data. A prefetch (pre) that specifies and reads in advance the data in the main memory that is necessary for processing And a fetch) controller 109. The four-sided buffer memory 105 and the buffer memory state control unit 107 are collectively referred to as an input / output buffer memory circuit 103. The main memory memory access device includes
From outside via the external CPU bus 129, operation instruction information by a predetermined program, that is, a processing program of data to be processed for the processor core unit 110 and calculation of a prefetch address for the prefetch control unit 109. Program is set.

Next, an outline of the operation of each unit in the configuration of FIG. 1 will be described focusing on the state transition of the buffer memories 105 on the four sides. The arbitrary number of processed data processing circuits 108 share the main memory 112. The processed data is input from the input port 101, and the processed data is output port 1
It is output from 02. The processed data that sequentially arrives at the input port 101 is written by the input control circuit 104 into any one of the four buffer memories 105.

FIG. 2 is an explanatory diagram showing the state transition of the buffer memory 105 of FIG. The input / output buffer memory circuit 103 will be described below with reference to FIGS. 1 and 2. There are four buffer memories 105 in the input / output buffer memory circuit 103, and the states of these buffer memories 105 are managed by the buffer memory status management unit 107. Each buffer 105
Shifts between six states as shown in FIG. As shown in FIG. 2, the order of state transition is constant, and which buffer memory 1
05 also state 0 → state 1 → state 1.5 → state 2 → state 3 →
State transition is made in the order of state 4 → state 0. Buffer memory 1
In 05, the connection is switched to a different circuit in the chip for each state transition, and 1 is set between the state 0 and the state 0 again.
A unit of processed data is processed.

Immediately after the initialization of the main memory access device of the present invention, the buffer memory 105 is in the unused state 0 on all four sides and forms a queue. When the data received by the input port 101 becomes one unit or more, the buffer memory state control unit 107 connects the buffer memory 105 at the head of the queue to the input control circuit 104. This state corresponds to the state 1 in FIG. Buffer memory 105
Transitions to the state 1, the input control circuit 104 writes 1 unit of received data to the buffer memory 105 in the state 1, and the buffer memory 105 immediately transits to the state 1.5 after the writing is completed. In the state 1.5, the buffer memory 105 stays in the state 1.5 until all the first-arriving buffer memories 105 finish the processing in the state 2.

At this time, when the data to be processed arrives continuously, while the buffer memory 105 in the unused state (that is, the state 0) exists, the new buffer memory 105 is transited to the state 1 and the next processed data is transmitted. The processing data is written in the buffer memory 105. Therefore, a plurality of buffer memories 10
5 may assume the state 1.5, at which time a queue is formed. When the first-arrival buffer memory 105 finishes the state 2, the buffer memory state control unit 107 connects the buffer memory 105 at the head of the queue in the state 1.5 to the prefetch control unit 109. This state corresponds to the state 2 in FIG. In the state 2, the value of the buffer memory 105 is read from the prefetch control unit 109. In the state 2, when the condition for ending the state 2 of the buffer memory 105 itself and the condition for ending the state 3 of the first-arrival buffer memory 105 are met,
The buffer memory state control unit 107 connects the buffer memory 105 to the processor core unit 110. This state corresponds to the state 3 in FIG.

In the state 3, the processed data of the buffer memory 105 can be referred to / updated from the processor core unit 110. Similarly to the state 2, in the state 3, when the conditions for ending the processing of the buffer memory 105 itself in the state 3 and ending the state 4 of the first-arrival buffer memory 105 are satisfied, the buffer memory state control unit 107 controls the output of the buffer memory 105. Connect to circuit 106. This state corresponds to the state 4 in FIG. In the state 4, the contents of the buffer memory 105 are transferred to the output control circuit 106. The state 4 transits to the state 0 upon completion of the processing, and the buffer memory 105 is at the end of the queue of the state 0.

Each of the four buffer memories 105 makes the state transition in this way, and the input / output buffer memory circuit 103 as a whole has a pipeline (pi) of processed data.
function as a processing mechanism. Such a pipeline processing mechanism is described in detail in, for example, "I / O buffer memory circuit" disclosed in Japanese Patent Application Laid-Open No. 10-106253 filed by the applicant of the present application,
The input / output buffer memory circuit 103 described above corresponds to a case where the buffer memory has four sides in the above invention. In the present invention, by applying this pipeline processing mechanism of the processed data, the data which can be specified from the content of the processed data and the like that is necessary for the processing (state 3) in the processor core unit 110 is mainly used in the state 2. Storage memory 11
By prefetching from 2, the influence of the waiting time for accessing the main memory 112 on the entire processing time is minimized.

Hereinafter, the prefetch control unit 109 and the processor core unit 1 will be focused on the access to the main memory 112.
The function sharing of 10 and the outline of each operation will be described. The purpose of the prefetch control unit 109 is to allow the processor core unit 110 to process the data to be processed stored in the buffer memory 105 in the state 3 in the main memory 11 required.
Most of the data on 2 is specified and read when the data to be processed is in state 2. There are two methods for specifying the read address. The first method is to use the buffer memory 10 in the state 2 via the data line 120.
The type of the processed data that has arrived is determined by reading the contents of No. 5, and in the cell processing in the ATM communication system, for example, the VPI (Vertical Pa) of the packet is determined.
th identifier), VCI (Vertical Channel)
l identifier), the read address of the required data is specified from the header information such as the cell type, and the second method is the processing of a task activated at a constant cycle interval, such as periodic arrival monitoring of a fault monitoring cell. This is a method in which the prefetch control unit 109 has a timer function like the data used in the above, and the processing contents and the read address of the required data are specified by the time measurement and the main memory 112 is read.

FIG. 8 is a block diagram showing the detailed arrangement of the prefetch control unit 109 shown in FIG. Hereinafter, FIG. 1 and FIG.
The outline of the configuration and operation of the prefetch control unit 109 will be described with reference to FIG. As shown in FIG. 8, the prefetch control unit 109 is composed of two parts, a preprocessor unit 500 and a memory access unit 501. The preprocessor unit 500 is a microprocessor designed by itself for its own purpose, and has a minimum instruction set and storage resources necessary for implementing prefetch processing. Instruction memory 59
0 is built in the preprocessor unit 500, and external C
A program is set in this instruction memory 590 via the PU bus 129. The address of the main memory 112 to be prefetched, that is, the prefetch address is calculated by executing the program set in the instruction memory 590, and the prefetch address as the calculation result is stored in the prefetch address memory 595. The prefetch address memory 595 is a CAM (Content Addressable Memory: Content Addressable Memory).
Memory).

The memory access unit 501 reads the main memory 112 according to the prefetch address calculated by the preprocessor unit 500. The start of access to the main memory 112 means the end of the calculation of the prefetch address from the preprocessor unit 500 and the dedicated instruction afin.
Started by When the dedicated instruction afin is executed, a request signal is sent to the bus control unit 111 via the control bus 128. In response to this, the bus control unit 111 arbitrates with the read / write request from the processor core unit 110, and sends the control bus 1 to the memory access unit 501.
A bus use permission signal is returned via 28. Upon receiving the bus use permission signal, the memory access unit 501 sends the read address to the address bus 127, and the control bus 12
By sending a read instruction signal to the bus control unit 111 via 8, the bus control unit 111 reads the main memory 112.

The read data is sent to the prefetch memory 5 of the memory access unit 501 via the data bus 126.
It is stored in one of 97 and 598. The transmission of the request signal is continued until the read requests for all the prefetch addresses calculated by the preprocessor unit 500 are permitted, and the same read processing is continued until the reading of all the prefetch addresses is completed.

When all the prefetch addresses calculated by the preprocessor unit 500 have been read,
The prefetch control unit 109 notifies the buffer memory state control unit 107 of the end of state 2 via the signal lines 543 and 122. After that, immediately if the first-arrival buffer memory 105 has already completed the state 3, otherwise, the first-arrival buffer memory 105 waits for the completion of the state 3, and then the relevant buffer memory 105 of the state 2 becomes the status 3 Transition to. In synchronization with the transition of the buffer memory 105 to the state 3, the processor core unit 110 is notified from the buffer memory state control unit 107 via the signal line 123 that the processed data has arrived.

The program of the processor core unit 110 is
The process execution is started by the arrival of the data to be processed as a trigger, and the data pre-fetched by the prefetch control unit 109 at the time of the process is immediately referred to via the data line 125. Therefore, for data that can be specified in advance and prefetched, the next instruction does not enter the processing waiting state because the main storage memory 112 of the data is waiting to be read.

Next, reading of data that cannot be prefetched by the prefetch control unit will be described. When which address of the main memory 112 is to be read for the first time is determined by the processing result in the processor core unit 110, the prefetch control unit 109 cannot specify the prefetch address in advance. For this reason,
A main memory 112 read instruction is defined in the instruction set of the processor core unit 110, and necessary data can be read from the processor core unit 110 as well. The outline of the read operation of the main memory 112 from the processor core unit 110 will be described.

First, by issuing a read command, a request for reading the main memory 112 is issued from the processor core unit 110 to the bus control unit 111. When the bus control unit 111 receives a read request from the processor core unit via the control bus 128, the prefetch control circuit 1 in the same processed data processing circuit 108
09, and the processor core unit 1 described later.
The bus use permission is given prior to the writing from 10. When the processor core unit 110 receives the bus use permission from the bus control unit 111, the processor core unit 110 sends a read address to the address bus 127 and a read instruction to the control bus 128, and sends the read instruction to the bus control unit 111. Read out. The read data is received by the processor core unit 110 via the data bus 126. In the reading by this method, until the data is read from the main memory 112, the next instruction of the processor core unit 110 is in the processing waiting state, which causes the performance deterioration. Therefore, as described above, the bus request permission is given to the read request of the main memory 112 from the processor core unit 110 in preference to the read from the prefetch control circuit 109 and the write from the processor core unit 110.

Next, an outline of a write operation in which the processor core unit 110 writes data to the main memory 112 will be described. Processor core unit 1 for write data
Reference numeral 10 gives a write instruction by a program instruction. The write instruction is once registered in the queuing buffer in the processor core unit 110, and a write processing request signal for the data registered in the queuing buffer is transmitted when either of the following two cases occurs. First, when the prefetch control unit 109 issues a dedicated instruction afin which means the end of prefetch address calculation. Secondly, when the dedicated instruction fin, which means the end of processing in the processor core unit 110 for the buffer memory 105 in state 3, is issued. A write request for the queuing buffer is issued when either of the above two states is entered. The bus control unit 111 performs bus arbitration, and when the processor core unit 110 receives the bus use permission via the control bus 128, the write address is output to the address bus 127 and the write data is output to the data bus 126. This is written in the main memory 112.

The details of the prefetch control unit 109 will be described below mainly with reference to FIG. As described above, the prefetch control unit 109 is the preprocessor unit 50.
0 and a memory access unit 501. The preprocessor unit 500 includes an instruction memory 590, an instruction decoder 591, an arithmetic processing / execution control unit 592, and a work memory 5.
93, CAM 594, prefetch address memory 59
5, a common bus 522 is provided. A program for prefetching is downloaded from the external CPU bus 129 and stored in the instruction memory 590. Instruction decoder 59
Reference numeral 1 interprets an instruction read from the instruction memory and outputs a control signal corresponding to the instruction to peripheral components. In response to an instruction from the instruction decoder 591, the arithmetic processing / execution control unit 592 uses an internal arithmetic unit to store data stored in various storage devices such as an internal register (not shown), work memory 593, and CAM 594. Then, arithmetic logic operation processing is performed between them, the processing is stored again in the various storage devices, and the program branch processing is executed.

In the program processing, the CAM 594 is used in addition to the work memory 593 which is generally used. The CAM 594 has a search function in addition to the read and write functions that are the usual memory functions. It gives a search key to check whether or not data matching the search key is written in the memory element. Further, when the matching data is written, the memory element has a function of outputting the address at which the data is written at the same time. The prefetch address calculated by the arithmetic processing / execution control unit 592 is written in the prefetch address memory 595 having the CAM structure, but the search function cannot be used from the program instruction of the prefetch control unit 109 and is used as a write-only memory.

The memory access unit 501 includes a prefetch access control unit 596 and a prefetch memory (A side) 5.
97, a prefetch memory (B side) 598. The A side and the B side of the prefetch memory are in a write mode in which prefetch data regarding the processed data of the buffer memory 105 in the state 2 is written and the written data is in the state. The reference mode referred to by the processor core unit 110 for processing the data to be processed in the buffer memory 105 that has moved to 3 is alternately repeated. The prefetch access control unit 596 manages the transition of this mode. The prefetch access control unit 596 reads the prefetch address memory 595, issues a main memory read request and a read address to the bus control unit 111, and outputs the read data to the A side 5 of the prefetch memory.
97, or writing to the B side 598 is controlled.

Details of the operation of the prefetch control unit 109 will be described below. The preprocessor unit 500 is inactive until the processed data transits to the state 2. From the buffer memory state control unit 107 to the signal line 524
When the notification that the data to be processed stored in the buffer memory 105 has transited to the state 2 is received via (= signal line 122), the arithmetic processing / execution control unit 592 starts the execution of the prefetch address calculation program. . When calculating the prefetch address, various storage resources (the buffer memory 105 in the state 2, the registers in the arithmetic processing / execution control unit 592, the work memory 593, the CAM 5 according to the program downloaded from the external CPU bus 129 are used.
94) is used to calculate the prefetch address.
Writing the calculation result to the prefetch address memory 595 is performed by executing a write instruction to the prefetch address memory 595. By this instruction, the instruction decoder 591 outputs a prefetch address memory 595 write instruction (signal line 525), and the prefetch address control unit 596 stores it in the prefetch address memory 595 via the signal line 534.
Furthermore, in the operand of this write instruction, the prefetch address, that is, the read destination address of the main storage memory 112 and the write address to the storage destination memory (prefetch memory A side 597 or prefetch memory B side 598) are designated by immediate values. Two pieces of information are written in the same word of the prefetch address memory 595, such as 602 (read destination address) and 601 (storage destination address) in FIG.

As described above, the calculation of the prefetch address is performed according to the purpose of use of the microprocessor.
It can be arbitrarily set by a user setting program stored in 90. Hereinafter, the calculation example 3 method will be described by taking ATM cell processing as an example.

The first method is an example of a method of calculating the prefetch address when referring to the table provided in the main memory 112 based on the information in the processed data.
This will be described with reference to the schematic diagram of FIG. Fixed-length packet data (ATM cell in ATM communication) represented by ATM communication has a connection ID (identifier) (VPI, VCI in ATM cell) information field in the data. Figure 1
In the first example, the required information for each ID number is fixedly allocated to the table provided in the main memory 112 in the order of the ID number from the head address of the entire table as a fixed-length entry of 2 nth power word.

When the data to be processed transits to state 2, execution of the program is started. First, an instruction to read the word including the ID information field in the buffer memory 105 in the state 2 is executed (FIG. 11, arrow 7a05).
The read word 7a00 is shifted to the left by n bits (arrow 7a06). Further, an instruction for arithmetically adding the table start address 7a01 already stored in the work memory 593 from the external CPU bus 129 is executed (arrow 7a0).
7). 7a02 obtained by the calculation up to this point becomes the start address of the entry of the ID in the table. Then, while executing the arithmetic addition instruction to increment by 1
An instruction for writing a value from 02 to (7a02 + table size of each ID-1) to the prefetch address memory 595 is executed (arrows 7a08 to 7a09). Incidentally, FIG.
In the example shown in FIG. 1, the entry size for each ID number in the table is limited to 2 to the n-th power.
In order to suppress the circuit scale of 0, if a preprocessor has a multiplier, the product of the ID number and the entry size for each ID is calculated to calculate each entry even if it is an entry size other than 2 n. The top address of can be calculated.

Next, the second method will be described with reference to FIG. The second method is also a method of calculating the prefetch address based on the information in the data to be processed, like the first method. However, the difference from the first method is that only the ID that the table entry is using is dynamically changed. Prefetch at the time of memory mapping that allocates a small number of table areas to any connection ID dynamically when the table is used, and releases the table area when it is not used so that other connection IDs can be used. It is an example of an address calculation method. Also in this case, the table entry size of each ID is 2 to the n-th power, and the connection ID is recorded at the address of the CAM 594 corresponding to the assigned entry number (rank). When the processed data transits to the state 2, the program starts executing. First, an instruction to read the word including the ID information field in the buffer memory 105 in the state 2 is executed (FIG. 1).
2, arrow 7b10). A command to search the CAM 594 is executed using the read ID information field in 7b00 as a search key. Address 7 hit by the search
Execute an instruction that shifts b01 left by n bits (arrow 7
b12). The subsequent steps are similar to the first method. That is, the work memory 593 is previously stored in the external CPU bus 129.
The instruction for arithmetically adding the table start address already stored in 7b02 and 7b02 is executed (arrow 7b13), and the arithmetic addition instruction for incrementing one by one is executed (arrows 7b14 to 7b).
15) Execute an instruction to write values from the added value 7b03 to 7b03 + table size of each ID-1 to the prefetch address memory 595.

The third method is an example of calculating a periodic prefetch address using a timer. That is, in the prefetch address calculation in the process having the periodicity of the process execution intervals, such as the periodic arrival monitoring of the failure monitoring cell, the preprocessor unit 500 has a timer built therein so that a specific address calculation program can be executed every fixed period. The prefetch address is obtained by executing it and written in the prefetch address memory 595.

Next, details of the operation of the memory access unit 501 will be described. The main function of the memory access unit 501 is to read the main storage memory 112 according to the prefetch address calculated by the preprocessor unit 500, and to read the prefetch memory A side 597 or the prefetch memory B side 5
98 to store. As a rule in the program description of the preprocessor unit 500, all the prefetch addresses of the main memory 112 necessary for the processor core unit 110 to process the processed data stored in the buffer memory 105 in the state 2 have been calculated. After that, a dedicated instruction afin, which always means the end of prefetch address calculation,
You have to do that. By executing this dedicated instruction afin, a signal notifying the end of prefetch address calculation and a notice of prefetch address calculation completion are output to the signal line 526 to the memory access unit 501 and the processor core unit 110. As a result, the prefetch access control unit 596 of the memory access unit 501
Starts the process for reading the main memory 112.

Upon receiving the prefetch address calculation completion notification from the signal line 526, the prefetch access control unit 596 receives the main memory 11 via the control bus 128.
2 The bus controller 111 is notified of the read request.
The bus control unit 111 performs arbitration with a read / write request from the processor core unit 110 and a request from another processed data processing unit 108. The prefetch access control unit 596 continues to issue the request signal until it receives the bus use permission from the bus control unit 111. When the bus use permission is received via the control bus 128, the prefetch access control unit 596 sends a read address on the address bus 127 and a read instruction signal on the control bus 128 and sends the signal to the bus control unit 111. The storage memory 112 is read.

The read data is sent to the data bus 126.
Via the prefetch memory A side 597 or the prefetch memory B side 598. The prefetch address memory 595 and the main storage memory 11 will be described with reference to FIG.
2. The correlation of data between the prefetch memory A / B planes 597/598 will be described. Prefetch address memory 5
1 word of 95 (for example, FIG. 10, N-3 address of the prefetch address memory 595) is read, and the prefetch address 602 (content 1F00) is stored in the main memory 112.
Read address (arrow 573) required data '1
0FF0C24 'is read and the prefetch memory storage address 601 (content 13) is used as the prefetch memory write address (arrow 532).
Write to address 3 (arrow 583). The request signal is
It is continuously transmitted until read requests for all prefetch addresses calculated by the preprocessor unit 500 are permitted, and the same use is obtained by obtaining bus use permission from the bus control unit 111 until reading of all prefetch addresses is completed. The reading process is continued. One of the A side 597 and the B side 598 of the prefetch memory stores the prefetched data while the other stores the processor core unit 1
The value can be referred to from 10. The switching between the storage state and the reference state is managed by the buffer memory status management unit 107 via the prefetch access control unit 596, and the buffer memory status management unit 107 manages the status 2
The prefetch access control unit 596 is controlled so as to switch between the storage state and the reference state at the timing when the buffer memory 105 of FIG.

Details of the processor core unit 110 will be described below with reference to the block diagram of FIG. 9 showing the configuration of the processor core unit 110. The processor core unit 110 includes an instruction memory 510, an instruction decoder 511, an arithmetic processing / execution control unit 512, a queuing buffer control unit 513, a queuing buffer 514, and a work memory 515. The application processing content and processing procedure relating to the data to be processed stored in the buffer memory 105 in the state 3 are downloaded from the external CPU bus 129 to the instruction memory 510, and the instruction decoder 511 is used for the instruction memory 5
The arithmetic processing / execution control unit 512 outputs a control signal in accordance with the ten instructions, and the arithmetic processing / execution control unit 512 executes programs such as arithmetic logic operation processing and branch processing on data stored in various storage resources according to an instruction from the instruction decoder 511. The processing is performed, and the data in the middle of the processing is temporarily stored in the work memory 515. The write address and the write data are temporarily stored in the queuing buffer 514 until the actual memory access when writing the processing result to the main memory 112. Reading / writing of the queuing buffer 514 is performed by a first-in first-out (FIFO) method, and the queuing buffer controller 513 performs this control.

Until the processed data transits to the state 3, the program processing of the processor core unit 110 is in the execution suspended state. Upon receiving a notification from the buffer memory state control unit 107 that the buffer memory 105 has transited to state 3 via the signal lines 123 to 578, the processor core unit 110 is stored in the buffer memory 105 that has transited to state 3. The execution of the application process is started for the existing processed data. When the application processing program is executed by the processor core unit 110, a value obtained by reading the contents of the main storage memory 112 by the prefetch control unit 109 in advance is referred to by a mechanism described below.

As a result of decoding the instruction read from the instruction memory 510, if it is found that the instruction refers to pre-fetched data, the instruction decoder 511 causes the signal line 5 to read.
The prefetch memory read address and the read instruction are output to the prefetch access control unit 596 of the prefetch control unit 109 via 65 to 130. The prefetch access control unit 596 outputs the prefetch memory address on the signal line 537 by receiving this signal. At this time, the signal of the prefetch address memory search hit notification on the signal line 533 is logic “0” because the prefetch address memory is not executing the search process.
The signal line 537 is connected to the signal line 531 by the switch 599, and the prefetch memory A / B surface 597
/ 598 is input. The reference / setting state of the prefetch memory is managed by the prefetch access control unit 596, and the read instruction signal is output only to the reference state of the prefetch memory read instruction signal lines 535/536. As a result, the memory in the reference state of the prefetch memory is read, and the data is output from the data line 541 or 542. The 2-input selector 599 selects the output of the memory in the reference state according to the signal on the signal line 544, and the read data is passed through the signal line 125 and the data bus 56 in the processor core unit.
Referenced via 4.

Next, the write operation for writing data in the main memory 112 in the processor core unit 110 will be described. Writing to the main storage memory is executed according to a program instruction of the processor core unit 110. The write instruction to the main memory 112 is the instruction memory 510.
When the contents of the instruction are transmitted to the arithmetic processing / execution control unit 512, the arithmetic processing / execution control unit 512 causes the signal line 563 to write the write address of the main memory 112 and internal data. Write data is output to the bus 564 and a write instruction is output to the signal line 562. The queuing buffer control unit 513 controls the writing of the queuing buffer 514, and outputs the write address and the write instruction of the queuing buffer 514 via the signal line 579. As a result, the write address and write data of the main memory 112 output from the arithmetic processing / execution control unit 512 are written in the queuing buffer 514. The address management of the queuing buffer control unit 513 is a FIFO method, and the next main storage memory 112 is added to the address next to the address written by the previous main storage memory write command.
Write the information of the write command.

The write address and the write data of the main memory 112 written in the queuing buffer 513 are held in the queuing buffer 513 until the write processing start trigger is applied, and the main memory 1
The write processing to 12 is suspended. The writing process to the main memory 112 is started when one of the two types of triggers described below occurs. The first is a dedicated instruction afin that means the end of prefetch address calculation.
Is issued. When the instruction decoder 591 of the prefetch control unit 109 decodes the dedicated instruction afin by issuing this instruction and puts a prefetch address calculation completion notice on the signal lines 526 to 124 to notify the queuing buffer control unit 513, the queuing buffer Control unit 51
3 issues a non-priority write request to the bus control unit 111 via the signal line 567 to the control bus 128. The second is the issue of a dedicated instruction fin for notifying the end of the program processing in the processor core unit 110. By issuing this instruction, the instruction decoder 511 decodes the dedicated instruction fin, and issues a processed data processing end notification to the signal line 570. The queuing buffer control unit 513 which has received the processed data processing end notification from the signal line 570
7 to issue a priority write request to the bus control unit 111 via the control bus 128. The priority / non-priority in the write request will be described in the later section.

When any of these two write process start triggers occurs, the queuing buffer control unit 513 notifies the bus control unit 111 of the main memory 112 write request via the signal line 567. The bus control unit 111 arbitrates the request from the read request from the prefetch control unit 109, the read request from the processor core unit 110, and each request from other processed data processing circuits 108. The queuing buffer control unit 513 continues to issue the request signal until it receives the bus use permission from the bus control unit 111. The queuing buffer control unit 513, which has received the bus use permission via the control bus 128, reads the queuing buffer 514, and the write address and the write data which were previously written by the program instruction of the processor core unit 110 and whose execution was reserved. Is read by the FIFO method. According to the read information, write data is output to the data bus 126, a write address is output to the address bus 127, and a write instruction signal is output to the control bus 128. The bus control unit 111 writes the data on the data bus 126 to the address position indicated by the address on the address bus of the main memory 112.
The main memory memory write request is issued until there is no write pending data on the queuing buffer 514, and the same processing is repeated while permitting bus use via the control bus 128.

Next, reading of the main storage memory by the program instruction of the processor core unit 110 will be described.
In the device of the present invention, most of the reading of the main memory 112 is performed in the state 2 by the prefetch operation by the prefetch control unit 109, but the address of the data to be read is specified only from the program processing result in the processor core unit 110. There are cases where you cannot. Therefore, it is necessary to read the main memory 112 by the program instruction from the processor core unit 110. When the read instruction to the main memory 112 is read from the instruction memory 510 and the instruction decoder 511 decodes the read instruction, the main memory read request by the program instruction is issued to the bus control unit 111 via the signal line 567 to the control bus 128. Sent out. The bus control unit 111 arbitrates for this request. When the bus use permission is output through the control bus 128, the instruction decoder 511 outputs the signal line 56.
6, a read address is output, a read instruction is output to the signal line 567, and the bus control unit 111 reads the main memory. The read data is output from the data bus 126 via the data line 582 to the data bus 564 in the processor core unit 110 and referred to by various program instructions.

As described above, access requests are issued from the processed data processing circuit 108 to the main memory 112 from the following three locations. The first is a prefetch access request from the prefetch control unit 109, the second is a write request from the processor core unit 110, and the third is a read request from the processor core unit 110. The bus control unit 111 arbitrates requests from these three locations for each of the processed data processing circuits 108. Details of access arbitration from these three locations in the bus control unit 111 will be described below with reference to the timing charts of FIGS. 3 to 6 and the flowchart of FIG. 7.

The access from the above-mentioned three locations is for reading and writing data required for the program processing in the processor core unit 110. The access timings to the main storage memory 112 from these three locations are not synchronized with the program processing of the processor core unit 110 except for the reading from the processor core unit 110. Generally, in the memory control method in which the read command immediately reads the memory and the write command immediately writes the data, the read / write is performed according to the procedure specified in the program, so that the old data is read accidentally or the old data is written on top of the new data. There is no need to worry about overwriting data. However, the present invention is adopted such that the prefetch control unit 109 reads the main memory 112, or the writing to the main memory 112 in the processor core unit 110 is once stored in the queuing buffer 514 and then written. In the access method that is used, it is necessary to guarantee by some method so that the old data cannot be accidentally read or the old data cannot be written.
This is hereinafter referred to as data consistency guarantee.
Hereinafter, with reference to FIG. 1 and FIG. 3, three inconveniences that occur when access is made from three locations without considering the consistency guarantee will be described.

FIG. 3 shows the prefetch control unit 109 and the processor core unit 11 in the processing of the processed data a and b.
5 is a timing chart showing an example of contention for access to the main memory 112 from 0. In the example of FIG. 3, time T1
At the time when the prefetch control unit 109 finishes calculating the 3-word prefetch addresses apf1 to apf3 required for the processor core unit 110 to process the processed data a later, the instruction decoder 591 notifies the prefetch address calculation end. Decoding the dedicated instruction afin. This dedicated instruction serves as a trigger for prefetch, and the prefetch control unit 109 sends a request signal to the bus control unit 111 via the control bus 128. The bus control unit 111 arbitrates the bus use, and when the prefetch control unit 109 receives the bus use permission via the control bus 128, it sends a read address to the address bus 127 and a read instruction signal to the control bus 128 to control the bus. Part 11
1 reads out the main memory 112. With the above procedure, the prefetch addresses apf1 to apf3 of the main memory 112 are read immediately after time T1. The space between the addresses apf1 and apf2 in FIG. 3 means that the access from the other processed data processing circuit 108 is prioritized and the access to the address apf2 is in a waiting state.

Here, as shown in FIG. 3, at time T2,
The prefetch control unit 109 executes the dedicated instruction pfin that means the end of processing for the data to be processed a, and the status 3
It is assumed that the buffer memory state control unit 107 is notified that it is waiting for the transition to. Buffer memory status controller 1
07 immediately shifts the buffer memory 105 in which the processed data a is stored from the state 2 to the state 3, and the processor core unit 110 starts processing the processed data a.
In the example, at time T3, the processor core unit 110 executes the instruction apf3read that refers to the content of the address apf3 prefetched by the prefetch control unit 109. However, at this time, the prefetch control unit 10
In 9, the reading of the address apf3 is not completed. Therefore, if the processor core unit 110 reads the prefetch memory A side 597 / B side 598 regardless of the state as it is, an incorrect value is read, and the consistency of the data in the main memory cannot be obtained.

The second disadvantage will be described with reference to FIG. At times T4 and T5, the processor core unit 110 writes a write command a for the processed data a.
w1 and aw2 are executed. In addition, at time T6, the prefetch control unit 109 causes the processor core unit 11 to
0 executes the dedicated instruction afin for notifying that the calculation of the prefetch addresses bpf1 to bpf3 of 3 words necessary for processing the data to be processed b has been completed. This dedicated instruction serves as a trigger for prefetching, and the request signal is transmitted via the control bus 128 to the bus control unit 111.
Send to. The bus control unit 111 arbitrates the bus use, and when the prefetch control unit 109 receives the bus use permission via the control bus 128, it sends the read addresses bpf1 to 3 to the address bus 127 and the read instruction signal to the control bus 128. , The bus control unit 111 is the main memory 112
The prefetch addresses bpf1 and bpf2 of are read. Further, at time T7, the processor core unit 110 executes the write command aw3 for the processed data a, and in the example of FIG. 3, the access for writing from the processor core unit 110 to the address aw3 has priority over the access to the address bpf3. And is running. In this way, in parallel with the access for reading from the prefetch control unit 109, the processor core unit 110 is processing the data a to be processed at times T4, T5,
At T7, T8, and T9, awl, aw2, aw3,
A write command is issued to aw4 and aw5, a bus is acquired by bus arbitration in the bus control unit 111, and writing to the main memory 112 is performed.

Here, considering the consistency of the data in the main memory 112, the data at the addresses bpf1 to 3 prefetched for the processing of the processed data b is always one before the processed data b. It is necessary to read the data that reflects the processing result for the processed data a that is the processed data. However, if a write is executed after the prefetch access to the same address as the prefetch address, for example, bp in FIG.
When f3 and aw4 have the same address, when the processed data is processed by the processor core unit 110, the data in which the processing result of the immediately preceding processed data is reflected cannot be used, and the main storage memory 112 cannot be used. The data will be inconsistent.

Next, the third disadvantage will be described with reference to FIG. At time T10 in FIG. 3, the program processing in the processor core unit 110 for the data to be processed a is completed and the dedicated instruction fin is executed, so that the processing for the data to be processed a is completed via the signal lines 578 to 123 in the buffer memory. It is assumed that the state control unit 107 is notified. The buffer memory state control unit 107 immediately sets the buffer memory 105 in which the processed data a is stored to the state 3
To state 4 and the output control circuit 106 outputs the processed data a. Immediately after that, the processed data b
The buffer memory 105 in which is stored transits from state 2 to state 3, the processor core unit 110 starts processing the processed data b, and in the example of FIG. Are read by a program instruction of the processor core unit 110. The address aw5 is an address to which the processor core unit 110 issues a write command as a processing result of the processed data a at T9. Therefore, for example, as shown in the example of FIG. 3, after the reading is performed at time T12,
When the writing is performed at the time T13, the processor core unit 110 cannot process the processed data b by reflecting the processing result of the processed data a, and the data in the main memory 112 cannot be consistent.

In the present invention, the main storage memory 112 is provided with the following three measures against the above-mentioned three types of inconveniences.
Guarantees the consistency of the above data. The three measures will be described below with reference to the timing chart after the measures shown in FIG. 4 corresponding to the timing chart of FIG.

As the first point of the countermeasure, the completion of prefetch access in the prefetch access control unit 569 is set as the transition condition from the state 2 to the state 3. In FIG. 3, the transition timing from the state 2 to the state 3 of the processed data a is the dedicated instruction pf for notifying the end of processing by the prefetch control unit 109 for the processed data a at time T2.
It was run-in. Therefore, the processed data b is in the state 3
Completion of prefetch access to apf1 to apf3 at the time of transition to is not guaranteed. As in the example of FIG. 3, when trying to read the data at the address apf3 that should have been prefetched at time T3, the prefetch access may be incomplete, and the old data may be erroneously read. Therefore, in the present invention, the dedicated instruction pfi for notifying the transition condition of the processed data a from the state 2 to the state 3 in the prefetch control unit 109 is notified.
In addition to the execution of n, the condition for prefetch memory access completion is added, and the transition from the state 2 to the state 3 is made possible when both of these conditions are satisfied. In the example of FIG. 4, the pfin instruction is executed at time T2, but the transition from state 2 to state 3 of the data to be processed a is performed at the time of completion of prefetch access (arrow 301) that occurs thereafter. As a result, the prefetch access is always completed when the processed data a transits to the state 3, and even if the processor core unit 110 performs apf3read referring to apf3 at time T3 immediately after, for example, the main memory. Memory 112 data consistency is guaranteed.

As a second countermeasure, the completion of writing the contents of the queuing buffer 514 to the main memory 112 performed by the queuing buffer control unit 513 is set as the transition condition from state 3 to state 4. In FIG. 3, the timing at which the processed data a transits from the state 3 to the state 4 is at the time of execution of the dedicated instruction fin for notifying the processing end of the processed data a at the time T10 in the processor core unit 110.
In this method, the completion of writing the processing result to the processed data a in the processor core unit 110 is not guaranteed when the processed data b transits to the state 3. As shown in FIG. 3, when attempting to read aw5 at time T11, there may be a case where the processing result writing of the processed data a has not been completed. In the present invention, the condition for transition of the processed data a from the state 3 to the state 4 is set as the condition for executing the dedicated instruction fin for notifying the end of processing of the processor core unit 110 and the condition for the completion of writing from the processor core unit 110. In addition, when both of these conditions are satisfied, the processed data a changes from the state 3 to the state 4
I made a transition to. Therefore, the processor core unit 11
When 0 starts processing the new processed data b, the completion of the write processing of the pre-processed data a is guaranteed.

The third countermeasure is dynamic management of the bus arbitration algorithm and address monitoring at the time of writing to the main memory. As described above as the second inconvenience, in the example of FIG. 3, the prefetch address bpf of the new processed data b is used.
3 and the write address aw4 of the preprocessed data a are the same address, the data of the prefetch address bpf3 referred to when the processed data b is processed by the processor core unit 110 was prefetched at time T14. The data was before writing to the write address aw4. Originally, it is necessary to refer to the data written at the time T15 as the processing result for the data to be processed a, but in this case, the old data is referred to and processed. Therefore, in the present invention, the bus control unit 111 dynamically manages the bus arbitration algorithm as described below, and the write address is monitored during the write processing from the processor core unit 110. Updating the prefetch memory 597/598 in synchronization with the storage memory 112 ensures the consistency of the data in the main storage memory 112.

That is, in order to prevent the writing of the data to be processed and the prefetching of the next data to be processed from intermingling, the bus control unit 111 includes the prefetch control unit 1
In the arbitration between the prefetch request from 09 and the data write request from the processor core unit 110, once the bus use permission is issued for the prefetch access (read) from the prefetch control unit 109, it is reserved in the prefetch address memory 595. Until the access of all words is completed, it is processed as a request having a higher priority than the write request from the processor core unit 110. On the contrary, once the processor core unit 110
When a bus use permission is issued in response to a write request from the main storage memory 1 from the queuing buffer 514.
Until the writing to 12 is completed, it is processed as a request having a higher priority than the prefetch access.

Further, in the present invention, the processor core unit 11
It has a function to monitor the write address from 0. That is, when the prefetch for the next processed data is prioritized by the bus arbitration algorithm, during the write processing of the processed data from the processor core unit 110, the processing address of the next processed data is included in the write address. If there is a matching address as a result of the search, the main memory 112 is written and at the same time the data of the corresponding address is By updating the read and stored prefetch memory (A side / B side) 597/598 with the write data, in the data processing of the processed data in the processor core unit 110, the processed data processing results up to immediately before are processed. Enabled to refer to the reflected data. This mechanism is activated only when prefetch access is preferentially processed. When the write process is preferentially processed by the arbitration algorithm, the data in the main memory 112 after the write is Since it is prefetched, such address monitoring / updating process becomes unnecessary.

The details of the operation when the above-mentioned two points are taken into consideration will be described below. This operation is a dedicated instruction a
Since it depends on whether fin (issued from the prefetch control unit 109 and triggering the start of access to the main memory 112) or dedicated instruction fin (issued from the processor core unit 110) is issued first, these 2 The two cases will be explained separately.

The operation when the dedicated instruction afin arrives first will be described with reference to FIGS. 4, 8 and 9 and then the bus arbitration algorithm in this case will be described with reference to FIG. At times T4 and T5 in FIG. 4, a write command for the main memory 112 is issued from the processor core unit 110 (aw1, aw2), but its execution is suspended until the start trigger occurs. The operation at this time will be described with reference to FIG.
As a result of decoding by No. 1, when it is found that the instruction is a write instruction to the main memory 112, the instruction decoder 511 transmits the result to the arithmetic processing / execution control unit 512 via the signal line 561. The arithmetic processing / execution control unit 512 outputs the main memory write address to the queuing buffer 514 via the signal line 563 and the main memory write data to the queuing buffer 514 via the internal bus 564.

At the same time, a write instruction is output to the queuing buffer 514 and the queuing buffer controller 513 via the signal line 562. As a result, the queuing buffer 514 stores a set of write address and write data for the main memory 112. The queuing buffer control unit 513 uses the queuing buffer 514.
And the signal line 56 from the arithmetic processing / execution control unit 512.
According to the write instruction output via 2, the number of write instructions of the main memory 112 during the processing of the processed data is counted. Next, in the example of FIG. 4, at time T6, the prefetch control unit 109 executes the dedicated instruction afin for notifying that the prefetch address calculation for the processed data b is completed. This instruction triggers the start of prefetch access, is transmitted from the instruction decoder 591 to the prefetch access control unit 596 via the signal line 526, and the prefetch access control unit 596 sends the prefetch request to the bus control unit 1 via the signal line 538.
Output to 11.

Dedicated instruction a as at times T4 and T5 in FIG.
When the main memory memory 112 write instruction (aw1, aw2) is executed in the processor core unit 110 before executing fin, the non-priority write request is also issued from the queue-in buffer control unit 513 at the same timing as the prefetch request. 567 via the bus control unit 111
Is output to. The mechanism for issuing the non-priority write request at this time will be described with reference to FIG. The dedicated instruction afin is transmitted to the queuing buffer control unit 513 of the processor core unit 110 via the signal lines 526 to 124, and the queuing buffer control unit 513 knows that the dedicated instruction afin has been executed. It is known that the write command has already been issued by the processor core unit 110 by this time because the queuing buffer control unit 513 counts the number of write command issuances based on the information from the signal line 562. Immediately a non-priority write request is issued. Further, as in the case shown in aw1 and aw2 (time T4 and T5) in FIG. 5, when the write instruction is issued after the dedicated instruction afin (time T6) that triggers the write start is executed, the time T4 When the first write command (aw1) is issued at, the signal line 567 is immediately issued.
A non-priority write request is issued via.

Next, as to how the prefetch request and non-priority write request signals thus received by the bus control unit 111 are adjusted by the bus control unit 111, the bus arbitration of the bus control unit 111 of FIG. 7 is performed. This will be described with reference to the flowchart showing the algorithm.
As in the case of FIG. 4, when the dedicated instruction afin is issued (time T
In 6), if the write command has already been issued (time T4, T5), the bus control unit 111 receives the prefetch request and the non-priority write request at the same timing as described above. Each step of FIG. 7 in this case will be described step by step. Referring to FIG. 7, the bus control unit 1
In the initial state, 11 turns off the two inhibit signals of the priority write inhibit signal and the prefetch inhibit signal (steps 401, 402) and waits for the arrival of each request. That is, first, it is checked whether or not the preferential write request has been received (step 403).
At 04, since the prefetch inhibit signal is turned off at step 402, it passes through step 404 and moves to step 407 to check whether or not the prefetch request is received. Since the prefetch request has been received and the prefetch inhibit signal is off, the process moves from step 409 to step 410, and the priority write inhibit signal is turned on to prevent write access. Next, it is assumed here that the read request is not issued from the processor core unit 110. Under this assumption, the process goes from step 410 to step 411 to step 413. However, since the dedicated instruction afin comes first, there is no preferential write request, and the process proceeds to step 416, but there is a prefetch request, and there is a prefetch inhibit. Since it is off, steps 417 to 418
Then, the bus use permission for prefetch is output.
As a result, the prefetch access is executed once. Then, the process returns to step 403, and the next access arbitration is performed.

As described above, once the bus use permission for the prefetch is issued, as long as the prefetch request continues, that is, prior to the prefetch until the access of all the words reserved in the prefetch address memory 595 is completed. The bus permission is issued. That is, in the case of FIG. 4, the dedicated instruction af at time T6
3 from address bpf1 to bpf3 triggered by in
The word prefetch is executed continuously. this is,
The prefetch control unit 109 sets 3 for the processed data b.
Means that the prefetch address of a word has been calculated. Therefore, in step 410, the priority write inhibit signal is turned on, and the processor core unit 110 causes the dedicated instruction fi to be turned on during the prefetch access.
Even when n is issued, the inhibit signal is checked in step 414 so that the prefetch access is preferentially processed.

When the prefetch access processing is completed,
That is, when the prefetch of all the addresses recorded in the prefetch address memory 595 is completed, the prefetch access control unit 596 stops the output of the prefetch request. Hereinafter, the arbitration algorithm in the bus control unit 111 when the prefetch request is not output will be described. In FIG. 7, step 403, if the preferential write request has not been received, control proceeds to step 407 via steps 403 and 404.
Since the prefetch request has disappeared, the priority write inhibit signal is turned off at step 408. Next, it is assumed that the read request is not issued from the processor core unit 110 here as well. That is, the step 411 goes to “none” and the process moves to the step 413, and the priority write request is “none”, and the step 4
The prefetch request of 16 is also "none", and step 4
When the non-priority request of 19 is “present”, the bus use permission for the non-priority write of step 420 is executed, and the process returns to step 403. In this manner, the bus use permission for the non-priority write is issued consecutively with aw1 and aw2 (since the prefetch of the next processed data is completed).

In the case of FIG. 4, addresses aw1 and aw2
There is a waiting time of 3 times after writing to the. This is because a request with a high priority has arrived at the bus control unit 111 from the other processed data processing circuit 108. In FIG. 4, at time T10, the processor core unit 110
At this time, the dedicated instruction fin is issued, and the writing process is restarted immediately after that, and writing is performed at the addresses aw3 to aw5. This is because the priority write request is issued by the dedicated instruction fin as described above, so that the write request from the processed data processing circuit 108 has a higher priority and is processed preferentially by the bus control unit 111. This is because This is because the next processed data waits for processing until the writing from the processor core unit 110 is completed as a transition condition from the state 2 to the state 3 of the buffer memory 105, so the priority is high after the dedicated instruction fin is issued. This is an arbitration algorithm for promptly completing the writing process.

By the way, the prefetch access from the prefetch control unit 109 is preferentially processed over the writing from the processor core unit 110, so that the consistency of the main memory 112 is not maintained. As described above, the write address from the processor core unit 110 is monitored, and if there is a match in the prefetch address for the next data to be processed, the write data is set in the prefetch memory (A side / B side) 597. / 59
Writing to 8 guarantees consistency.

The operation of the consistency guarantee mechanism will be described below with reference to FIGS. 4, 8, 9 and 10. As described above, when the prefetch access is completed, the bus control unit 111 permits the non-priority write request from the processor core unit 110. This permission signal is transmitted to the queuing buffer control unit 513 via the signal line 567,
The queuing buffer read instruction signal is output on the signal line 579, the read address of the queuing buffer is output on the address line 584, and the write address and write data from the queuing buffer 514 to the main memory 112 are written on the signal line 580. And 581 are output to the address bus 127 and the data bus 126, respectively. At this time, in order to guarantee the consistency of the data in the main memory 112, the prefetch address memory 595 is searched in parallel with the write operation to the main memory 112. That is, the write addresses output to the signal line 580 are simultaneously used as search keys in the signal lines 572 to 130.
Is supplied to the prefetch address memory 595 through
The queuing buffer control unit 513 outputs a search instruction signal to the prefetch address memory 595 via the signal lines 571 to 130, and the CAM search of the prefetch address memory 595 is performed.

As a result of the search, if there is no matching address in the prefetch address memory 595, it means writing of data unrelated to the prefetch data, and no special processing is performed. As a result of the search, when there is a matching address in the prefetch address memory 595, the write data is set in the prefetch memory (A side /
The write data to the main memory 112 is written at the address where the corresponding data of (B side) 597/598 is stored. The operation at this time will be described. As a result of the search, if there is a matching address in the prefetch address memory 595, the prefetch access control unit 596 knows this matching via the signal line 533, and the signal line 528 /
529 outputs a write instruction to the prefetch memory (A side / B side) 597/598 in which the write data is set. The write address and the write data at that time are the search address of the signal line 532 from the prefetch address memory 595 and the write data because the two 2-input selectors 599 are switched to the B input selection by the search match signal of the signal line 533. Are signal lines 581 to 583 to 1 from the queuing buffer 514.
It becomes the main memory memory write data supplied via 30.

The above operation will be described with reference to FIG. 6 words are prefetched in some processed data,
It is assumed that the prefetch address memory 595 stores prefetch reserved information from addresses N-5 to N. In each entry, prefetched address information 602 of the main memory 112 and storage destination address information 601 of prefetched data are stored in one word. During the writing process to the address 1F00 of the main memory 112, the prefetch address memory 595 is CAM-searched using this address data 1F00 as a search key, and the data matching the address N-3 is found. When the matching data is found, the matching address (N in the example of FIG. 10) of the prefetch address memory 595 is detected.
(Address -3), the value of the 601 field (address 13 in the example of FIG. 10) in the prefetch memory (Side A / B)
The write data to the main memory 112 (1 in the example of FIG. 10) is used as the write address to the surface 597/598.
0FF0C24) is written.

Next, the operation in the case of the first-come-first-served fin instruction will be described with reference to FIGS. 6, 8 and 9.
The output timing and internal operation of the 2-access request will be described, and then the bus arbitration algorithm will be described with reference to FIG. 7. FIG. 6 shows an example in which there is a slight gap in the arrival interval of the processed data. In such cases,
The processing of the processed data a precedes the processor core unit 110.
The dedicated instruction fin from is a trigger for writing the processing result of the processed data a in the processor core unit 110 (time T
7). The operation at this time will be described with reference to FIG. As a result of decoding the instruction read from the instruction memory 510 by the instruction decoder 511, if the instruction decoder 511 finds that it is the dedicated instruction fin, the instruction decoder 511 sends the control bus 128 via the signal line 567.
The priority write request is output to. When this request is arbitrated by the bus control unit 111 and a bus use permission signal is output from the bus control unit 111 and received via the control bus 128 and the signal line 567, the processor core unit 110
Starts the writing process. The writing process at this time is
Similar to the writing process triggered by the dedicated instruction afin of the prefetch control unit 109, the queuing buffer control unit 513 reads the write address and the write data from the queuing buffer 514 for processing, and the search process of the prefetch address memory 595. The difference is that is not performed.

Next, how the bus control unit 111 arbitrates with respect to the priority write request signal received will be described by following each step shown in FIG. At time T6 in FIG. 6, since the dedicated instruction afin for the next non-processed data b has not yet been issued, the main memory bus is empty and the two inhibit signals are off. Since the priority write request is checked in step 403 and the priority write request is received, the process proceeds to step 406 through steps 403 and 405, and the prefetch inhibit signal is turned on. Since I have not received the prefetch request in step 407,
Step 408 is bypassed. Here again, it is assumed that the read request is not issued from the processor core unit 110. Steps 411 to 413, 4
Moving to 14, 415, the bus use permission is output to the priority write request. After that, the process returns to step 403 and the priority writing is continued.

At time T8 in FIG. 6, the dedicated instruction afin is issued from the prefetch control unit 109. However, since the priority write request is always checked before the prefetch request, and the priority write request continues to be issued until the writing of the address aw6 is completed, the prefetch inhibit cannot be turned off. Is processed first.

When the writing is completed up to the address aw6, the priority write request is released, the process proceeds from step 403 to step 404 in FIG. 7, and the prefetch inhibit signal is turned off. When the writing of the address aw6 is completed, the prefetch control unit 109 has already executed the dedicated instruction af.
Since in has been issued, the prefetch request has been issued and the prefetch inhibit signal is off (steps 407 and 409), so that the priority write inhibit signal is turned on at step 410. Next, again, it is assumed that the read request from the processor core unit 110 has not been issued. From step 411 to steps 413, 416, 417, 418, bus use permission is issued for prefetch access.

The bus arbitration algorithms when there is no read request from the processor core unit 110 have been described above. However, as described above, direct read of the main memory 112 from the processor core unit 110 completes data read. Until then, the next instruction of the processor core unit 110 is put in a processing wait state, which causes performance degradation. Therefore, the presence / absence of a read request from the processor core unit 110 is determined in steps 413 and 416.
And 419, the priority write request, the prefetch request, and the non-priority write request are prioritized and checked in step 411, and if "Yes", the bus use permission is unconditionally given (step 412).

As described above, the bus use arbitration for writing to the main memory 112 is as follows: 1) When the processing of the data to be processed ends prior to the calculation of the prefetch address of the next data to be processed, it is dedicated. The instruction fin is executed, the write data in the queuing buffer 514 is continuously processed in priority to the prefetch request by the priority write request, and the prefetch is performed thereafter, so that the latest data is prefetched and referred to by the processor core unit 110. 2) When the calculation of the prefetch address of the next processed data is completed prior to the processing of the processed data, the dedicated instruction afin is executed first, and the prefetch access is preferentially executed. At the time of non-priority or preferential writing to the memory 112, if the data of the write address has been prefetched, the prefetch data is updated at the same time, so that the processor core unit 110 can similarly refer to the latest data.

The embodiment of the present invention in which the prefetch control unit 109 is solely responsible for prefetching data in the main memory 112 has been described above. As described above, the object of the present invention is to prefetch the data in the main storage memory 112 necessary for the program processing in the processor core unit 110 one state before, and
12 To shorten the access time. The specification of the prefetch address in the prefetch control unit 109 is determined by referring to the processed data in the state 2 or the timer function,
Processing results in the processor core unit 110 and main memory 1
The prefetch address was specified without referring to the contents of 12. By applying this idea, the prefetch control unit 109 can be used not only for prefetching data but also for a preprocessor of another processor core unit 110. That is, regarding the processing in which the processing contents are specified by the processed data reference or the timer function in the state 2,
By preparing an instruction set suitable for processing the processed data in the preprocessor unit 500, the preprocessor unit 50
0, preprocessing is performed, and the processing result is processed by the processor core unit 110 by referring to the preprocessing result of the preprocessor unit 500 by newly providing a storage resource of a two-side configuration similar to the prefetch memory A side 597 or B side 598. It is possible to realize distributed processing, and it is possible to improve the overall processing through-top. As the above memory resource, there are two sides, side A and side B.
New pre-process memory consisting of
The control unit 109 controls each of the connected buffer memories.
Mainly identified as necessary for the required processing of the processed data of
The data in the storage memory 112 is transferred to the A side of the prefetch memory.
Prefetch by alternately using 597 and B-side 598
Of the required processing of each processed data,
No need to write data to main memory 112
Execute part or all of the processing, and
Record by alternately using the A side and B side of the process memory,
The processor core unit 110 is the A side of the prefetch memory.
597 and B side 598 of the prefetch control unit 109
Unused side and A side of the above preprocess memory
Not used by the prefetch control unit 109 of the B side and the B side
Perform other processing of the required processing by referring to the surface .

[0086]

As described above, according to the present invention, (1) the program execution waiting time is reduced. (2) The waiting time for memory access seen from the program instruction is hidden. (3) An inexpensive memory element can be used. (4) The main memory can be utilized as the data communication space between the processed data processing circuits. (5) The guaranteed performance value of the processor is improved. (6) The effective data transfer capability of the main memory is improved.

As to the effect (1), the prefetch control unit 109 prefetches the main storage memory, so that most of the main storage memory data required for the program processing in the processor core unit 110 is stored in advance in the high-speed RAM inside the chip. Is stored. Further, in writing, the next instruction can be executed without waiting for the actual writing to the main memory 112. As a result, it is possible to reduce the program execution waiting time caused by the main memory access wait. As for the effect (2), the processor core unit 11
The access other than the read access of the main memory 112 by the program instruction of 0 is executed by the processor core unit 11
It can be performed asynchronously with 0 program processing. Asynchronous here means that the pre-fetched data is read for reading, and the main memory 1 is actually written for writing.
This means that the next instruction is executed without waiting for the write processing to 12. Therefore, in the memory element used for the main memory, the program execution wait does not occur even if the wait time (latency) from the access instruction to the data read is long.

As for the effect (3), a memory device having a fast access time is used for an application program which normally has a problem of main memory access latency in order to reduce the program wait time at the time of a cache miss. Although necessary, the present invention has an effect (2)
As described above, even if a memory element having a large access time or a long latency is used, it does not directly lead to an increase in the program execution wait time, so that an inexpensive memory element can be used for the main memory. As for the effect (4), since the plurality of processed data processing circuits 108 share one main storage memory 112 and its memory bus,
The main memory 112 is used as it is for the processed data processing circuit 1
08 has a function as a data communication space.

As for the effect (5), the data on the main memory 112 read by the prefetch is:
If the program of the processor core unit 110 guarantees a reference without a wait time and knows how many words are prefetched in advance, the main memory access improvement effect by prefetching can be quantified and the guaranteed performance value of the processor can be calculated. Can be improved.

As for the effect (6), in the synchronous memory device, when switching from the read access to the write access, it is usually necessary to temporarily suspend the memory device after the read operation and then perform the write operation. -In the case of a memory device called a "register" in which registers exist before and after the memory core, a 2-clock pause period is required. Therefore, in order to effectively draw out the bandwidth of the bus, it is necessary to reduce the number of switching operations for reading and then writing. In the present invention, the bus control unit 111
As a result, the number of switching from read to write is reduced by arbitrating so that either the prefetch access in the prefetch control unit 109 or the processing result write access in the processor core unit 110 is continuously preferentially processed. The effective data transfer capability of 112 is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main memory access device of the present invention.

FIG. 2 is an explanatory diagram showing a state transition of the buffer memory in FIG.

3 is a timing chart showing an example of a relationship between a program instruction and memory access timing when data to be processed successively arrives in the device of FIG. 1 without considering data consistency.

FIG. 4 is a timing chart showing an example of a relationship between program instructions and memory access timing when data to be processed successively arrives in the device of FIG. 1 in consideration of data consistency.

5 is a timing chart showing another example of the relationship between a program instruction and memory access timing when data to be processed successively arrives in the device of FIG. 1 in consideration of data consistency.

FIG. 6 is a timing chart showing an example of the relationship between program instructions and memory access timing when data to be processed arrives intermittently in the device of FIG. 1 in consideration of data consistency.

7 is a flow chart showing an arbitration algorithm of the bus control unit of FIG. 1. FIG.

8 is a block diagram showing a detailed configuration of a prefetch control unit in FIG. 1. FIG.

9 is a block diagram showing a detailed configuration of a processor core unit in FIG. 1. FIG.

10 is a schematic diagram showing the configuration of the prefetch address memory of FIG.

FIG. 11 is a schematic diagram showing an example of prefetch address calculation.

FIG. 12 is a schematic diagram showing another example of prefetch address calculation.

[Explanation of symbols]

101 input port 102 output ports 103 I / O buffer memory circuit 104 Input control circuit 105 buffer memory 106 Output control circuit 107 buffer memory state control unit 108 processed data processing circuit 109 prefetch control unit 110 processor core 111 Bus control unit 112 main memory 120-125, 130, 520-584 signal lines 126 data bus 127 address bus 128 control bus 129 External CPU bus 500 preprocessor section 501 memory access unit 510, 590 instruction memory 511 and 591 instruction decoder 512, 592 Operation processing / execution control unit 513 queuing buffer controller 514 queuing buffer 515, 593 Work memory 594 CAM 595 prefetch address memory 597 Prefetch memory (A side) 598 Prefetch memory (B side) 599 2-input selector

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naoki Shimura 1-403, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa NEC Telecom Systems Stock Company In-house (72) Hiroki Teramoto 1-chome, Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa 403 Japan Electric Telecom System Stock Association In-house (56) Reference JP 10-106253 (JP, A) JP 4-56548 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB) Name) G06F 12/00 G06F 9/38

Claims (11)

(57) [Claims] 1. A bus control unit for arbitrating bus usage for an access request to a main memory which is commonly accessed via a memory bus by an arbitrary number of processed data processing circuits. And the arbitrary number
A microprocessor provided with an internal memory provided inside each of the processed data processing circuits, the plurality of processed data processing circuits each include a plurality of buffer memories and the processed data. From the input control circuit for writing the processed data sequentially input to the data processing circuit to the connected one of the plurality of buffer memories, and the processed data written to the connected one of the plurality of buffer memories, A prefetch control unit that prefetches data in the main memory memory, which is specified as being necessary for the required processing of the processed data, into the internal memory; Regarding the data, the main record prefetched into the internal memory by the prefetch control unit for the processed data. A processor core unit that performs the required processing using data in the memory; an output control circuit that outputs to-be-processed data written in one of the plurality of buffer memories connected to the output control circuit; The processed data processing is performed by sequentially connecting each of the plurality of buffer memories to each of the prefetch control unit, the processor core unit, and the output control circuit in consideration of respective processing states performed asynchronously. A microprocessor provided with a prefetch mechanism for a main memory, comprising a buffer memory state management unit for controlling pipeline processing of processed data sequentially input to a circuit. 2. A state in which the buffer memory state management unit sets a state of waiting for connection to the input control circuit for the plurality of buffer memories to state 0, and is connected to the input control circuit and has data to be processed written therein. Is set to state 1, and the state of waiting for connection to the prefetch control unit after completion of writing of the processed data in the input control circuit is set to state 1.5,
State 2 connected to the prefetch control unit
When the state connected to the processor core section is set to state 3 and the state connected to the output control circuit to output the processed data is set to state 4, the preceding buffer memory finishes state 1, When the processed data input to the input control circuit becomes 1 unit or more, one of the buffer memories in the state 0 is transited to the state 1, and the buffer memory which has completed the state 1 is in the state 1.5. It is added to the end of the buffer memory queue, and when the preceding buffer memory finishes state 2, the head of the buffer memory queue in state 1.5 is placed in state 2
The buffer memory in the state 2 is transited to the state 3 on condition that the preceding buffer memory finishes the state 3 and the prefetch of the specified data in the main memory into the internal memory is completed. Then, the buffer memory in the state 3 is transited to the state 4 on condition that the preceding buffer memory finishes the state 4 and the data writing to the main memory generated by the required processing is completed, The microprocessor having a prefetch mechanism of the main memory according to claim 1, wherein the buffer memory which has completed the above is controlled to be transferred to the state 0. 3. Each of the processed data is packet data having a connection ID (identifier) corresponding to the required processing, and the prefetch control unit is a connection I of packet data of a connected buffer memory.
From the value of D, the head address of the entry of the table that describes the prefetch address of the data in the main memory specified to be necessary for the corresponding processing in connection ID order is calculated, and this table is referenced,
2. The microprocessor having a main memory prefetch mechanism according to claim 1, wherein a prefetch address of the data in the main memory specified to be required for the required processing of the packet data is acquired. 4. Each of the processed data is packet data having a connection ID (identifier) corresponding to the required processing, and the prefetch control unit is a connection I of packet data of a connected buffer memory.
An entry of a table in which a prefetch address of data in the main memory specified from the value of D by using a CAM (associative search memory) is specified as being necessary for required processing corresponding to each connection ID in use. 2. The prefetch address of the data of the main memory specified to be necessary for the required processing of the packet data is acquired by searching the head address of the packet and referring to this table. Microprocessor with prefetch mechanism for main memory. 5. When the data in the main memory specified as necessary for the required processing of the processed data is specified by the processing cycle of the processed data,
The microprocessor having a prefetch mechanism for a main memory according to claim 1, wherein the prefetch control unit calculates a prefetch address of data in the main memory from a count value of an internal timer. 6. The internal memory has a prefetch memory and a queuing buffer each of which is composed of two sides, A side and B side, and the prefetch control unit is the required processing of the processed data of each of the connected buffer memories. The data of the main memory specified as necessary for the A side and the B side.
Prefetch by alternately using planes, the processor core unit performs the required processing by referring to a plane not used by the prefetch control unit of the planes A and B, and By storing the write data to the main storage memory in the queuing buffer, the usage state of the memory bus is excluded except for the reading of the data of the main storage memory which is required to be referenced for the first time due to the result of the required processing. The microprocessor with a prefetch mechanism for a main memory according to claim 1, wherein the required processing is executed without being affected. 7. The prefetch control unit has a prefetch address memory configured by a CAM, and is a read destination of data in the main memory specified as necessary for the required processing of the processed data. A prefetch address and a preprocessor section that calculates a storage destination address of the prefetch memory in which this data should be stored and stores the prefetch address in the same address of this prefetch address memory; After the completion of the calculation of the storage destination address, a prefetch request is issued to the bus control unit, the use permission of the memory bus is obtained, the data of the main memory is read from the prefetch address, and the storage destination of the prefetch memory is read. Store at address A memory access unit that executes a process for all prefetch addresses stored in the prefetch address memory, wherein the processor core unit executes the required process for the processed data by the preprocessor unit. When the prefetch address of the processed data next to the processed data ends prior to the end of the calculation, a priority write request is issued to the bus control unit to obtain permission to use the memory bus and the queuing is performed. The process of writing the write data to the main memory stored in the buffer to the main memory is executed for all the data stored in the queuing buffer, and the calculation of the prefetch address of the next processed data is completed. If the processing is completed prior to the required processing, the required processing Until the completion, the non-priority write request is issued to the bus control unit, and after the required processing is completed, the priority write request is issued to the bus control unit, and the queuing buffer is obtained with the permission to use the memory bus. At the same time that the write data stored in the main memory is written to the main memory, the prefetch address memory is searched through the memory access unit, and the address matching the write address to the main memory is searched. If the data has been prefetched, the process of updating the prefetch memory with the write data to the main memory using the storage destination address obtained from the search result is performed for all the data accumulated in the queuing buffer. A queuing buffer control unit for executing, the bus control unit When the required processing of the processed data of the processor core unit is completed prior to the end of the calculation of the prefetch address of the next processed data, the priority write request is given priority over the prefetch request. Give permission to use the bus,
When the end of the calculation of the prefetch address of the next processed data is completed prior to the required processing of the processed data of the processor core unit, the bus is transferred to the prefetch request with priority over the priority write request. 7. A microprocessor provided with a prefetch mechanism for a main memory according to claim 6, wherein bus utilization arbitration for giving permission of use is performed. 8. The processor core unit has an instruction memory, and the required processing is executed by a user through an external CPU bus in accordance with a program stored in the instruction memory. Microprocessor with prefetch mechanism for main memory. 9. The prefetch control unit has an instruction memory, and a prefetch address of the data in the main memory which is specified as necessary for the required processing is stored in the instruction memory by a user via an external CPU bus. The microprocessor provided with the prefetch mechanism of the main memory according to claim 1, wherein the microprocessor is calculated in accordance with the executed program. 10. The prefetch control unit has an instruction memory and a work memory, and the data of the main memory memory specified as necessary for the required processing is stored in the instruction memory by a user via an external CPU bus. The prefetch mechanism for the main memory according to claim 3 or 4, wherein the prefetch mechanism is calculated by referring to the table expanded in the work memory by the user via the external CPU bus in accordance with the executed program. Equipped microprocessor. 11. The internal memory further includes A side and B side.
The prefetch control unit has a preprocess memory having two surfaces, and the prefetch control unit prefetches data in the main memory specified to be required for the required processing of each processed data in the connected buffer memory. Prefetch by alternately using the A side and the B side of the memory, and execute some or all of the required processing of the respective processed data that does not require data writing to the main memory. , The execution result
The A surface and B surface of the reprocessing memory recorded using alternately the processor core section, the prefetch memory A
Other processing of the required processing with reference to the surface not used by the prefetch control unit among the surfaces and the B surface and the surface not used by the prefetch control unit among the surfaces A and B of the preprocess memory 7. A microprocessor having a main memory prefetch mechanism according to claim 6, wherein