JP3372854B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a capacitor for operating as a smoothing capacitor is provided between a power supply voltage for operating a circuit and a ground.

[0002]

2. Description of the Related Art In a semiconductor device, in order to suppress the fluctuation of the power supply voltage in an internal circuit, it is generated between the external power supply voltage supplied from the outside and the ground or inside the semiconductor device based on the external power supply voltage. A capacitor that operates as a smoothing capacitor is provided between the internal power supply voltage and the ground. In recent years, with the progress of miniaturization of semiconductor devices, the data transfer rate has been improved by increasing the speed and increasing the number of bits. As a result, the fluctuation of the power supply voltage inside the semiconductor device becomes large, and the importance of the capacitance described above is becoming more and more important. Therefore,
Gate oxide capacitors having a large capacitance per unit area have been used.

[0003]

However, when an oxide film is used as the capacitance between the power supply voltage and the ground, a defect existing in the oxide film causes a problem. For example, when there is a defect in the gate oxide film when the gate oxide film capacitance is used between the power supply voltage and the ground, a leak current flows from the power supply voltage to the ground, so that the semiconductor device becomes defective in the leak current. In order to prevent defective leakage current, attempts have been made to obtain a defect-free gate oxide film from the viewpoint of the manufacturing process by adjusting the material of the gate oxide film, manufacturing conditions, and the like.

However, even if devised from the viewpoint of the manufacturing process, the total area of the capacitance occupying the entire semiconductor device is considerably large, and it is difficult to completely eliminate defects from the gate oxide film used for the capacitance. Furthermore, if there is even one defect in the entire capacitance, that is, the power supply voltage
When a leak current is generated between the grounds, the semiconductor device is determined to be defective. On the other hand, it is very difficult to determine the presence or absence of defects in each capacitance by inspection. Even if the inspection is possible, in order to relieve the defective capacity, the defective fuse is disconnected from the power supply voltage by disconnecting the redundant fuse provided in each capacity from the outside of the semiconductor device. This causes an increase in chip size and inspection cost. Therefore, under the present circumstances, when a leakage current defect due to the oxide film capacitance occurs, the semiconductor device is determined to be defective and is discarded.

In order to solve the above conventional problems, it is an object of the present invention to provide a semiconductor device which can be used as a good product even when a leak current due to a defect occurs in each capacitance of the semiconductor device. .

[0006]

In order to achieve the above object, the present invention provides a semiconductor device having a functional block,
A configuration including a capacitor interposed between power supplies for operating the functional block, and a disconnecting unit for inspecting the capacitor for a leak current and disconnecting the capacitor in which the leak current is generated from the power supplies. It is what

Specifically, the solution means taken by the invention of claim 1 is to provide a semiconductor device having a functional block connected to a first power source through a power source wiring with a power source wiring so that each semiconductor device operates as a smoothing capacitor. A plurality of capacitors interposed between the second power supply and the leak current of each of the plurality of capacitors are detected, and each capacitance is supplied from the power supply wiring or the second power supply according to the detection result of the leak current. It further comprises a disconnecting means for disconnecting.

According to this, among the plurality of capacitors for operating as the smoothing capacitor of the semiconductor device, the capacitor in which the leak current is generated is disconnected from the power supply wiring or the second power source, so that the leak current is generated in the smoothing capacitor. Since the capacity to be used is eliminated, the semiconductor device having the leak current can be relieved without being discarded.

Specifically, the solution of the invention of claim 2 is that in the semiconductor device of claim 1, each of the plurality of capacitors is a capacitor formed of a gate oxide film.

According to this, it is possible to relieve the semiconductor device that has been discarded due to the leak current caused by the defect in the gate oxide film.

Specifically, the solution means taken by the invention of claim 3 is the semiconductor device of claim 1, wherein the disconnecting means is
A plurality of switch means respectively interposed between the power supply wiring or the second power source and the corresponding one of the plurality of capacitors; a charging means for charging each of the plurality of capacitors to a predetermined voltage; After the completion, a change in the terminal voltage of each of the plurality of capacitors is detected after a lapse of a predetermined time, and the plurality of capacitors are disconnected from the power supply wiring or the second power supply according to the detection result. The control means for controlling the switch means is provided.

According to this, of the plurality of capacitors charged to a predetermined voltage, the capacitor judged to be defective based on the change of the terminal voltage after a predetermined time is surely confirmed from the power supply wiring or the second power supply. Can be separated into

Specifically, a solution means taken by the invention of claim 4 is the semiconductor device according to claim 3, wherein the charging means is provided with a plurality of charging power sources and a plurality of capacities corresponding to each other. It has an N-channel type MOS transistor.

According to this, the voltage for charging each of the plurality of capacitors is lower than the voltage at the charging power source due to the threshold voltage of each N-channel type MOS transistor, so that the amount of charge charged in each of the plurality of capacitors is reduced. By reducing the leakage current, it is possible to shorten the determination time in determining the leakage current and improve the leakage detection sensitivity.

Specifically, the solution means taken by the invention of claim 5 is the semiconductor device according to claim 3, wherein the control means has a terminal of a corresponding capacitance of a plurality of capacitances at the time when a predetermined time elapses. A plurality of latch circuits for holding a logic signal having a voltage level according to a voltage and controlling a corresponding switch means among a plurality of switch means according to the held logic signal are provided. is there.

According to this, the logic signal corresponding to the terminal voltage of each capacitor at the time when the predetermined time has elapsed can be surely held and the switching means can be surely controlled.

Specifically, the solution means taken by the invention of claim 6 is that in the semiconductor device of claim 3, the charging means and the control means are set to operate when the power of the semiconductor device is turned on. Is.

According to this, when the power of the semiconductor device is turned on, the capacitance in which the leakage current is generated is determined by the power supply wiring or the second capacitor.
Can be reliably disconnected from the power supply.

Specifically, the solution means taken by the invention of claim 7 is connected to the internal boosting power source for generating a power source voltage higher than the voltage of the first power source and the internal boosting power source via the power source wiring. And a plurality of capacitors interposed between the power supply wiring and the second power source so that each semiconductor device operates as a smoothing capacitor, and a leak current of each of the plurality of capacitors. And a disconnecting means for disconnecting each of the capacitors from the power supply wiring in accordance with the detection result of the leak current, and the disconnecting means respectively includes the power supply wiring and the corresponding capacitor of the plurality of capacitors. A plurality of P-channel type MOSs interposed as switch means between
A transistor, a charging means for charging each of the plurality of capacitors to a predetermined voltage, and a change in the terminal voltage of each of the plurality of capacitors after a predetermined time has elapsed after completion of charging, and the detection A control means for controlling the plurality of P-channel type MOS transistors so that each capacitance is disconnected from the power supply wiring in accordance with the result, and the control means respectively includes a first power supply and a second power supply. And a logic circuit having a voltage level of the first power supply or the second power supply according to a terminal voltage of a corresponding one of a plurality of capacitors at a time when a predetermined time has elapsed. A plurality of latch circuits for holding signals and a logic signal held in a corresponding one of the plurality of latch circuits is converted into a logic signal having a voltage level of an internal boost power supply or a second power supply. In addition, the logic signal obtained by the conversion is selected from among the plurality of P-channel MOS transistors so that the capacitance is disconnected from the power supply wiring according to the detection result regarding the change in the terminal voltage of the corresponding capacitance among the plurality of capacitances. And a plurality of level shifters for supplying to the gates of the corresponding MOS transistors.

According to this, it is determined whether or not the terminal voltage has changed after charging for each of the plurality of capacitors operating as the smoothing capacitors of the functional block using the internal boosting power source and the second power source. A logic signal having the voltage level of the first or second power supply is held according to the determination, and the held logic signal is converted into a logic signal having the voltage level of the internal boosting power supply or the second power supply. When the terminal voltage changes, the capacitance can be disconnected from the power wiring. Therefore, even when the functional block uses the internal boosting power supply and the second power supply, it is possible to reliably disconnect the capacitance in which the leakage current has occurred from the internal boosting power supply and the second power supply.

Specifically, the solution means taken by the invention of claim 8 is connected to the internal step-down power supply for generating a power supply voltage lower than the voltage of the first power supply, and the internal step-down power supply via the power supply wiring. And a plurality of capacitors interposed between the power supply wiring and the second power source so that each semiconductor device operates as a smoothing capacitor, and a leak current of each of the plurality of capacitors. And a disconnecting means for disconnecting each of the capacitors from the power supply wiring in accordance with the detection result of the leak current, and the disconnecting means respectively includes the power supply wiring and the corresponding capacitor of the plurality of capacitors. A plurality of MOS transistors interposed as switch means between the two, a charging means for charging each of the plurality of capacitors to a predetermined voltage, and a predetermined time after the completion of charging, each of the plurality of capacitors. Control means for detecting a change in the child voltage and controlling a plurality of MOS transistors so that the respective capacitors are disconnected from the power supply wiring in accordance with the detection result. A latch circuit configured between a power supply and a second power supply, the first power supply or the second power supply according to a terminal voltage of a corresponding one of a plurality of capacitors at a time when a predetermined time has elapsed. Hold a logic signal having the voltage level of the power supply, detect a change in the terminal voltage of the corresponding one of the plurality of capacitors, and hold the capacitor so that it is disconnected from the power supply wiring in accordance with the detection result. A plurality of latch circuits for supplying the generated logic signals to the gates of the corresponding MOS transistors of the plurality of MOS transistors, and an internal step-down power supply of the corresponding capacitance of the plurality of capacitances or the second A terminal voltage having a voltage level of a source is converted into a logic signal having a voltage level of the first power supply or the second power supply, and the logic signal obtained by the conversion is corresponding to one of the plurality of latch circuits. Further, a plurality of level shifters for supplying to the

According to this, after the operation of the disconnecting means is completed, a change in the terminal voltage after charging of the plurality of capacitors operating as the smoothing capacitors of the functional block using the internal step-down power source and the second power source is performed. It is possible to hold the logic signal and to control the intervening MOS transistor as a switch means for each of the capacitors based on the logic signal. Therefore, the capacitance in which the leak current is generated is separated from the internal step-down power supply and the second power supply, and the capacitance in which the leak current is not generated is connected between the internal step-down power supply and the second power supply and smoothed. The state of operating as a capacitor can be maintained.

Specifically, the solution means taken by the invention of claim 9 is to connect to the first power supply through an internal boosting power supply for generating a power supply voltage higher than the voltage of the first power supply and power supply wiring. A plurality of capacitors interposed between the power supply wiring and the second power source so that each semiconductor device operates as a smoothing capacitor, and a leakage current of each of the plurality of capacitors. And disconnecting means for disconnecting each capacitance from the power supply wiring according to the detection result of the leak current, and the disconnecting means is each power supply wiring and the corresponding capacitance of the plurality of capacitances. A plurality of N-channel type MOS transistors which are interposed as a switch means between the two, a charging means for charging each of the plurality of capacitors to a predetermined voltage, and a plurality of after a lapse of a predetermined time after completion of charging. Content Detecting a change in each of the terminal voltages of,
And a control means for controlling the plurality of N-channel type MOS transistors so that the respective capacitors are disconnected from the power supply wiring in accordance with the detection result, and the control means respectively include the first power supply and the second power supply. A latch circuit configured between the power supply and a power supply, the first latching circuit according to a terminal voltage of a corresponding one of a plurality of capacitors when a predetermined time has elapsed.
A plurality of latch circuits for holding a logic signal having the voltage level of the second power supply or the power supply of the second power supply, and the internal boosting power supply or the second latch circuit for holding the logic signal held by the corresponding latch circuit of the plurality of latch circuits. A plurality of level shifters for converting into a logic signal having the voltage level of the power supply and supplying it to the gate of the corresponding MOS transistor among the plurality of N channel type MOS transistors.

According to this, the layout area of the semiconductor device can be reduced by using the N-channel type MOS transistor having a larger current driving capability.

Specifically, a solution means taken by the invention of claim 10 is that a semiconductor device having a functional block connected to a first power source via a power source wiring is provided with a power source wiring and a first power source wiring so as to operate as a smoothing capacitor. The capacity that is interposed between the two power sources,
Switch means interposed between the power supply wiring or the second power source and the capacity, charging means for charging the capacity to a predetermined voltage, and a terminal voltage of the capacity after a predetermined time elapses after charging is completed. It further comprises a control means for detecting the change and controlling the switch means so that the capacitor is disconnected from the power supply wiring or the second power supply according to the detection result.

According to this, when a leak current occurs in the capacitor for operating as the smoothing capacitor of the semiconductor device, the capacitor can be disconnected from the power supply wiring or the second power supply.

[0027]

DETAILED DESCRIPTION OF THE INVENTION A semiconductor device according to the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a semiconductor device of the present invention. In FIG. 1, power supply voltage Vcc is an external power supply voltage supplied from the outside.
The ground Vss is a reference voltage that serves as a reference for the operation of the semiconductor device. The internal boosted power supply PSh is a power supply for boosting the received power supply voltage Vcc to generate the boosted voltage Vpp. The internal step-down power supply PS1 is a power supply for stepping down the received power supply voltage Vcc to generate the step-down voltage Vint. The functional block FB is a circuit for performing a predetermined operation in the semiconductor device by the power supply voltage Vcc, the boosted voltage Vpp, the stepped down voltage Vint, and the ground Vss. Capacitance CAP is the power supply voltage Vc
The gate oxide film capacitances are provided between c and the ground Vss, between the boosted voltage Vpp and the ground Vss, and between the stepped down voltage Vint and the ground Vss.
The disconnection circuit SW includes the capacitors CAP and the power supply voltage Vcc,
The capacitor CAP, which is provided between the boosted voltage Vpp and the stepped-down voltage Vint and has a leak current, is connected to the power supply voltage Vc.
c, a boosting voltage Vpp or a step-down voltage Vint.

The operation of the semiconductor device shown in FIG. 1 will be described. First, a control means (not shown) provided in association with each capacitance CAP indicates the value of the amount of charge charged in each capacitance when the power is turned on after a certain period of time.
The voltage across the terminals of P is detected.

As a result, if the voltage across the terminals of the capacitor CAP maintains the value immediately after charging, it means that no leakage current has occurred in the capacitor CAP, and the control means turns on the disconnection circuit SW. , Capacity CAP to power supply voltage V
cc, step-up voltage Vpp, or step-down voltage Vint. Therefore, the capacitance CAP is equal to the power supply voltage Vcc, the boost voltage Vpp, or the step-down voltage Vint and the ground Vss.
And acts as a smoothing capacitor.

On the other hand, if the inter-terminal voltage of the capacitor CAP is 0 V, it means that a leak current has occurred in the capacitor CAP, so the control means turns off the disconnection circuit SW to supply the power supply voltage Vcc and the boosted voltage. The capacitor CAP is separated from Vpp or the step-down voltage Vint and the ground Vss. Therefore, the capacitance CA in which the leakage current occurs
P no longer acts as a smoothing capacitor.

For example, consider a case where 12 capacitors CAP are arranged between the power supply voltage Vcc and the ground Vss of the semiconductor device, and a leak current occurs in one of them. Conventionally, even if a leak current occurs in one capacitor CAP, the semiconductor device is discarded as a defect. However, according to the semiconductor device of the present invention, 12 capacitors C
Only one of the APs where the leak current has occurred is the power supply voltage V
It can be separated from cc. As a result, the capacitance value of the smoothing capacitance between the power supply voltage Vcc and the ground Vss is reduced by about 8%, but it is possible to relieve a semiconductor device that has been discarded as a leak current defect.

As described above, according to the semiconductor device of FIG. 1, it is determined whether or not there is a defect in the capacitor CAP, and the defect is detected between the power supply voltage Vcc, the boost voltage Vpp, or the step-down voltage Vint and the ground Vss. The capacity CAP with can be disconnected. Therefore, the semiconductor device, which has been conventionally discarded as a leak current defect, is relieved by determining whether or not to use the capacitor CAP as a smoothing capacitor without inviting an increase in chip size due to a redundant fuse or the like. Thus, a semiconductor device that reduces waste can be provided.

In the above description, the capacity CAP
When charging the battery, the power supply voltage Vcc, the boost voltage Vpp, and the step-down voltage Vint connected to the capacitor CAP may be used respectively, and the power supply voltage Vc supplied from the outside may be used.
You may connect and use c for charge.

The functional block FB has a power supply voltage Vc.
It suffices that it operates by at least one of c, the boosted voltage Vpp, and the lowered voltage Vint, or a combination thereof.

FIG. 2 is a circuit diagram showing an example of details of the semiconductor device of FIG. As shown in FIG. 2, the semiconductor device includes a capacitor CAP, a charging circuit CHGp, and a disconnecting circuit S.
It is composed of Wp and a latch circuit LAT. The disconnection circuit SWp corresponds to the disconnection circuit SW in the semiconductor device of FIG. The same components as those in FIG. 1 are designated by the same reference numerals as those in FIG. 1, and the description thereof will be omitted as appropriate.

The capacitance CAP is a gate oxide film capacitance provided between the node NA and the ground Vss which is a reference voltage. That is, the capacitor CAP operates as a smoothing capacitor between the potential at the node NA and the ground Vss.

The charging circuit CHGp includes an inverter INV1.
And a P-channel type MOS transistor (PMOS transistor) Qp1. Inverter INV1
Is an inverting circuit for inverting the charging signal SCHG received from a control circuit (not shown). The source of the PMOS transistor Qp1 is connected to the power supply voltage Vcc, the drain is connected to the node NA, and the gate is connected to the output of the inverter INV1.

The disconnection circuit SWp is a switching means composed of a PMOS transistor Qp2. The PMOS transistor Qp2 has a source connected to the power supply voltage Vcc, a drain connected to the node NA, and a gate connected to the node NB.

The latch circuit LAT is the inverter INV2.
And PMOS transistors Qp3, Qp4 and N-channel type MOS transistor (NMOS transistor) Qn1,
And Qn2. The inverter INV2 receives the latch signal / SL received from the control circuit (not shown).
It is an inverting circuit for inverting AT. The PMOS transistor Qp3 has a source connected to the power supply voltage Vcc, a drain connected to the node NB, and a gate connected to the node NA. The PMOS transistor Qp4 has a source connected to the power supply voltage Vcc, a drain connected to the node NB, and a gate connected to the output of the inverter INV2. NMO
The drain of the S transistor Qn1 is connected to the node NB, the source is connected to the drain of the NMOS transistor Qn2, and the gate is connected to the output of the inverter INV2. The source of the NMOS transistor Qn2 is connected to the ground Vss, and the gate thereof is connected to the node NA.

In the semiconductor device of FIG. 2, an operation of detecting a current leak occurring in the capacitor CAP and an operation of determining whether or not to use the capacitor CAP based on the detection result will be described.

First, when the power is turned on, the charging signal SC
HG and latch signal / SLAT are "high"
("H"). As a result, the inverter INV
Since the output of 1 is set to "low"("L") to turn on the PMOS transistor Qp1, the potential of the node NA becomes the power supply voltage Vcc, that is, "H", and the PMOS transistor Qp3 is turned off. At the same time, the output of the inverter INV2 is set to "low"("L") to turn on the PMOS transistor Qp4 and turn off the NMOS transistor Qn1, so that the potential of the node NB becomes the power supply voltage Vcc, that is, "H". Therefore, the PMOS transistor Q
PMOS transistor Qp turned on by turning off p2
The capacitor CAP is charged with the power supply voltage Vcc via 1. The charging time in this case is determined by the electrostatic capacitance value of the capacitor CAP, the current driving capability of the PMOS transistor Qp1, and the potential difference between the power supply voltage Vcc and the ground Vss, that is, Vcc-Vss = Vcc.

Next, the capacity CAP is set by the power supply voltage Vcc.
After charging, the charge signal SCHG is set to “L” and P
The MOS transistor Qp1 is turned off and the state is maintained. This completes the charging of the capacitor CAP and thereafter keeps the capacitor CAP separated from the power supply voltage Vcc via the PMOS transistor Qp1.
The supply of charges via the PMOS transistor Qp1 is stopped. Therefore, the potential of the node NA is equal to the capacitance CAP.
In the case where the leak current occurs, the charge flows to the ground Vss to become the ground Vss, and when it does not occur, the power supply voltage Vcc is maintained. By detecting the potential of the node NA in this case, it is possible to determine whether or not there is a leak current due to a defect in the capacitor CAP. The timing of setting the charging signal SCHG to “L” is
The capacitance value of the capacitance CAP and the PMOS transistor Qp
1, current drive capacity, power supply voltage Vcc and ground Vs
It is determined by the potential difference with s, that is, Vcc-Vss = Vcc.

Next, description will be made for different cases based on the presence / absence of a leak current due to a defect in the capacitor CAP. When no leak current is generated, the potential of the node NA is kept at “H” even after the PMOS transistor Qp1 is turned off. This turns off the PMOS transistor Qp3 and keeps the NMOS transistor Qn2 on. Then, the latch signal / SLAT is changed from "H" to "L".
By setting the output of the inverter INV2 to "H", turning off the PMOS transistor Qp4,
And the NMOS transistor Qn1 is turned on. That is,
Turning off the PMOS transistors Qp3 and Qp4, and
By turning on the NMOS transistors Qn1 and Qn2, the potential of the node NB becomes “L” and is held. As a result, the PMOS transistor Qp2 is turned on, so that the capacitor CAP can be connected to the power supply voltage Vcc.
Therefore, the capacitor CAP operates as a smoothing capacitor between the power supply voltage Vcc and the ground Vss.

On the other hand, when a leak current is generated in the capacitor CAP, the leak current causes an electric charge to be generated in the capacitor CAP.
Since it flows out from the ground to the ground Vss, the potential of the node NA becomes “L” after a certain period of time. As a result, the PMOS transistor Qp3 is turned on and NM
The OS transistor Qn2 is turned off. Then, by changing the latch signal / SLAT from "H" to L, the output of the inverter INV2 is set to "H", the PMOS transistor Qp4 is turned off, and the NMOS transistor Qp4 is turned off.
Turn on n1. In this case, even if the PMOS transistor Qp4 is turned off, the PMOS transistor Qp3
Is turned on, and the NMOS transistor Qn1
Since the NMOS transistor Qn2 is turned off even when is turned on, the potential of the node NB becomes "H" and is held. As a result, the PMOS transistor Qp2
Is turned off, the capacity CAP is equal to the power supply voltage Vcc.
Stay separate from. Therefore, thereafter, no leak current is generated in the capacitor CAP. That is, when the capacitance CAP is defective, the generation of the leak current can be prevented by disconnecting the capacitance CAP from the power supply voltage Vcc.

As described above, according to the semiconductor device of FIG. 2, the PMO is provided between the capacitance CAP and the power supply voltage Vcc.
The disconnection circuit SWp including the S transistor Qp2 is provided, and the capacitor CAP is charged by the charging circuit CHGp when the power is turned on. Then, after a fixed time, the latch circuit L
AT detects the potential of the node NA. As a result, if the potential of the node NA is “L”, it is determined that a leak current has occurred in the capacitor CAP, and the disconnection circuit SWp disconnects the capacitor CAP from the power supply voltage Vcc. On the other hand, if the potential of the node NA is “H”, it is determined that no leak current has occurred in the capacitor CAP, and the disconnection circuit SW
p connects the capacitor CAP to the power supply voltage Vcc. Therefore, it is determined that there is a leak current defect by determining the presence or absence of a defect in the capacitor CAP and disconnecting the defective capacitor CAP from the power supply voltage Vcc, that is, by determining whether or not to use the capacitor CAP as a smoothing capacitor. It is possible to provide a semiconductor device that reduces the amount of waste by relieving a semiconductor device that has been conventionally discarded.

FIG. 3 is a circuit diagram showing a first modification of the details of the semiconductor device of FIG. As shown in FIG.
The semiconductor device includes a capacitor CAP, a charging circuit CHGn, a disconnecting circuit SWp, and a latch circuit LAT.
The disconnection circuit SWp is the disconnection circuit SW in FIG.
Equivalent to. The same components as those in FIG.
The same reference numerals as those in FIG.

The semiconductor device of FIG. 3 has a charging circuit CH that operates in response to a charging signal / SCHG instead of the charging circuit CHGp that operates in accordance with the charging signal SCHG in FIG.
Gn is provided. The charging circuit CHGn includes an inverter INV1 and an NMOS having a threshold voltage Vtn.
It is composed of a transistor Qn3.

The operation of the charging circuit CHGn will be described. First, when the power is turned on, the charge signal / SCHG is set to "L".
To Charge signal / SC by inverter INV1
"H", which is the inverted HG, is the NMOS transistor Qn3.
Is supplied to the gate of the NMOS transistor Qn
3 turns on. Then, since the PMOS transistor Qp2 is turned off as in the case of FIG. 2, the capacitor CAP is charged by the voltage via the NMOS transistor Qn3.
In this case, the voltage via the NMOS transistor Qn3 rises to Vcc-Vtn (<Vcc), so that the capacitance CAP is charged by Vcc-Vtn (<Vcc).

Next, after the capacitance CAP is charged by the voltage Vcc-Vtn (<Vcc), the charge signal / SCH is generated.
G is set to "H" to turn off the NMOS transistor Qn3 and maintain its state. This completes the charging of the capacitor CAP, and thereafter the NMOS transistor Q
The capacitor CAP remains disconnected from the power supply voltage Vcc via n3. The operation of detecting the current leak generated in the capacitor CAP and the operation of determining whether or not to use the capacitor CAP based on the detection result are the same as in the case of FIG.

As described above, according to this modification,
By determining whether or not the capacitor CAP is used as the smoothing capacitor by itself, it is possible to provide a semiconductor device that can relieve a semiconductor device that has been conventionally discarded as a leak current defect and reduce the discard.

Further, the charging circuit CHGn using the NMOS transistor Qn3 allows the voltage Vcc-Vtn (<V
The capacity CAP is charged by cc). As a result, the amount of charge charged in the capacitor CAP is smaller than that in the case where the capacitor CAP is charged by the power supply voltage Vcc.
Therefore, when a leak current due to a defect occurs in the capacitor CAP, the time taken for the charge charged in the capacitor CAP to flow to the ground Vss is shortened, and therefore the time required to determine the leak current can be shortened.

Further, when the leak current determination times are the same, the amount of charge charged in the capacitor CAP is smaller than that in the case where the capacitor CAP is charged by the power supply voltage Vcc, so a smaller leak current is obtained. Can be detected to improve the leak detection sensitivity.

FIG. 4 is a circuit diagram showing a second modification of the details of the semiconductor device of FIG. As shown in FIG.
The semiconductor device includes a capacitor CAP, a charging circuit CHGp, a disconnecting circuit SWp, a latch circuit LAT, and a level shifter L.
It is composed of SF1. The separation circuit SWp corresponds to the separation circuit SW in FIG. Then, the same components as those in FIG. 2 are designated by the same reference numerals as those in FIG. 2, and the description thereof will be appropriately omitted.

The semiconductor device of FIG. 4 is obtained by adding the level shifter LSF1 to the semiconductor device of FIG. 2 and connecting the disconnection circuit SWp to the boosted voltage Vpp. The source of the PMOS transistor Qp2 included in the disconnection circuit SWp is the boosted voltage Vpp, the drain thereof is the node NA,
The gates are connected to the outputs of the level shifter LSF1. The level shifter LSF1 is a conversion means for converting a signal of the power supply voltage Vcc level into a signal of the boosted voltage Vpp level, and its input is connected to the node NB.

In the semiconductor device of FIG. 4, an operation of detecting a current leak occurring in the capacitor CAP and an operation of determining whether or not to use the capacitor CAP based on the detection result will be described.

First, as in the case of FIG. 2, when the power is turned on, the charge signal SCHG and the latch signal / SLAT are set to "H", and the potential of the node NA and the potential of the node NB are set to the power supply voltage Vcc level. Set to "H". In this case, the boosted voltage Vpp generated inside the semiconductor device is
Immediately after the power is turned on, the power supply voltage V supplied from the outside
lower than cc. Therefore, until the boosted voltage Vpp is raised to the potential of the power supply voltage Vcc, the level shifter LSF1 to which the potential “H” of the node NB is input can output only up to the power supply voltage Vcc.

Next, when the boosted voltage Vpp exceeds the power supply voltage Vcc and reaches a normal level, the level shifter LSF1
Is the boosted voltage V applied to the gate of the PMOS transistor Qp2.
It outputs pp level "H". Therefore, in the PMOS transistor Qp2 whose source is connected to the boosted voltage Vpp, by supplying "H" of the boosted voltage Vpp level to the gate, the gate-source voltage Vp
Gs is set to Vgs = 0 and the PMOS transistor Qp2 is turned off. As a result, the PMOS transistor Qp
The capacitor CAP is charged with the power supply voltage Vcc via 1.

Next, according to the power supply voltage Vcc, the capacitance CAP
After being charged, the charging signal SC
HG is set to "L" to turn off the PMOS transistor Qp1 and maintain that state. As a result, the charging of the capacitor CAP is completed, and thereafter, the capacitor CAP is charged with the power supply voltage V
Leave it separated from cc.

Next, description will be made for different cases based on the presence / absence of a leak current due to a defect in the capacitor CAP. When no leak current occurs, the potential of the node NB becomes "L" of the power supply voltage Vcc level by the same operation as in the case of FIG. 2, so the output of the level shifter LSF1 is the boosted voltage Vp.
The p-level becomes "L", and the PMOS transistor Qp2
Is turned on and the capacitor CAP can be connected to the boosted voltage Vpp.
Therefore, the capacitor CAP operates as a smoothing capacitor between the boosted voltage Vpp and the ground Vss.

On the other hand, when a leak current occurs in the capacitor CAP, the potential of the node NA becomes "L". Therefore, the potential of the node NB is "L" of the power supply voltage Vcc level by the same operation as in the case of FIG. H "and is held. The potential of the node NB is the level shifter LSF1.
Is converted to "H" at the boosted voltage Vpp level.
Therefore, the level shifter LSF1 includes the PMOS transistor Qp2 whose source is connected to the boosted voltage Vpp.
The "H" of the boosted voltage Vpp level is continuously supplied to the gate of the. As a result, by maintaining the state of the gate-source voltage Vgs = 0, the PMOS transistor Qp2
Is off, the capacitance CAP is equal to the boost voltage Vpp.
Stay separate from. Therefore, thereafter, no leak current is generated in the capacitor CAP. That is, when the capacitor CAP is defective, the leakage current can be prevented by disconnecting the capacitor CAP from the boosted voltage Vpp.

In addition, in the period until the capacity CAP is charged and then it is determined whether or not there is a defect, and when the defect of the capacity CAP is found as a result, the PMO
It is necessary to turn off the S transistor Qp2 and disconnect the capacitor CAP from the boosted voltage Vpp. However, when the gate potential of the PMOS transistor Qp2 is lower than the source potential, a leak current flows between the source and drain.
This causes a problem that the leak current due to the defect of the capacitor CAP cannot be accurately detected, or the capacitor CAP cannot be completely separated even if there is a defect. According to the semiconductor device of the present invention, the internally controlled boosted voltage Vpp level signal is supplied to the gate controlling the PMOS transistor Qp2 instead of the externally supplied power supply voltage Vcc level signal. As a result, in the PMOS transistor Qp2, the gate-source voltage Vgs is -Vgs> Vtp (Vtp is P
Since the threshold voltage of the MOS transistor Qp2) is set, the leakage current between the source and drain is suppressed and the capacitance C
A leak current due to a defect in AP can be accurately detected, and the PMOS transistor Qp2 can be reliably turned off.

As described above, according to this modification,
By determining whether or not the capacitor CAP is used as the smoothing capacitor by itself, it is possible to provide a semiconductor device that can relieve a semiconductor device that has been conventionally discarded as a leak current defect and reduce the discard.

Further, the power supply voltage Vcc supplied from the outside
When the semiconductor device is operated by the boosted voltage Vpp generated by the semiconductor device based on
It is possible to more accurately determine the presence or absence of the defect of No. 1 and to more reliably disconnect the defective capacitor CAP from the boosted voltage Vpp.

FIG. 5 is a circuit diagram showing a third modification of the details of the semiconductor device of FIG. As shown in FIG.
The semiconductor device includes a capacitor CAP, a charging circuit CHGp, a disconnecting circuit SWn, a latch circuit LAT, and a level shifter L.
It is composed of SF2. The separation circuit SWn corresponds to the separation circuit SW in FIG. The same components as those in FIG. 4 are designated by the same reference numerals as those in FIG. 4, and the description thereof will be omitted as appropriate.

The semiconductor device of FIG. 5 is different from the semiconductor device of FIG. 2 in that the disconnecting circuit SWp is replaced with the disconnecting circuit SW.
n, the boosted voltage V is applied to the level shifter LSF1 of FIG.
A level shifter LSF2 by adding an inverter INV3 using pp as a power source is added. The inverter INV3 is an inverting means for inverting and supplying the signal received from the level shifter LSF1, that is, the signal of the boosted voltage Vpp level. Disconnection circuit SWn
Has the drain at the power supply voltage Vcc and the source at the node NA.
Of the NMOS transistor Qn4 whose gates are respectively connected to the output of the inverter INV3, and based on the signal received from the inverter INV3, the capacitance CAP
Is a switch means for connecting to or disconnecting from the power supply voltage Vcc.

The semiconductor device of FIG. 5 determines the potential of the node NA similarly to the semiconductor device of FIG. Then, the disconnecting circuit SWn keeps the capacitor CAP disconnected from the power supply voltage Vcc when a leak current occurs in the capacitor CAP, and connects the capacitor CAP to the power supply voltage Vcc when no leak current occurs. In this case, the signal of the boosted voltage Vpp level is supplied to the gate of the NMOS transistor Qn4 by the inverter INV3. Therefore, when the inverter INV3 supplies "H", the gate-source voltage Vgs of the NMOS transistor Qn4 becomes Vgs> Vtn (Vtn is the threshold voltage of the NMOS transistor Qn4), and thus the capacitance CAP.
Is reliably connected to the power supply voltage Vcc.

As described above, according to this modification,
By determining whether or not the capacitor CAP is used as the smoothing capacitor by itself, it is possible to provide a semiconductor device that can relieve a semiconductor device that has been conventionally discarded as a leak current defect and reduce the discard.

Further, by using the NMOS transistor Qn4 having a current driving capacity about twice as high as that of the PMOS transistor, the decoupling circuit SWn can be constructed with about half the transistor size, and therefore the layout area of the semiconductor device can be reduced. .

FIG. 6 is a circuit diagram showing a fourth modification of the details of the semiconductor device of FIG. As shown in FIG.
The semiconductor device includes a capacitor CAP, a charging circuit CHGp, a disconnecting circuit SWp, a latch circuit LAT, and a level shifter LSF.
3 and a level changeover switch LSW. The separation circuit SWp corresponds to the separation circuit SW in FIG. Then, the same components as those in FIG. 2 are designated by the same reference numerals as those in FIG. 2, and the description thereof will be appropriately omitted.

In the semiconductor device of FIG. 6, a level shifter LSF3, a level switching switch LSW, and a switching signal SLSW are added to the semiconductor device of FIG.
p is connected to the step-down voltage Vint. The source of the PMOS transistor Qp2 included in the disconnection circuit SWp is connected to the step-down voltage Vint. The level shifter LSF3 is a conversion means for converting the received signal of the step-down voltage Vint level into a signal of the power supply voltage Vcc level and supplying the signal. Level changeover switch LSW
Switches the potential of the node NA and the signal of the power supply voltage Vcc level received from the level shifter LSF3 according to a switching signal SLSW received from a control circuit (not shown), and outputs a control signal CTL consisting of either one selected. It is a switching means for supplying to the node NB.

In the semiconductor device of FIG. 6, an operation of detecting a current leak generated in the capacitor CAP and an operation of determining whether or not to use the capacitor CAP based on the detection result will be described.

First, when the power is turned on, the charge signal SCHG and the latch signal / SLAT are set to "H" as in the case of FIG. 2, and the switching signal SLSW is set so that the level switching switch LSW selects the node NA. Set. As a result, the potential of the node NA and the potential of the node NB are set to “H” at the power supply voltage Vcc level, and the level changeover switch LSW sets the potential of the node NA, that is, “H” at the power supply voltage Vcc level to the node NB. Supply. Therefore, as in the case of FIG. 2, the PMOS transistor Qp2
Is turned off, the capacitor CAP is charged by the power supply voltage Vcc via the PMOS transistor Qp1.

Next, according to the power supply voltage Vcc, the capacitance CAP
After being charged, the charging signal SC
HG is set to "L" to turn off the PMOS transistor Qp1 and maintain that state. As a result, the charging of the capacitor CAP is completed, and thereafter, the capacitor CAP is charged with the power supply voltage V
Leave it separated from cc.

Next, description will be made for different cases based on the presence / absence of a leak current due to a defect in the capacitor CAP. When the leak current does not occur, the capacitor CAP can be connected to the step-down voltage Vint by the same operation as in the case of FIG. Therefore, the capacitor CAP operates as a smoothing capacitor between the step-down voltage Vint and the ground Vss. Also,
The level switching switch LSW receives the switching signal SL
According to SW, the level shifter LSF3 causes the node N
The power supply voltage Vcc converted from the potential of A (= step-down voltage Vint) is selected and supplied to the node NB. As a result, when there is no defect in the capacitance CAP, that is, in the case of normal operation, the voltage of the node NA and the voltage of the latch circuit LAT that operates using the power supply voltage Vcc are matched, so that the through current of the PMOS transistor Qp3 is reduced. Occurrence can be prevented.

On the other hand, when a leak current is generated in the capacitor CAP, the potential of the node NA becomes "L" of the power supply voltage Vcc level, and the control signal CTL via the level shifter LSF3 and the level changeover switch LSW is also the power supply voltage. It goes to Vcc level "L". Then, by the same operation as in the case of FIG. 2, the potential of the node NB changes to the power supply voltage Vcc.
The level becomes “H” and is held. Therefore,
Power supply voltage Vcc is applied to the gate of the PMOS transistor Qp2.
The level "H" is continuously supplied, and as a result, the PMOS transistor Qp2 remains off, so that the capacitance CAP
Keeps a state separated from the step-down voltage Vint.
Therefore, thereafter, no leak current is generated in the capacitor CAP. That is, when the capacitor CAP is defective, the leakage current can be prevented by disconnecting the capacitor CAP from the step-down voltage Vint.

As described above, according to this modification,
When the semiconductor device operates with the step-down voltage Vint generated by the semiconductor device based on the power supply voltage Vcc supplied from the outside, it is determined whether or not there is a defect in the capacitor CAP,
The defective capacitor CAP can be separated from the step-down voltage Vint. Therefore, by determining whether or not the capacitor CAP is used as the smoothing capacitor by itself, it is possible to provide a semiconductor device which can relieve a semiconductor device that has been conventionally discarded as a leak current defect and reduce the discard.

In each of the semiconductor devices described above, the disconnection circuits SW, SWp, SWn.
Is the power supply voltage Vcc, the boost voltage Vpp, or the step-down voltage V
Although it is arranged between int and the capacitor CAP, it may be arranged between the capacitor CAP and the ground Vss instead.

[0078]

According to the first to third aspects of the invention, the semiconductor device itself detects the capacitance in which the leak current is generated among the plurality of capacitances provided so as to operate as the smoothing capacitance, and supplies the capacitance to the power supply. Since it is disconnected from the wiring or the second power source, it is possible to relieve a semiconductor device that has been conventionally discarded as a leak current defect and reduce the waste of the semiconductor device.

According to the invention of claim 4, the voltage for charging each capacitance is lowered by the threshold voltage of the N-channel type MOS transistor used as the charging means, so that the amount of charge charged in each capacitance is reduced. Thus, it is possible to shorten the time for determining the leak current and improve the leak detection sensitivity.

According to the fifth aspect of the present invention, since the switch means is surely controlled by surely holding the logic signal corresponding to the terminal voltage of each capacitor after charging, the capacitor in which the leak current is generated is connected to the power supply wiring. Alternatively, the semiconductor device can be prevented from being discarded due to a defective leakage current by reliably disconnecting it from the second power supply.

According to the sixth aspect of the present invention, the capacity in which the leak current is generated when the power is turned on can be reliably separated from the power supply wiring or the second power supply, so that the semiconductor device can operate reliably after the power is turned on. it can.

According to the seventh and eighth aspects of the present invention, the leak current also occurs in the functional block using the internal step-up power source and the second power source and the functional block using the internal step-down power source and the second power source. The generated capacitance can be reliably separated from the power supply wiring to prevent the semiconductor device from being discarded due to defective leakage current.

According to the ninth aspect of the invention, the switch means is an N-channel type M having a larger current drive capability.
By using the OS transistor, the layout area of the semiconductor device can be reduced.

According to the tenth aspect of the present invention, when a leak current is generated in the capacitor for operating as the smoothing capacitor of the semiconductor device, the capacitor is disconnected from the power supply wiring or the second power supply, and the leak current is defective. It is possible to prevent the disposal of the semiconductor device.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a semiconductor device according to the present invention.

FIG. 2 is a circuit diagram showing an example of details of the semiconductor device of FIG.

FIG. 3 is a circuit diagram showing a first modification of the details of the semiconductor device of FIG.

FIG. 4 is a circuit diagram showing a second modification of the details of the semiconductor device of FIG.

5 is a circuit diagram showing a third modification of the details of the semiconductor device of FIG.

FIG. 6 is a circuit diagram showing a fourth modification of the details of the semiconductor device of FIG.

[Explanation of symbols]

CAP capacity CHGn, CHGp charging circuit (charging means) CTL control signal FB functional block INV1, INV2, INV3 inverter LAT latch circuit LSF1, LSF2, LSF3 level shifter LSW level changeover switch NA, NB node PSh internal step-up power supply PS1 internal step-down power supply Qn1, Qn2, Qn3, Qn4 NMOS transistor Qp1, Qp2, Qp3, Qp4 PMOS transistor SCHG, / SCHG charge signal / SLAT latch signal SLSW switching signal SW, SWn, SWp disconnection circuit (switch means) Vcc power supply voltage Vint step-down voltage Vpp step-up voltage Vss Ground

─────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-7-335833 (JP, A) JP-A-7-142680 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 27/04

Claims (10)

(57) [Claims] 1. A semiconductor device having a functional block connected to a first power supply via a power supply wiring, wherein the power supply wiring and the second power supply wiring are arranged to operate as smoothing capacitors, respectively.
A plurality of capacitors interposed between the plurality of capacitors and a power source of the plurality of capacitors, and a leak current of each of the plurality of capacitors is detected. A semiconductor device further comprising a disconnecting unit for disconnecting from a power supply. 2. The semiconductor device according to claim 1, wherein each of the plurality of capacitors is a capacitor formed of a gate oxide film. 3. The semiconductor device according to claim 1, wherein the disconnecting unit is provided with a plurality of switch units each interposed between the power supply line or the second power supply and a corresponding one of the plurality of capacitors. A charging means for charging each of the plurality of capacitors to a predetermined voltage; and, after the charging is completed, detecting a change in the terminal voltage of each of the plurality of capacitors, and A semiconductor device comprising: control means for controlling the plurality of switch means so that each of the capacitors is disconnected from the power supply wiring or the second power supply according to the detection result. 4. The semiconductor device according to claim 3, wherein the charging unit includes a plurality of N-channel type Ms each interposed between a charging power source and a corresponding one of the plurality of capacitors.
A semiconductor device having an OS transistor. 5. The semiconductor device according to claim 3, wherein the control unit has a logic level having a voltage level corresponding to a terminal voltage of a corresponding one of the plurality of capacitors at the time when the predetermined time has elapsed. A semiconductor device having a plurality of latch circuits for holding a signal and controlling a corresponding switch means of the plurality of switch means according to the held logic signal. 6. The semiconductor device according to claim 3, wherein the charging unit and the control unit are set to operate when the power of the semiconductor device is turned on. 7. A semiconductor device having an internal boosting power supply for generating a power supply voltage higher than the voltage of the first power supply, and a functional block connected to the internal boosting power supply via a power supply wiring, The semiconductor device includes the power supply wiring and the second wiring so as to operate as a smoothing capacitor.
A plurality of capacitors interposed between the power source and the power source, and a disconnection for detecting each leakage current of each of the plurality of capacitors and disconnecting each of the capacitors from the power supply wiring according to the detection result of the leakage current. A plurality of P-channel type MOS transistors interposed as switch means between the power supply wiring and a corresponding one of the plurality of capacitors, and Charging means for charging each to a predetermined voltage, after the completion of the charging, to detect a change in the terminal voltage of each of the plurality of capacitors after the elapse of a predetermined time, and according to the detection result, Control means for controlling the plurality of P-channel type MOS transistors so that the respective capacitors are separated from the power supply wiring, the control means respectively comprising: the first power supply; And a second power supply, the first power supply according to a terminal voltage of a corresponding one of the plurality of capacitors at the time when the predetermined time has elapsed. Or a plurality of latch circuits for holding a logic signal having a voltage level of the second power supply, and a logic signal held in a corresponding latch circuit of the plurality of latch circuits, the internal boosting power supply or the Second
Converting into a logic signal having a voltage level of the power supply of the power supply, and converting the capacitance so that the capacitance is disconnected from the power supply wiring in accordance with a detection result regarding a change in the terminal voltage of the corresponding capacitance. A semiconductor device comprising: a plurality of level shifters for supplying the logic signal obtained by the above to a gate of a corresponding MOS transistor among the plurality of P-channel type MOS transistors. 8. A semiconductor device having an internal step-down power supply for generating a power supply voltage lower than the voltage of a first power supply, and a functional block connected to the internal step-down power supply via a power supply wiring, The semiconductor device includes the power supply wiring and the second wiring so as to operate as a smoothing capacitor.
A plurality of capacitors interposed between the power source and the power source, and a disconnection for detecting each leakage current of each of the plurality of capacitors and disconnecting each of the capacitors from the power supply wiring according to the detection result of the leakage current. A plurality of MOS transistors interposed as switch means between the power supply wiring and a corresponding one of the plurality of capacitors, and the plurality of capacitors each having a predetermined capacitance. Charging means for charging to a voltage of, after the completion of the charging, to detect a change in the terminal voltage of each of the plurality of capacitors after the lapse of a predetermined time, and according to the detection result, each of the A control means for controlling the plurality of MOS transistors so that a capacitance is separated from the power supply wiring, wherein the control means is provided between the first power supply and the second power supply, respectively. A latch circuit configured to change the voltage level of the first power supply or the second power supply according to the terminal voltage of the corresponding one of the plurality of capacitors at the time when the predetermined time has elapsed. Holding the logic signal, detecting a change in the terminal voltage of the corresponding capacitance of the plurality of capacitances, and holding the logic signal so that the capacitance is disconnected from the power supply wiring in accordance with the detection result. A plurality of latch circuits for supplying the gate to the gate of a corresponding MOS transistor of the plurality of MOS transistors, and a voltage of the internal step-down power supply or the second power supply of a corresponding capacitance of the plurality of capacitors. A terminal voltage having a level is converted into a logic signal having a voltage level of the first power supply or the second power supply, and the logic signal obtained by the conversion is converted into a plurality of logic signals. A semiconductor device further comprising a plurality of level shifters for supplying the corresponding latch circuits of the switch circuits. 9. A semiconductor device having an internal boosting power supply for generating a power supply voltage higher than the voltage of the first power supply, and a functional block connected to the first power supply via a power supply wiring. The semiconductor device includes the power supply wiring and the second wiring so that each of the semiconductor devices operates as a smoothing capacitor.
A plurality of capacitors interposed between the power source and the power source, and a disconnection for detecting each leakage current of each of the plurality of capacitors and disconnecting each of the capacitors from the power supply wiring according to the detection result of the leakage current. A plurality of N-channel type MOS transistors interposed as switch means between the power supply wiring and a corresponding one of the plurality of capacitors; Charging means for charging each to a predetermined voltage, after the completion of the charging, to detect a change in the terminal voltage of each of the plurality of capacitors after the elapse of a predetermined time, and according to the detection result, A control means for controlling the plurality of N-channel type MOS transistors so that the respective capacitors are separated from the power supply wiring, and the control means respectively include the first power supply. And a second power supply, the first power supply according to a terminal voltage of a corresponding one of the plurality of capacitors at the time when the predetermined time has elapsed. Or a plurality of latch circuits for holding a logic signal having a voltage level of the second power supply, and a logic signal held in a corresponding latch circuit of the plurality of latch circuits, the internal boosting power supply or the Second
2. A semiconductor device comprising: a plurality of level shifters for converting into a logic signal having a voltage level of the power source and supplying the logic signals to the gates of the corresponding MOS transistors among the plurality of N-channel MOS transistors. 10. A semiconductor device having a functional block connected to a first power supply via a power supply wiring, wherein a capacitor interposed between the power supply wiring and the second power supply so as to operate as a smoothing capacitor. Switch means interposed between the power supply wiring or the second power source and the capacitance, charging means for charging the capacitance to a predetermined voltage, and for a predetermined time after the charging is completed. And a control means for detecting a change in the terminal voltage of the capacitor after a lapse of time and controlling the switch means so that the capacitor is disconnected from the power supply wiring or the second power supply according to the detection result. A semiconductor device having.