JP3371756B2 - Semiconductor substrate manufacturing method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor substrate in which a semiconductor layer for element formation is provided on a supporting substrate with an insulating film interposed therebetween.

[0002]

As a semiconductor substrate formed by forming a single crystal semiconductor layer for element formation on a substrate with an insulating film interposed therebetween, for example, an SOI (structure in which a silicon single crystal is provided as a semiconductor layer There is a Silicon On Insulator substrate. This has a structure in which an oxide film is formed on a silicon substrate to be a substrate and a silicon single crystal film is formed on the oxide film. By using such a semiconductor substrate, an insulating separation process from the substrate can be performed. It is not necessary to carry out separately, the separation performance is good, and it is possible to form an integrated circuit by forming elements on a silicon single crystal film with a high degree of integration.

In this case, there are various conventional methods for producing a silicon single crystal film provided on an SOI substrate. Among them, the semiconductor thin film production is performed through the following three steps. The technology is JP-A-5-211128.
Is disclosed in. Below, the manufacturing method is shown in FIG.
2 is used for the explanation.

First, in the first step, hydrogen gas or a rare gas is ionized into the semiconductor substrate 1 and accelerated and injected at a predetermined injection energy (see FIG. 12 (a)) to obtain the surface of the semiconductor substrate 1. The ion-implanted region 2 is formed so that the implanted ions are distributed to a predetermined depth from. Next, as a second step, the support substrate 3 formed of at least one rigid material is bonded to the ion-implanted surface 1a of the semiconductor substrate 1 by a bonding method or the like (see FIG. 2B). ). In this case, the supporting substrate 3 can be a semiconductor substrate, and in terms of finally forming an SOI substrate, it is desirable to keep the insulating film 4 such as an oxide film formed.

Next, as a third step, a heat treatment is performed in a state where the semiconductor substrate 1 and the supporting substrate 3 are bonded to each other, so that the semiconductor is bounded by the microvoids P formed in the ion implantation region 2. The SOI substrate 6 having a structure in which the substrate 1 and the thin film portion are separated so as to be separated, and the silicon single crystal film 5 is bonded onto the support substrate 3 with the insulating film 4 interposed therebetween.
Are formed (see FIG. 7C).

In reality, since the peeled surface has irregularities of about several nm, the peeled surface P is subjected to polishing treatment, etching treatment, etc. to finish the silicon single crystal film 5 flat and a predetermined film. The SOI substrate 6 is formed by adjusting the thickness (for example, 0.1 μm) (see FIG. 3D).

By the way, these techniques have a semiconductor substrate 1 formed of a single material and having a flat surface, or a multilayer film structure in which various materials are uniformly laminated on the semiconductor substrate 1. Although it is suitable in the case of a configuration, for example, when a plurality of laminated materials are partially arranged on the surface of the semiconductor substrate 1 to form a pattern, or when there is a step on the surface of the semiconductor substrate 1, Causes the following problems.

That is, in the semiconductor substrate 1 having the above-described pattern structure formed therein, when ions are implanted from the surface thereof, the ion is introduced into the semiconductor substrate 1 due to the influence of the pattern structure due to a difference in material, a step, or the like. The implantation depth of is different depending on the in-plane position. As a result, when the delamination step is performed with the support substrate 4 bonded together, delamination is performed along the surface of the ion implantation region affected by the pattern structure, and thus the delaminated surface becomes a step in the ion implantation region. It becomes a state having a corresponding step.

Therefore, the surface of the silicon single crystal film 5 obtained at the time of peeling is a surface having a step. It is not impossible to flatten the peeled surface thus obtained by a polishing step, but the step initially remaining on the peeled surface is the thickness of the silicon single crystal film 5 that is finally left by polishing. The size of the silicon single crystal film 5 may be several times larger than the size (for example, about 0.2 μm in the polishing step), and it is difficult to flatten the size by polishing, and the film thickness of the silicon single crystal film 5 may be parallel. It is very difficult to polish accurately while maintaining the above, resulting in a high cost.

In other words, in order to perform the ion implantation process in the state where the step is formed on the semiconductor substrate 1 to form the defect layer region to be the delamination surface and to perform the delamination, the ions implanted in the plane Since the implantation depth of the implantation material differs depending on the pattern structure, it is difficult to make the peeling surface flat, which is not practically applicable.

The present invention has been made in view of the above circumstances. An object of the present invention is to provide a substrate on which a pattern structure is formed by a film forming process, an etching process, or the like on the side of a substrate to be bonded. When the whole or a part of the thin film is peeled off to a desired thickness, it is bonded to the supporting substrate with the flatness of the peeled surface being secured.
It is an object of the present invention to provide a method for manufacturing a semiconductor substrate that can form a semiconductor substrate such as an I substrate.

[0012]

According to the invention of claim 1, in the pattern structure forming step P1, a pattern for forming an element is formed as a semiconductor substrate (11) to be manufactured.
The semiconductor layer (14) having the portion (15a) is provided , and the ion implantation layer (19) formed in the ion implantation step P2 due to the pattern portion (15a) is formed in the semiconductor layer substrate (17). If there is a step, the pattern part (1
A region to be a dummy pattern portion (15b) having the same layer structure as the pattern portion is provided in a region where 5a) is not formed.

[0013] Thus, in the subsequent ion implantation process P2, the pattern structure (15) injected into a predetermined ion from the pattern structure (15) side to the semiconductor layer substrate formed (17) is ion An injection layer (19) is formed. This ion-implanted layer (19) is used for the semiconductor layer substrate (1
In distribution of the implanted ions with respect to the depth direction of 7) it does not depend on the shape of the pattern structure (15), so that injection layer ions are distributed substantially in the same plane (19) is formed. As a result, in the peeling step P4, the peeling can be performed on the flat surface P, and the subsequent peeling surface polishing step (P5).
Through this, it becomes possible to obtain a highly accurate thin film element-forming semiconductor layer (14).

According to the invention of claim 2, the pattern portion (1
5a) formed by one semiconductor layer (14)
In this case, since the pattern structure forming step (P1) is performed so that the dummy pattern portion (15b) is additionally provided to the pattern portion (15a), the ion implantation step (P2)
Then, the ion-implanted layer (19) can be formed on substantially the same surface, whereby the separation surface P can be formed as a flat surface.

According to the third aspect of the invention, the device forming pattern is formed.
A plurality of semiconductor layers (14a, 14b) having turn parts
When forming , each pattern part (21a, 23a, 24
As the semiconductor layer in the dummy pattern portion corresponds to a region which becomes a) (21b, 23b, so to implement the pattern structure formation step (P1) so as to provide by adding a region serving as 24b), an ion implantation process (P2 ), The ion implantation layer (1
9) can be formed on substantially the same surface, whereby the peeling surface P can be formed as a flat surface.

According to the invention of claims 4 to 6, when the pattern portions (21a, 23a, 24a) are provided on all of the plurality of semiconductor layers (14a, 14b), the respective pattern portions (21a, 23a). , 24a), the dummy pattern portions (21b, 23b, 24b) are provided. Therefore, the pattern portions (21a, 23b) corresponding to the structures of the elements formed in the semiconductor layers (14a, 14b) are formed.
a, even when setting the size and shape of 24a), a dummy pattern portion (21b corresponding thereto in a pattern structure formation step P1, 23b, so providing a region serving as 24b), substantially the same ion implantation layer (19) It can be formed on a flat surface, and the flatness of the peeling surface P is increased to increase the semiconductor layer (14a,
14b) can be accurately formed.

According to the invention of claim 7, the pattern portion (15a, 2) of the pattern structure (15, 21, 23, 24).
1a, 23a, 24a), when a step is formed on the surface, in the pattern structure forming step P1, the dummy pattern portion (15) is formed so as to eliminate the step.
b, 21b, 23b, 24b), the ion-implanted layer (19) can be formed on substantially the same surface, and the flatness of the separation surface P can be increased to form the semiconductor layers (14a, 14b) with high accuracy. it can.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to FIGS.
Will be described with reference to. FIG. 1 shows a schematic cross section of an SOI substrate 11 which is a semiconductor substrate according to the present invention. Its structure is such that an oxide film 13 as an insulating film is formed on a base silicon substrate 12 as a supporting substrate. A single crystal silicon film 14 which is a semiconductor layer is formed. This single crystal silicon film 14 forms a pattern structure 15 .
It is formed into a large number of islands,
As shown in FIG. 2, when viewed in a plan view, square regions are arranged.

In this case, the pattern structure 15 should be formed.
And the portion corresponding to the area for forming the element is the pattern portion 1
5a (area not shaded in the figure), and a dummy pattern portion 15b (area shaded in the figure) corresponding to a region not directly used for element formation
It is provided as.

This is as shown in FIG.
5a has, for example, one element formed therein, and is electrically connected by the wiring pattern 16. The dummy pattern portion 15b is not formed with an element, and therefore is electrically connected by the wiring pattern 16. Absent. In addition, the above-mentioned pattern portion 15a and the dummy pattern portion 1
The dimension of 5b is, for example, about 10 μm × 10 μm, and the width dimension of the oxide film 13 separating these is set to about 0.5 μm.

The SOI substrate 11 in the present embodiment, for example, the pattern portion 15a in which the semiconductor layer 14 is formed,
A predetermined semiconductor element is formed through the element forming step, and wiring is formed by the wiring pattern 16 to form a circuit. As a result, each semiconductor element can be formed in a state of being insulated by the oxide film 13. It is possible to obtain an integrated circuit having excellent characteristics.

Next, a method of manufacturing the SOI substrate 11 having the above structure will be described with reference to FIGS. FIG. 3 schematically shows the flow of the whole process for manufacturing the SOI substrate 11. First, the pattern structure forming process P is performed.
At 1, the pattern structure 15 is formed on the single crystal silicon substrate 17 which is the semiconductor layer substrate. FIG. 4A schematically shows a cross section of a single crystal silicon substrate 17 which is a semiconductor layer substrate. A photoresist 18 is applied to the surface of the single crystal silicon substrate 17 and patterned by photolithography. The portions exposed in the lattice form are etched by an etching process to form the concave portions 17a. Next, the photoresist 18 is peeled off to form a silicon oxide film 13 as an insulating film on the surface (see FIG. 3B).
The width dimension of the concave portion 17a is 0.5 μ as described above.
It is set to about m.

Subsequently, an ion implantation step P2 (see FIG. 3)
Then, ion implantation is performed from the surface of the single crystal silicon substrate 17 on which the oxide film 13 is formed under predetermined conditions. Ions to be implanted are those obtained by ionizing hydrogen gas or rare gas. Here, the case where hydrogen ions H ⁺ (protons) are used is shown, and these ions are accelerated at a predetermined acceleration energy and then implanted. The implantation amount (dose amount) at this time is 1 × 10.
It is set to about ¹⁶ to 1 × 10 ¹⁷ atoms / cm ² . As a result, the ion implantation layer 19 is formed at a predetermined depth deeper than the bottom surface of the recess 17a (see FIG. 4C).

Next, in the bonding step P3, the surface side of the oxide film 13 of the single crystal silicon substrate 17 and the base silicon substrate 12 are bonded, and a heat treatment for bonding is performed at a temperature of, for example, about 500.degree. Perform (see FIG. 5A). After that, in the peeling step P4, heat treatment is performed at a high temperature in order to increase the bonding strength of the above-mentioned bonding and peeling. In this case, the heat treatment temperature is preferably 1
60 above 100 ° C, more preferably around 1150 ° C
Do about a minute. At this time, bonding with the base silicon substrate 12 and peeling occur in the peeling defect layer region formed in the ion implantation region 19 (see FIG. 5B).

As described above, the bonding step P3
Instead of performing the two-step heat treatment in each of the peeling process P4 and the peeling process P4, the heat treatment may be performed once for the purpose of simplifying the process. In this case, the heat treatment temperature is preferably 1100 ° C. or higher, and more preferably about 1150 ° C. for about 60 minutes, so that the peeling can be performed in the peeling defect layer region.

Next, in the peeling surface polishing step P5, a polishing process is performed to flatten the peeling surface P peeled in the above-described peeling step P4 (see FIG. 5C), at this time, the concave portion 17a. polishing until the oxide film 13 formed in the bottom row stomach, it is possible to form the SOI substrate 11 having a pattern structure 15 in a state in which pattern portion 15a and the dummy pattern portion 15b is separated.

By the way, in the above-mentioned technique of peeling by the ion implantation region 19, the single crystal silicon substrate 17 is used.
The hydrogen ions implanted therein are distributed in a state in which the crystal lattice has defects or the crystal lattice is distorted. At this time, the target depth of ion implantation is set to, for example, 0.
The distribution of hydrogen ions when set to about 1 μm actually widens to about 0.3 μm. But,
In the portion where the amount of implanted hydrogen ions exceeds a certain amount (threshold value), the defect layer region becomes a very narrow region with a thickness dimension of about several nm by undergoing heat treatment in the state immediately before peeling. It will be condensed.

As a result, delamination occurs in a very thin defect layer region, and the delaminated surface can be very flat. The peeling surface polishing step P5 is performed to ensure flatness and reduce the degree of surface roughness, and to form the pattern structure 15 in a separated state. In addition to the above-mentioned hydrogen, a rare gas may be used as the ions for performing such peeling, and various ions such as oxygen, chlorine, and fluorine may be considered.

Further, the SO formed in the present embodiment
When the I substrate 11 is obtained, the single crystal silicon substrate 17 is a product in which the impurity concentration is controlled to a constant value as in the case of forming a normal semiconductor device in order to ensure the quality of the single crystal silicon film 14. While it is desirable to use a wafer, the base silicon substrate 12 to be bonded is used.
As for the single crystal silicon film 17 through the oxide film 13,
It suffices to fulfill the function as a substrate for holding the substrate, so that a dummy wafer whose impurity concentration is not strictly controlled can be used.

Therefore, an inexpensive one can be used as the base silicon substrate 12, and further, the single crystal silicon substrate 17 after peeling is treated with a flattening treatment such as polishing the surface so that another SOI substrate 11 can be formed again. It can be used as a product for manufacturing, effective use of resources can be achieved, and cost can be reduced as a whole.

[0031] According to the first embodiment, in manufacturing the semiconductor substrate 11 to form a pattern structure 15, by providing the pattern portion 15a equivalent to the dummy pattern portion 15b of its ion implantation step Since the ion implantation region 19 in P2 can be formed in substantially the same plane, a step is not generated on the peeling surface P when peeling is performed in the peeling step P4, and the semiconductor layer 17 is formed with high accuracy. The SOI substrate 11 can be obtained.

(Second Embodiment) FIGS. 6 to 9 show a second embodiment of the present invention, and only portions different from the first embodiment will be described below. In the present embodiment, as shown in FIG. 6, an SOI substrate 20 as a semiconductor substrate is provided with a pattern structure 21 in place of the pattern structure 15 in the first embodiment. A state in which a polycrystalline silicon film 14b as a semiconductor layer is separately embedded in the lower layer portion of the single crystal silicon film 14a as a semiconductor layer exposed on the surface in the same configuration as that of the embodiment via an oxide film 13 as an insulating film. It has a pattern structure 21 formed in the above.

[0033] In this SOI substrate 20, each layer of a semiconductor layer of the top and bottom monocrystalline silicon film 14a and the polycrystalline silicon film 14b is formed in the same shape, the oxide film 13
It is formed in a structure having a pattern portion 21a and a dummy pattern portion 21b separated by. The pattern portion 21a of the polycrystalline silicon film 14b on the lower layer side is provided so as to be used as a back gate when the element is formed.

FIGS. 7 to 9 show respective cross sections according to the manufacturing process of the SOI substrate 20, and the schematic procedure of the manufacturing process is the same as that of the first embodiment, and is performed according to the flow shown in FIG. The process contents of the pattern structure forming process P1 will be described in detail.

That is, in the pattern structure forming step P1, the photoresist 19 is applied and patterned by photolithography, and then the recess 17a is formed by etching (see FIG. 7A).
The oxide film 13a is formed (see FIG. 11B).

Next, a polycrystalline silicon film 14b as a semiconductor layer is formed on the oxide film 13a, patterned by photolithography and then subjected to etching to form the same pattern as when the oxide film 13a was formed. A polycrystalline silicon film 14b is formed (see FIG. 7C).
Then, an oxide film 13b is formed on the entire surface so as to fill the gap between the patterns of the polycrystalline silicon film 14b (FIG. 8).
(See (a)), and make it flat.

In the next ion implantation step P2, ion implantation is performed under predetermined conditions in the same manner as in the first embodiment to form the ion implantation region 19 (see FIG. 7B). In the subsequent bonding step P3, the surface side of the oxide film 13b of the single crystal silicon substrate 17 and the base silicon substrate 12 are bonded together, and then heat treatment for bonding is performed (see FIG. 3C).
After that, in the peeling step P4, heat treatment is performed at a high temperature in order to increase the bonding strength of bonding and peeling.
At this time, the bonding with the base silicon substrate 12 and the peeling in the peeling defect layer region formed in the ion implantation region 19 occur (see FIG. 9A).

Next, in the peeling surface polishing step P5, a polishing process is performed to flatten the peeling surface P peeled in the above-described peeling step P4 (see FIG. 9B). At this time, the concave portion 17a is formed. Polishing is performed until the oxide film 13 formed at the bottom of the film is reached, and the pattern structure 15 is formed with the portions to be the single crystal silicon film 14 separated from each other.
Thereby, the SOI substrate 20 is obtained.

[0039] According to the second embodiment, a configuration made of single-crystal silicon film 14a and the polycrystalline silicon film 14b which is a semiconductor layer of a double several layers, even with a 21a a pattern portion in each layer, By forming the dummy pattern portion 21b in the pattern structure forming process P1 in the same manner as in the first embodiment, the ion implantation layer 19 in the ion implantation process P2 can be formed to the same depth, and the peeled surface can be formed. It is possible to obtain the SOI substrate 20 in which the semiconductor layers 14a and 14b are formed with high accuracy by eliminating the step difference of P.

(Third Embodiment) FIG. 10 shows a third embodiment of the present invention. The difference from the second embodiment is that the SOI substrate 20a has a single crystal silicon film 14a as a semiconductor layer. the Ri der was not be provided the pattern structure, the polycrystalline silicon film 14b formed lump padded, to form a pattern portion 21a
In addition, the dummy pattern portion 21b is formed .

The SOI substrate 20a having such a configuration
In manufacturing the pattern structure, in the pattern structure forming step P1 of the second embodiment, the recess 17a is not provided in the single crystal silicon substrate 17 which is the semiconductor layer substrate, and the oxide film 13 is formed on the flat surface. In this state, the polycrystalline silicon film 14b as a semiconductor layer is formed, and the pattern structure 2
1 is formed. Even in the third embodiment as described above, the dummy pattern portion 21b
Since this is provided, the same effect as that of the second embodiment can be obtained.

(Fourth Embodiment) FIG. 11 shows a fourth embodiment of the present invention.
The second embodiment will be described, and the points different from the second embodiment will be described. That is, the SOI in the present embodiment
The substrate 22 is a single crystal silicon film 1 which is the upper and lower semiconductor layers.
4a and the polycrystalline silicon film 14b are provided with pattern structures 23 and 24, respectively, and different pattern portions 23a and 2
4a is arranged. In this case, in the pattern structure forming step P1, each pattern portion 2
3a, 24a corresponding to the dummy pattern portions 23b, 24
b is arranged and formed.

Then, the SOI substrate 22 having such a structure
Then, for example, the pattern portion 23a is formed corresponding to the structure of the element formed in the single crystal silicon film 14a, and the pattern portion 24a is arranged and formed so that the polycrystalline silicon film 14b located on the lower layer side is used as a back gate. It was done. Further, when an element is formed by using the SOI substrate 22 as a substrate, the gate 25 is arranged in the pattern portion 23a portion of the single crystal silicon film 14a via an insulating film as shown in the figure. Can be manufactured easily and with high performance.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. In the pattern structure, the shape of the dummy pattern portion does not have to be the same as that of the pattern portion, and it is not always necessary to form cells in the same shape. For example, a dummy in which all the portions without the pattern portion are connected is connected. It may be formed as a pattern portion, and may be formed in a shape according to need.

As the semiconductor layer substrate, as a material other than silicon, if it is a single crystal mainly composed of a Group 4 element, for example, Ge (germanium), SiC (silicon carbide), SiGe (silicon germanium), diamond, or the like. The substrate of can be used. In this case, when a SiC substrate or the like is used, the substrate itself is very expensive, and therefore polishing and recycling after peeling increase the effect of effective use of resources and cost reduction.

[Brief description of drawings]

FIG. 1 is a schematic vertical cross-sectional side view of an SOI substrate showing a first embodiment of the present invention.

FIG. 2 is a diagram schematically showing an upper surface of an SOI substrate.

FIG. 3 is a process schematic diagram.

FIG. 4 is a schematic vertical sectional side view in each manufacturing process of the SOI substrate (No. 1)

FIG. 5 is a schematic vertical sectional side view in each manufacturing process of the SOI substrate (Part 2)

FIG. 6 is a view corresponding to FIG. 1 showing a second embodiment of the present invention.

FIG. 7 is a view corresponding to FIG. 4 (No. 1).

FIG. 8 is a view corresponding to FIG. 7 (No. 2).

FIG. 9 is a view corresponding to FIG. 7 (part 3).

FIG. 10 is a view corresponding to FIG. 1 showing a third embodiment of the present invention.

FIG. 11 is a view corresponding to FIG. 1 showing a fourth embodiment of the present invention.

FIG. 12 is a schematic vertical sectional side view in each manufacturing process of an SOI substrate showing a conventional example.

[Explanation of symbols]

11, 20, 20a and 23 are SOI substrates (semiconductor substrates), 12 is a silicon base substrate (support substrate), 13,
Reference numerals 13a and 13b are oxide films (insulating films), 14 and 14a are single crystal silicon films (semiconductor layers), 14b is a polycrystalline silicon film (semiconductor layers), 15, 21, 23 and 24 are pattern structures, and 15a, 21a, 23a and 24a are pattern parts, 1
5b, 21b, 23b and 24b are dummy pattern parts, 1
6 is a wiring pattern, 16a is a contact portion, 17 is a single crystal silicon substrate (semiconductor layer substrate), 18 is a photoresist, and 19 is an ion implantation layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP 10-125880 (JP, A) JP 10-199840 (JP, A) JP 7-254690 (JP, A) JP 10- 303139 (JP, A) JP-A-10-308354 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 27/12 H01L 21/20 H01L 21/265

Claims (7)

(57) [Claims] 1. In a state of being insulated on a support substrate (12)
In a method for manufacturing a semiconductor substrate (11) provided with a semiconductor layer (14) having a pattern portion for element formation, a semiconductor layer substrate (17) for forming the semiconductor layer (14) is subjected to an etching treatment. The pattern structure (1
Pattern structure forming a 5) and (P1), the pattern structure (15) is the pattern structure (15) by injecting a predetermined ion from the side of the substrate (17) for the semiconductor layer formed ion implantation An ion implantation step (P2) for forming a layer (19); a bonding step (P3) for bonding the support substrate (12) to the semiconductor layer substrate (17); and the bonded semiconductor layer substrate (P3) 17) and the supporting substrate (12) are heat-treated to form the ion implantation layer (19).
The method includes a peeling step (P4) of peeling at a part and a peeling surface polishing step (P5) of polishing the peeling surface of the supporting substrate (12), and before the formation in the pattern structure forming step (P1).
Kipa turn portion and formed by corresponds to the arrangement state of the region (15a), the ion implantation layer by providing a a region that pattern portions dummy pattern portion of the same layer structure and a region (15a) (15b) A method of manufacturing a semiconductor substrate, wherein (19) is formed in substantially the same plane. 2. The method for manufacturing a semiconductor substrate according to claim 1, wherein when the pattern portion (15a) is formed by one semiconductor layer (14), the pattern portion (1) is formed.
A method of manufacturing a semiconductor substrate, characterized in that a dummy pattern portion (15b) composed of the same semiconductor layer (14) as 5a) is provided. 3. In a state of being insulated on a supporting substrate (12)
A plurality of semiconductor layers (14 having a pattern portion for element formation)
a, 14b), a method of manufacturing a semiconductor substrate (20, 22), comprising: etching the semiconductor layer substrate (17) for forming the plurality of semiconductor layers (14a, 14b) with the pattern structure (17). and Rupa turn structure forming step to form a 21, 23, 24) (P1), the pattern structure (21, 23, 24) is formed the pattern structure on the substrate (17) for said semiconductor layer (21,
23, 24 ). Ion implantation step (P2) of implanting predetermined ions from the side of 23, 24 ) to form the ion implantation layer (19), and bonding the support substrate (12) to the semiconductor layer substrate (17) In the step (P3), the bonded semiconductor layer substrate (17) and supporting substrate (12) are heat-treated to perform the ion implantation layer (19).
A peeling step of peeling (P4) in portions, said polishing the release surface of the support substrate (12) comprises a release surface polishing step (P5), and in the pattern structure formation step (P1), before Symbol Pattern In the arrangement state of the areas that will be parts (21a, 23a, 24a)
Correspondingly , the pattern portion (21a, 23a, 24a)
Dummy pattern portion having the same layer structure as the a region (21b,
23b, 24b) is provided so that the ion implantation layer (19) is formed in substantially the same plane. 4. The method for manufacturing a semiconductor substrate according to claim 3, wherein when the plurality of semiconductor layers (14a, 14b) are provided with pattern portions (21a, 23a, 24a), the respective pattern portions are provided. The dummy pattern portions (21b, 23b, 24) corresponding to (21a, 23a, 24a)
A method of manufacturing a semiconductor substrate, characterized in that b) is provided. 5. The method of manufacturing a semiconductor substrate according to claim 3, wherein the pattern portion (21a) has a plurality of semiconductor layers (14a,
14b), the pattern portion (21a) and the dummy pattern portion (21b) formed on the upper semiconductor layer (14a) and the pattern formed on the lower semiconductor layer (14b) A method of manufacturing a semiconductor substrate, characterized in that the portion and the dummy pattern portion are provided so as to have the same shape in plan view. 6. The method of manufacturing a semiconductor substrate according to claim 3, wherein the pattern portions (23a, 24a) are provided.
When the semiconductor layer is formed over a plurality of semiconductor layers (14a, 14b), the pattern portion (23) of the upper semiconductor layer (14a) is formed.
a) and the dummy pattern portion (23b), and the pattern portion (24a) formed in the underlying semiconductor layer (14b).
And a method of manufacturing a semiconductor substrate, wherein the dummy pattern portion (24b) and the dummy pattern portion (24b) are provided so as to have a different shape in plan view. 7. The method of manufacturing a semiconductor substrate according to claim 1, wherein in the pattern structure forming step (P1), a region to be the pattern portion (15a, 21a, 23a, 24a) and a dummy. Pattern part (15b, 21b, 23b, 24
b) a step on the surface of the pattern structure having a region
A method for manufacturing a semiconductor substrate, which is solved by forming an insulating film (13).