JP3371463B2 - Detection circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a detection circuit applied to, for example, a non-contact type IC card for reading / writing data by microwave.

[0002]

2. Description of the Related Art An IC card has a microprocessor, that is, a central control unit and an arithmetic unit in a microcomputer, and a built-in LSI and IC memory in which a single silicon substrate is incorporated, and has an information processing function. Therefore, it is expected to be widely used because it has the characteristics of being versatile and multifunctional, and being difficult to steal or forge.

An IC card is a contact type which is connected to an external device through a conductive terminal provided on the card, and a contact portion is made non-contact to exchange data by radio waves or light. There is a non-contact type that is used. Contact type I
The C card has the inconvenience such as contact failure due to wear and dirt on the contacts, which makes it impossible to exchange data, whereas the non-contact type IC card has no such inconvenience and is relatively close. There is an advantage that good data can be transmitted and received in the distance.

A non-contact type IC card generally has a built-in battery, and an oscillating circuit, a control circuit, a storage section and the like inside the card are operated based on the voltage of the battery. For example, the control circuit is based on a reference signal from the oscillating circuit. The collation information stored in the storage unit is output.

By the way, in a non-contact type IC card using radio waves, since data reading / writing operations are performed by microwaves, a circuit for detecting with high sensitivity and low power consumption is required.

Various circuits have been conventionally proposed as a detection circuit. Among these circuits, the power consumption is 10
A diode detection circuit that consumes no power in principle is known as one having a power consumption of μW or less.

[0007]

However, since the above-mentioned diode detection circuit requires an input amplitude of the threshold voltage V _{TH of the} transistor, for example, 0.7 V or more, it is necessary to realize highly sensitive detection. Is difficult.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a detection circuit capable of detecting with high sensitivity and low power consumption.

[0009]

In order to achieve the above object, the detection circuit of the present invention is different from the first and second MOS transistors whose drain and gate are connected to each other.
A first and second MOS having a dynamic amplifier and a current source
The middle point of connection between the drain and gate of the transistor is connected to the current source, the gate of the first MOS transistor is connected to the signal input line, and the first and
The source of the second MOS transistor is the power supply voltage supply source.
Connected to the input, one input of the differential amplifier is
Between the drain and gate of one MOS transistor
Connected to the connection midpoint and the connection midpoint between the current source and the other
The input is the drain of the second MOS transistor and
Connected to the midpoint between the gates and the midpoint between the current sources
And the current capability of the second MOS transistor is set to be larger than that of the first MOS transistor.

[0010]

In the present invention, a first resistance element for reducing the capacitance to ground seen from the input is connected between the current source and the connection midpoint between the drain and gate of the first MOS transistor. A second resistance element for reducing the capacitance to ground seen from the input is connected between the connection point between the drain and gate of the second MOS transistor and the current source.

According to the present invention, the first capacitor for helping to average the drain current is connected to the connection midpoint between the drain and gate of the first MOS transistor and the connection midpoint between the current source. And the second MOS
A second capacitor for assisting in averaging the drain current was connected to the connection midpoint between the drain and gate of the transistor and the connection midpoint between the current sources.

[0013]

[0014]

According to the present invention, the same bias current is supplied from the current source to the first and second MOS transistors when no signal is input without an RF signal input. Current capability is the first MO
Since it is set to be larger than the current capability of the S transistor, the current source and the first MOS are
The relationship between the voltage V _{1 at} the connection midpoint between the gate and drain of the transistor and the voltage V _{2 at} the connection midpoint between the current source and the gate and drain of the second MOS transistor is V
And it has a _1> V _2. When an RF signal is input to the detection circuit in such a state, the output current is greatly distorted due to the non-linear characteristic of the MOS, but the current source and the first MOS are arranged so that the average value thereof matches the above-mentioned bias current. Voltage V _{1 at the} midpoint of connection with the gate and drain of the transistor
DC voltage drops. That is, the operating point drops.
Then, when an RF input amplitude that satisfies V ₁ <V ₂ is applied, the output level of the differential amplifier arranged in the output stage is inverted, and the current change is extracted as a voltage change.

Further, according to the detection circuit of the present invention using one MOS transistor, the voltage Vd at the midpoint of connection between the current source and the drain of the MOS transistor is determined by the current source when there is no RF signal input and no signal is input. Current supplied and M
Due to the current difference from the current Id flowing through the OS transistor,
It is almost stuck to the power supply voltage V _DD . If, for example, an RF signal is input to the detection circuit in such a state, M
The gate voltage Vg of the OS transistor has a predetermined value.
Further, the average potential of the gate voltage Vg remains the bias voltage, but when the current Id of the MOS transistor is averaged, it increases from Id when there is no signal due to the non-linear characteristic of the MOS. When the average current of the current Id of the MOS transistor becomes larger than the current capability of the current source, the difference current causes the voltage Vd at the midpoint of connection between the current source and the drain of the MOS transistor to drop to almost the same level as V _SS. Become. The change in the voltage Vd at the midpoint of connection is taken out through an inverter arranged in the output stage.

FIG. 1 shows an embodiment of a detection circuit according to the present invention.
It is a circuit diagram which shows the basic composition of (Example 1) . In FIG. 1, Q ₁ and Q ₂ are n-channel MOSs (hereinafter referred to as nMOSs).
Transistor), I _e1 and I _e2 are constant current sources having the same characteristics, AMP is a differential amplifier, Cin is a capacitor, V
_SS indicates the power supply voltage.

The source of the nMOS transistor Q ₁ is connected to the supply line of the power supply voltage V _SS , and the gate is connected to the input terminal DI via the capacitor Cin and also to the drain. The midpoint of the connection between the gate and drain of the nMOS transistor Q ₁ is connected to the constant current source I _e1 and one input end of the differential amplifier AMP. nM
The source of the OS transistor Q ₂ is the supply line of the power supply voltage V _SS .
The gate is connected to the drain, and the midpoint of the connection between the gate and the drain is connected to the constant current source I _e2 and the other input end of the differential amplifier AMP. The output of the differential amplifier AMP is connected to the output terminal DO.

In such a structure, the current capacity of the nMOS transistor Q ₂ is set to be larger than that of the nMOS transistor Q ₁ . Specifically, nMO
The channel width of the S transistor Q ₂ is set to be twice the channel width of the nMOS transistor Q ₁ .

Next, analysis of the operating point in the configuration of FIG.
Is performed based on FIG. First, there is no RF signal input
NMOS transistor Q₁And Q ₂Against
Then, the constant current source I_e1, I_e2The same bias current I
₁, I₂Is being supplied, but as described above, nM
OS transistor Q₁, Q₂Depending on the current capacity difference of
Source I_e1And nMOS transistor Q₁Gates and doors
The voltage V at the connection midpoint A with the rain₁And constant current source I_e2And M
OS transistor Q₂Gate and drain connection
Voltage V at midpoint B₂As shown in Fig. 2 (a),
In addition, V1> V2. That is, the differential amplifier A
The input level of one input of MP and the other input is V₁>
V₂Are satisfied with the relationship.

In the detection circuit in such a state, the input terminal D
When the RF signal is input via I, the output current is MOS
However, as shown in FIG. 2B, the DC voltage of the voltage V _{1 at} the connection midpoint A drops so that its average value matches the bias current described above. That is, the operating point drops. Then, when the RF input amplitude that satisfies V ₁ <V ₂ is applied, the output level of the differential amplifier AMP is inverted.

FIG. 3 is a diagram showing a concrete circuit configuration example of the detection circuit of FIG. 1, and the same elements as those in FIG. 1 are represented by the same reference numerals. That is, Q ₁ and Q ₂ are nM
OS transistors, P ₁ , P ₂ , P ₃ are pMOS transistors forming a constant current source, AMP is a differential amplifier, Ci
n, C ₁ and C ₂ are capacitors, R ₁ , R ₂ and R ₃ are resistance elements, and V _DD and V _SS are power supply voltages.

In FIG. 3, pMOS transistor P ₁
The sources of P ₃ to P ₃ are connected to, for example, the supply line of the power supply voltage V _DD , the respective gates are connected to each other, and the gate of the pMOS transistor P ₃ is connected to the differential amplifier AMP. The drain of the pMOS transistor P ₁ is connected to a connection midpoint A with one input of the differential amplifier AMP, and a resistance element is provided between the connection midpoint A and the midpoint of connection between the gate and drain of the nMOS transistor Q _1. R ₁ is connected. Further, a capacitor C ₁ is connected between the connection line between the connection midpoint A and one input of the differential amplifier AMP and the ground.

The drain of the pMOS transistor P ₂ is connected to the middle point B of connection with the other input of the differential amplifier AMP, and between the middle point B of connection and the middle point of connection between the gate and drain of the nMOS transistor Q _2. Resistance element R ₂
Are connected. Also, the connection midpoint B and the differential amplifier AM
A capacitor C ₂ is connected between the connection line of the other input of P and the ground. The drain of the pMOS transistor P ₃ is connected to the gate and the resistance element R
Grounded through ₃ .

The resistance elements R ₁ and R ₂ are capacitors C ₁ and C _{2 in} order to reduce the capacitance to ground seen from the input.
Are provided to help average the drain currents of the nMOS transistors Q ₁ and Q ₂ .

Next, the input sensitivity of the detection circuit according to this embodiment will be considered with reference to FIG.

The minimum input amplitude will be calculated below.

[Equation 1] Where V0 is the bias voltage when there is no signal, {Vm cos
(Ωt)} is the RF input signal, dV is D when the RF signal is input
The C bias drops are shown respectively.

In the above equation (1), (V0 + dV) <
When reaching V ₂ , the output level of the differential amplifier AMP is inverted. Considering the offset of the differential amplifier AMP, the DC bias drop dV at the time of inputting the RF signal needs to be at least about 60 mV. Therefore, the input amplitude that causes the DC bias drop of 60 mV becomes the minimum RF level.

By the way, since the nMOS transistor Q ₁ in the input stage is self-biased near its threshold voltage V _TH , the so-called exponentia is given by the following equation.
l Operates with characteristics.

[Equation 2] Here, k is the Boltzmann constant, T is the absolute temperature, and q is the charge.

By substituting the equation (1) into the equation (2), the current I ₁ at the time of no signal and at the time of RF input is as follows.

[Equation 3]

[Equation 4]

Then, in the detection circuit of FIG.
DV is generated such that the average value of the equation (4) matches the equation (3). Therefore, Vm at which dV becomes 60 mV may be obtained.

From the expressions (3) and (4), the following relational expression is established.

[Equation 5] By substituting f (Vm / E) for the term including the integral on the right side of the equation (5), the following relational expression is obtained.

[Equation 6]

When the replaced f (Vm / E) is expanded, it becomes as follows.

[Equation 7]

Therefore, the above equation (6) can be rewritten as the following equation.

[Equation 8]

FIG. 4 is a diagram showing a result of calculating a DC bias drop dV by substituting an appropriate Vm into the equation (8). As can be seen from FIG. 4, in order to obtain a DC bias drop of 60 mV or higher, an input amplitude of 150 mV or higher is sufficient. This means that the input sensitivity is improved by 10 dB or more as shown below as compared with diode detection which requires an input amplitude of V _TH (for example, 0.7 V) or more. 20 log (0.7 / 0.15) = 13.4 dB

A current of 0.1 μA flows in each of the detection stage, the reference stage, the bias generation stage, and the differential amplifier, and a total of 0.4 μA is consumed. Therefore, looking at the power consumption Pd, the power supply voltage of 3V is 1.2μ.
The power consumption becomes W, and ultra-low power consumption comparable to diode detection can be realized.

As described above, according to this embodiment,
Since the non-linearity of the MOS transistor, which operates with exponential characteristics when the MOS transistor is biased near the threshold voltage V _TH , is used, and the bias current is suppressed to a low level, microwaves with high sensitivity and low power consumption are provided. It is possible to realize a high-frequency detection circuit that can detect Therefore,
There is an advantage that an IC card that reads / writes data by microwave can be realized. The detection stage is
The bias voltage is slightly moved by the RF input (100
(about mV), the detection response speed is fast.

FIG. 5 is a circuit diagram showing the basic structure of a reference example of the detection circuit according to the present invention.

The present embodiment is different from the first embodiment, a configuration that the small input voltage in the first embodiment is converted as a large current change, as further converted into a voltage change by using a differential amplifier On the other hand, in this reference example, the current change is directly detected. In FIG. 5, Q ₃ is an nMOS transistor, I _e1 is a constant current source ,
C in is a capacitor, V _B is a constant voltage source, R _B is a resistance element,
INV indicates an inverter, and V _SS indicates a power supply voltage.

The source of the nMOS transistor Q ₃ is connected to the supply line of the power supply voltage V _SS , the gate is connected to the input terminal DI via the capacitor Cin, and the drain is connected to the constant current source I _e1 and the input terminal of the inverter INV. Has been done. Further, a constant voltage source V _B and a resistance element R _B are connected in series between the gate and the connection line between the source of the nMOS transistor Q ₃ and the supply line of the power supply voltage V _SS . The output of the inverter INV is connected to the output terminal DO.

Next, analysis of the operating point in the configuration of FIG. 5 will be performed based on FIG. In addition, in the configuration of FIG.
It is assumed that the constant current source I _e1 is a constant current element having a supply current I ₁ of 80 nA and the nMOS transistor Q ₃ is a constant current element having a current Id of 50 nA flowing when there is no signal, and its static characteristics are as shown in FIG. 6A.

First, when there is no RF signal input and there is no signal,
The voltage Vd at the connection midpoint C between the constant current source I _e1 and the drain of the nMOS transistor Q ₃ is the current I ₁ (80 nA) supplied by the constant current source I _e1 and the nMOS transistor Q ₃
Due to the current difference (30 A) from the current Id (50 nA) flowing through the current Id, it is almost stuck to the power supply voltage V _DD .

In the detection circuit in such a state, the input terminal D
When the RF signal is input via I, the gate voltage Vg of the nMOS transistor Q ₃ is given by the following equation.

[Equation 9] Where VB is the bias voltage, Vm is the RF amplitude, and {Vm
cos (ωt)} indicates the RF input signal.

Average potential of this gate voltage Vg

[Equation 10] Is still the bias voltage VB, but when the current Id of the nMOS transistor Q ₃ is averaged, it increases from Id (Ib) when there is no signal due to the non-linear characteristic of the MOS.

[0044] As shown in FIG. 6 (b), the average current of the current Id of the nMOS transistor Q ₃ is, the larger than the current capability 80nA of the constant current source I _e1, constant current source I _e1 and nMOS by the difference current The voltage Vd at the connection midpoint C with the drain of the transistor Q ₃ drops and becomes almost the same level as the power supply voltage V _SS . The change in the voltage Vd at the connection midpoint C is output through the inverter INV.

FIG. 7 is a diagram showing a specific circuit configuration example of the detection circuit of FIG. 5, and the same elements as those of FIG. 5 are represented by the same reference numerals. That is, Q ₃ and Q ₄ are nM
OS transistors, P ₁ , P ₂ , P ₃ are pMOS transistors forming a constant current source, INV is a differential amplifier, Ci
n and C ₃ are capacitors, R ₃ and R ₄ are resistive elements, V _DD ,
V _SS indicates the power supply voltage.

In FIG. 7, the pMOS transistor P ₁
The sources of P ₃ to P ₃ are connected to, for example, the supply line of the power supply voltage V _DD , the respective gates are connected to each other, the gate of the pMOS transistor P ₃ is connected to the drain, and the connection midpoint is grounded via the resistance element R _3. Has been done. The drain of the pMOS transistor P ₁ is connected to the drain of the nMOS transistor Q ₃ , and the connection midpoint C thereof is connected to the input of the inverter INV.

The drain of the pMOS transistor P ₂ is n
Connected to the drain of the MOS transistor Q ₄ ,
The drain of the nMOS transistor Q ₄ is connected to the gate of the nMOS transistor Q ₄ , and the midpoint of the connection is the nMOS via the resistance element R _4.
It is connected to the gate of transistor Q ₃ and
It is connected to the supply line of the power supply voltage V _SS via the capacitor C ₃ . The source of the nMOS transistor Q ₄ is connected to the supply line of the power supply voltage V _SS .

In FIG. 7, the nMOS transistor Q
₃And pMOS transistor P₁The detection stage consists of
NMOS transistor Q_Four, PMOS transistor
Type P ₂, Resistance element R_FourAnd capacitor C₃By
Asbestos generation stage is configured.

Next, the input sensitivity of the detection circuit according to the present reference example will be considered with reference to FIG.

Since the nMOS transistor Q _{1 in the} input stage is self-biased near its threshold voltage V _TH , it operates with so-called exponential characteristics as shown in the following equation. Therefore, the characteristic of the nMOS transistor Q ₃ is expressed by the following equation.

[Equation 11]

[Equation 12]

By substituting the equation (11) into the equation (12), the current Id is as follows.

[Equation 13] Here, Ib represents the bias current when there is no signal.

Average current Id of current Id Is given by the following equation.

[Equation 14] That is,

[Equation 15] Becomes

This (Id / Ib) is about twice, in this example, about 100 nA, the output is inverted. Therefore, by calculating f (Vm / E),
Know the minimum input amplitude.

[Equation 16]

FIG. 8 is a diagram showing the result of calculating the relationship between the input amplitude and the current ratio by substituting numerical values into this equation (16). As can be seen from FIG. 8, about 70 mV is required as Vm in order to obtain the double current ratio. This means that the input sensitivity is improved by 20 dB or more as shown below as compared with the diode detection that requires an input amplitude of V _TH (for example, 0.7 V) or more. 20log (0.7V / 70mV) = 20dB

Further, a current of 0.1 μA flows in the current source,
A current of 50 nA flows in each of the detection stage and the bias voltage generation stage, consuming 0.2 μA in total. Therefore, looking at the power consumption Pd, it is assumed that the power supply voltage is 1.5V and the power consumption is 0.5V.
The power consumption is 3 μW, and ultra-low power consumption comparable to diode detection can be realized.

As described above, according to this reference example,
In addition to suppressing the bias current to a low level, a simple circuit configuration without using a differential amplifier etc. enables low-voltage operation (about 1.5 V) and high-sensitivity detection. Of course, it is possible to realize a detection circuit with ultra-low power consumption of 0.3 μW.

[0057]

As described above, according to the present invention,
It is possible to realize detection with high sensitivity and low power consumption. Therefore, there is an advantage that an IC card that reads / writes data by microwave can be realized.

[Brief description of drawings]

1 is a circuit diagram showing the basic structure of the real施例of the detection circuit according to the present invention.

FIG. 2 is an explanatory diagram of an operating point analysis of FIG.

FIG. 3 is a diagram showing a specific circuit configuration example of the detection circuit of FIG.

FIG. 4 is a diagram showing a result of calculating a DC bias drop amount dV of the circuit of FIG.

FIG. 5 is a circuit diagram showing a basic configuration of a reference example of a detection circuit according to the present invention.

FIG. 6 is an explanatory diagram of the operating point analysis of FIG.

7 is a diagram showing a specific circuit configuration example of the detection circuit of FIG.

8 is a diagram showing the result of calculation of the relationship between the input amplitude and the current ratio of the circuit of FIG.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03D 1/00-1/08 H03D 1/18

Claims (3)

(57) [Claims] 1. A connection between drains and gates of first and second MOS transistors, comprising first and second MOS transistors having drains and gates connected to each other, a differential amplifier, and a current source. The midpoint is connected to the current source, the gate of the first MOS transistor is connected to the signal input line, and the sources of the first and second MOS transistors are electrically connected.
The differential amplifier is connected to the supply line of the source voltage and one input of the differential amplifier is connected to the first MOS transistor.
The middle point of connection between the drain and gate of the transistor and the above
It is connected to the middle point of the connection with the source and the other input is connected to the second
Connection between drain and gate of MOS transistor
A detection circuit connected to a midpoint between a midpoint and the current source, wherein the current capability of the second MOS transistor is set larger than the current capability of the first MOS transistor. 2. Between the connection midpoint between the drain and gate of the first MOS transistor and the current source,
A first resistance element for reducing the capacitance to ground seen from the input is connected, and a pair seen from the input is provided between the midpoint of connection between the drain and gate of the second MOS transistor and the current source. The detection circuit according to claim 1, wherein a second resistance element for reducing the ground capacitance is connected. 3. A first for assisting in averaging the drain current with respect to a connection midpoint between the drain and gate of the first MOS transistor and a connection midpoint between the current source.
Of the second MOS transistor is connected, and a second capacitor for helping the averaging of the drain current is connected to the connection midpoint between the drain and gate of the second MOS transistor and the connection midpoint between the current source. The detection circuit according to claim 1 or 2.