JP3370227B2 - Associative memory - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention includes a plurality of memory words for storing respective data, and a function of searching for a match / mismatch between data stored in each memory word and input search data. Associative memory (As
sociative Memory, Content Addressable Memory; Content Ad
dressable memory).

[0002]

2. Description of the Related Art In recent years, an associative memory having the above search function has been proposed. FIG. 5 is a circuit block diagram showing an example of a conventional associative memory. This associative memory 1
0 is provided with a large number of memory words 11a, 11b, ..., 11n composed of a plurality of memory cells arranged in the lateral direction of the drawing. The associative memory 10 also includes a search register 12 into which search data is input and latched. The search data latched in the search register 12 has a bit pattern of all or a predetermined part thereof and each memory word 11.
Of the data stored in a, 11b, ..., 11n, the bit pattern of the corresponding portion is compared with the bit pattern of the corresponding portion, and each memory word 11a, 11 is compared.
, 11n corresponding to the memory words 11a, 11b, ..., 11n whose bit patterns match among the match lines 14a, 14b ,. A match signal of logic "1" is output to 14n, and the other match lines 14a, 14
A mismatch signal of logic "0" is output to b, ..., 14n.

Here, each flag line 14a, 14b, ...
14n are '0', '1', '0', '0',
It is assumed that signals of "1", ..., "0" have been output. This signal is input to the priority encoder 15 and the priority encoder 15 has the highest priority among the match lines (here, the match line 14b and the match line 14e) from which the match signal of logic "1" is output. The address signal AD corresponding to the highest priority match line is output. Here, the younger the subscript, the higher the priority. Therefore, the match line 14b is the highest priority match line here. The address signal AD corresponding to the highest priority match line 14b output from the priority encoder 15
Are input to the address decoder 16 as needed. The address decoder 16 decodes the input address signal AD to decode each of the memory words 11a and 11a.
Of the word lines 17a, 17b, ..., 17n provided corresponding to each of b, ..., 11n, any one of the word lines corresponding to the input address signal AD (here, the word line 17b). An access signal (here, a signal of logic “1”) is output to. This causes the memory word 1 corresponding to the word line 17b to which the access signal is output.
The data stored in 1b is read to the output register 18.

As described above, the associative memory 10 uses search data to generate a large number of memory words 11a, 11b, ...
It is a memory that can retrieve the contents (data) stored in 1n, obtain the address of the memory word in which the matching data is stored, and read the entire data stored in that memory word. FIG. 6 is a detailed circuit diagram showing one memory word in the associative memory.

The memory word 11 is composed of n memory cells 11-1, 11-2, ..., 11-n having the same structure. Each memory cell 11-1, 11-2, ...,
11-n include first inverters 20-1, 20-2, ..., 20-n and second inverters whose outputs are connected to their inputs.
, 21-n of the inverters 21-1, 21-2, ..., 21-n, and these inverters 20-1, 21-1;
20-2, 21-2; ...; 20-n, 21-n provide 1-bit information of logic "1" or logic "0" to each memory cell 11-1, 11-2, ..., 11-n. Remembered.

Further, each memory cell 11-1, 11-2,
, 11-n, the first inverters 20-1, 20
The outputs of −2, ..., 20-n are transmitted through the N-channel transistors 22-1, 22-2 ,.
, 23-n, and the gates of the transistors 22-1, 22-2, ..., 22-n are connected to the word line 24. The outputs of the second inverters 21-1, 21-2, ..., 21-n are
N-channel transistors 25-1, 25-2, ..., 2
Bit bar lines 26-1, 26-2, ...
26-n connected to this transistor 25-
The gates of 1, 25-2, ..., 25-n are also connected to the word line 24. Further, each memory cell 11-1, 11-
2, ..., 11-n have bit lines 23-1, 23-2,
23-n and bit bar lines 26-1, 26-2 ,.
26-n and two N-channel transistors 27-1 and 28- connected in series to each other so as to connect the same to 26-n.
1; 27-2, 28-2; ...; 27-n, 28-n are arranged, and each of these two transistors 27-1,
28-1; 27-2, 28-2; ...; 27-n, 28-
one of the transistors 27-1, 27-2,
The gate of 27-n is connected to the first inverter 20-1,
Outputs of 20-2, ..., 20-n, other transistor 2
The gates of 8-1, 28-2, ..., 28-n are connected to the outputs of the second inverters 21-1, 21-2 ,.

The match line 14 is connected to each memory cell 11-
1, 11-2, ..., 11-n are provided with transistors 36-1, 36-2, ..., 36-n one by one, and these transistors 36-1, 36-2 ,. ，
36-n are connected in series with each other, and each gate of the transistors 36-1, 36-2, ..., 36-n has two transistors 27-1, 28-1;
2, 28-2; ...; 27-n, 28-n are connected to the midpoint.

Further, another transistor 36-0 is connected in series to the match line 14, and the left end of the match line 14 in FIG. 6 is grounded through the transistor 36-0. The gate of the transistor 36-0 is connected to the control line 30. FIG. 6 of the match line 14
A sensing inverter 31 is arranged at the right end of the, and a match line 14 further extends from the output of the inverter 31 and is connected to the priority encoder 15 shown in FIG.

The input of the inverter 31 and the power source V
Two P-channel transistors 32 between DD and
33 are arranged, and these two transistors 3
One of the transistors 32 and 33 has a gate connected to the control line 30, and the other transistor 33 has a gate connected to the output of the inverter 31. In the associative memory including the memory word having such a structure and its peripheral circuit, the matching search is performed as follows.

It is assumed that information of logic "1" is stored in the memory cell 11-1. That is, in this case, the output side of the first inverter 20-1 is in the state of logic "1" and the output side of the second inverter 21-1 is in the state of logic "0". It is assumed that a search for logic "1" is performed on this memory cell 11-1. That is, the bit line 23-1 has a logic "1" and the bit bar line 26-1 has a logic "0". The word line 24 is held in the state of logic "0". In this case, the voltage of logic "1" is applied to the gate of the transistor 27-1, and the signal of logic "1" of the bit line 23-1 is applied to the gate of the transistor 36-1. Turns on. That is, when the bit information stored in the memory cell 11-1 and the bit information in the search data input via the bit line 23-1 and the bit bar line 26-1 match, the corresponding transistor 36- 1 is in the "on" state.

The memory cell 11-2 has a logic "0".
Information is stored. In this case, the output side of the first inverter 20-2 is in the logic "0" state and the output side of the second inverter 21-2 is in the logic "1" state. It is assumed that the logic "1" is searched for the memory cell 11-2. That is, the bit line 23-2 has a logic "1" and the bit bar line 26-2 has a logic "0". In this case, the signal of the bit bar line 26-2 in the logic “0” state is applied to the gate of the transistor 36-2 via the transistor 28-2, and thus the transistor 36-2 is in the “off” state. Will remain. That is, in the case of a mismatch, the charges precharged on the match line 14 are not discharged.

Further, regarding the masked bits,
As shown in the memory cell 11-n, the bit line 23-n,
Both of the bit bar lines 26-n are set to logic "1".
In this case, either the transistor 27-n or the transistor 28-n is set to "1" depending on whether the information of logic "1" is stored in the memory cell 11-n or the information of logic "0" is stored. It will be in the'on 'state, which will cause transistor 36-n to be in the'on' state in either case. That is, regarding the memory cell, it is considered that the stored information and the search information match each other.

In the search, the control line 30 first becomes logic "0", the transistor 32 becomes "on", the match line 14 on the input side of the inverter 31 is precharged, and then the control line 30 becomes logic "1". Then, the transistor 32 is turned off, precharge is stopped, and the transistor 36-0 is turned on.

At this time, the information stored in the memory cell and the input search information match in all the memory cells forming this memory word 11 (the masked bits as described above are regarded as a match). In this case, all of the transistors 36-1, 36-2, ..., 36-n are in the “on” state, the charge precharged on the match line 14 is discharged, and the inverter 31 outputs a signal of logic “1”. It

The memory structure of the associative memory shown in FIG. 6 is merely an example, and various structures have been proposed (for example, see Japanese Patent Application No. 5-216424). As described above, the associative memory requires high-speed data processing because it can input search data and instantly know whether or not the data that matches the search data is stored with only one search operation. Widely applied to various fields.

Various techniques have been proposed for this associative memory. Here, a technique referred to when the present invention is described later will be described. One of them is the technique proposed in JP-A-57-74887. When data matching a certain search data is stored in a plurality of memory words, the priority encoder 15 (see FIG. 5) always outputs the address of the specific memory word corresponding to the matching line having the highest priority, and matches. Inequalities will occur between the memory words in which the data is stored. To solve this, a flag indicating whether or not an address has been read is stored in association with each memory word, and for the memory word from which the address has been read, a match is detected again in a later search. Even if it is done, the priority is lowered.

The other one is Japanese Patent Publication No. 61-31558.
This is the technology proposed in the publication. The large number of memory words that make up the associative memory do not always have the data to be searched stored in all memory words, and some of these memory words are empty spaces that do not store valid data. In some cases, new valid data may be written to the memory word in the empty state or in the empty memory word. In this case, it is complicated to manage which memory word is empty or not externally, so whether valid data is stored in the memory word corresponding to each memory word. , Or store a flag indicating whether or not the memory word is empty in association with each memory word, and when writing new valid data, find the empty memory word in the associative memory itself. , Writing valid data to that memory word.

The relationship between these two techniques and the present invention will be described later. Next, as an example of application of the associative memory, an example of application to a LAN (Local Area Network) will be described. FIG. 7 is a diagram showing an example of a LAN.
As shown in FIG. 7A, two communication lines LAN1 and L
It is assumed that a plurality of terminals A to G and T to Z are connected to the AN2, respectively, and thereby two communication networks are configured. It is assumed that the traffic volume of each communication line LAN1 and LAN2 (the amount of data flowing through the communication line: the congestion degree of the communication line) is '10'.

When it is necessary to connect these two communication lines to each other, if they are simply connected as shown in FIG. 7 (B), the traffic amount of the communication circuits LAN1 and LAN2 becomes 20, which is extremely congested. As a result, the terminals are not easily connected to each other, resulting in an increase in waiting time and idle time. Therefore, as shown in FIG.
A bridge for filtering whether or not to transmit the data transmitted from one of the communication lines LAN1 and LAN2 to the other is connected between the two communication lines LAN1 and LAN2. When this bridge is connected, assuming that the traffic amount of data passing through the bridge, that is, the traffic amount of data transmission / reception across two communication networks is 1, each communication line LAN1, LAN2
Each communication line LA combined with the internal traffic volume of 10
The traffic volumes of N1 and LAN2 are 11, respectively, and the traffic volume is greatly reduced as compared with the case of FIG. 7B in which two communication lines LAN1 and LAN2 are simply connected. Here, the connection of the two communication lines LAN1 and LAN2 has been described, but if a large number of communication lines are connected to one bridge, this difference becomes more remarkable.

FIG. 8 is an explanatory view of the function of the bridge. The bridge has an internal memory and initially starts from a blank state. For example, when data is transmitted from the terminal A of the communication line LAN1, the data is transmitted from the LAN1 side, and the terminal A receives the data. Is connected to the communication line LAN1. This learning is conceptually
This is performed by having a table 1 and a table 2 for each of the communication lines LAN1 and LAN2 in the memory inside the bridge, and writing the terminal A in the table 1 corresponding to the communication line LAN1. Whether or not the destination of the data transmitted from the terminal A is in the communication network on the same LAN1 side as the terminal A is not known at the time of learning only for the terminal A, and therefore unconditionally passes the bridge at this time. Let

By repeating such learning, tables 1 and 2 as shown in FIG. 8 are created in the bridge, and after these are created, for example, as shown in FIG. LAN1 side), destination is terminal X
The data on the (LAN2 side) is recognized by the bridge that the terminals B and X are passing over the bridge and is passed through the bridge, and the destination and destination are both the terminals A and E on the LAN1 side. In this case, the terminals A and E recognize that they are on the same side of the communication network as seen from the bridge and block the passage of bridge data. As a result, as described above,
The amount of traffic can be reduced.

If an associative memory is used as the memory provided in this bridge, the processing speed can be increased. For example, information on each of the terminals A to G and T to Z and information on whether each of those terminals belongs to the table 1 (is connected to the LAN 1 side) or the table 2 (is belonging to the LAN 2 side). Is stored in the associative memory, and in determining whether or not to pass the data, for example, when the receiving destination is the terminal X, the X is searched as search data,
It can be recognized that X is a terminal belonging to Table 2 (LAN2), and based on this, whether or not to pass data can be determined.

On the other hand, when the bridge is provided with a normal RAM memory or the like, it is necessary to read the stored data one by one and search for the data of the terminal X by successive comparison. Therefore, it takes a lot of time to decide whether to pass or block the bridge.

[0024]

As described above, the associative memory is preferably used in, for example, a LAN network, but further improvement is desired as shown below. That is, as described above, the bridge first learns from a blank state, but in this learning process, it is necessary to pass the data unconditionally through the bridge without knowing which communication network the data transmission destination belongs to. As a result, the traffic volume is increased as shown in FIG. 7 (B). There is almost no problem if the traffic volume is increased only once at the first time, but in reality, it is usually necessary to perform it fairly frequently, for example, every several tens of seconds to 1 minute. This is because it is necessary to eliminate the terminals that are not involved in data transmission / reception, and to repeatedly initialize the memory in the bridge to perform learning. Since it is necessary to repeatedly initialize the memory in this way, this is one of the obstacles to further reducing the traffic amount.

To solve this problem, it is necessary to record whether or not each terminal participated in data transmission / reception between the last initialization and this time, instead of completely initializing the memory. It may be possible to initialize the data of the terminals that have not participated and to leave the data of the terminals that have participated as they are, with reference to the record. However, if the conventional associative memory is used to realize this, the terminal data that need to be initialized are sequentially deleted one by one while referring to the flag indicating whether or not the device has participated in data transmission / reception. Need to go,
As with the successive comparison described above, it takes a lot of time for initialization.

Therefore, the inventor of the present application has filed Japanese Patent Application No. 5-248.
No. 119 specification, an associative memory capable of collectively erasing only unnecessary data, or in Japanese Patent Application No. 6-240045 specification, according to the hit history for each entry,
We proposed an associative memory that can erase unnecessary data. However, in such an associative memory, there is a problem that the entry data which is desired to be retained semipermanently is erased regardless of the hit history.

Therefore, the inventor of the present application filed Japanese Patent Application No. 6-25.
In the specification of No. 5092, by holding the validation control flag of the second flag for each memory word,
We proposed an associative memory that can erase only unnecessary data for each entry without erasing the entry data that you want to keep regardless of the hit history. However, in such an associative memory, there has been a problem that means for defining whether or not each entry is held in the memory table must be separately provided according to the entry data. Therefore, an object of the present invention is to solve the above problems and propose a new associative memory capable of setting whether or not to hold semi-permanently in the memory table for each entry according to the result of searching the entry data. Especially.

[0028]

An associative memory of the present invention which achieves the above object is provided with a plurality of memory words for storing respective data and a plurality of memory words respectively corresponding to the plurality of memory words. In an associative memory having a match detection circuit for detecting a match / mismatch between the data stored in and the input search data, (1)
Provided corresponding to each of the plurality of memory words,
The corresponding memory word is the memory word in the first storage state in which the valid data to be searched is stored, or the valid data is not stored in the second storage word and therefore the second writing is permitted. A first flag register for storing a first flag indicating whether the memory word is in the storage state of (2), which is provided corresponding to each of the plurality of memory words, and the corresponding memory word is
It is a memory word in the first history state in which a match was detected at least once in the past multiple searches, or in a second history state in which all matches were unmatched in the past multiple searches. Second indicating if there is
A second flag register storing the flag of (3), the first flag of the memory words in the first storage state
The second flag in which the second flag indicating one of the second history state and the second history state is stored.
A memory state corresponding to the flag register of No. 1 and in which the result of the search for each specific bit of the plurality of memory words is either coincident or non-coincident, the memory state is changed to the second memory state. It is characterized in that a change circuit is provided.

Here, it is preferable that the associative memory according to the present invention further includes a storage state reset circuit for collectively changing the memory words in the first storage state to the second storage state. In the associative memory according to the present invention, the second history state is stored in the second flag register of the memory word in which the search result of each specific bit of the plurality of memory words is either coincident or non-coincident. It is preferable to include a history state reset circuit for storing the second flag shown.

[0030]

In the associative memory of the present invention, a first flag indicating whether valid data is stored and a second flag indicating whether a match is detected are associated with each memory word. The memory word in which valid data is stored is erased for each word in accordance with the second flag state and the result of the search of the specific bit of the stored data. At the time of initialization, it is not the data that should be retained regardless of the presence or absence of the past match detection, and the match detection has never been performed in the past, that is, only the data of the terminal that has not participated in the data transmission / reception is fixed. It can be erased word by word at time intervals, and the data required at this time, that is, data that you want to retain semipermanently, regardless of past hit history, can be erased by mistake. Mau nor. Note that the memory word may be erased by erasing the data itself stored in the memory word, but is not limited to this, and it is only necessary that the data is substantially equivalent to the case where it is erased. For example, the first flag The memory word may not participate in the search by rewriting the flag content of the register.

As mentioned above, JP-A-57-74887
The publication discloses a flag that is similar to the second flag according to the present invention, and the publication of Japanese Patent Publication No. 61-31588 discloses the first flag according to the present invention. However, as described above, the techniques proposed in these publications show means for solving completely different problems, and these publications associate these first flag and second flag with each other. Things do not exist at all. Further, these publications do not include the storage state changing circuit according to the present invention.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. FIG. 1 is a block diagram of an associative memory 1 according to an embodiment of the present invention.
It is a circuit diagram which shows the characteristic part corresponding to one memory word. The components corresponding to the components in the drawings referred to in the above-mentioned conventional example are designated by the same numbers as those in the drawings.

In FIG. 1, the structure of the memory word 11 and the match line 14 is schematically shown. The structure of the entry data stored in the associative memory device of the present invention and the memory word storing this entry data will be described later.
A first flag register 51 is provided corresponding to each memory word 11, and the first flag register 5 is provided.
In the case where 1 stores valid data to be searched for in the corresponding memory word 11, '0' is stored, and invalid data which is excluded from the search and therefore allows writing ( Here, the corresponding memory word 11 is referred to as "in a free state", and a free flag of "1" (an example of the first flag according to the present invention) is stored. Here, it is assumed that this empty flag is "0", that is, valid data is stored in the illustrated memory word 11. The Q output of the first flag register 51 is connected to the inverting input side of the AND gate 53 whose one input side is inverted.

, 23-n and bit bar lines 26-1, ..., 26-n are searched and the search data and the illustrated memory word 11 (memory) are searched. If the data stored in the cells 11-1, ..., 11-n) match, the match line 14 becomes “1”. The match line 14 is connected to the non-inverting input of the AND gate 53, and the first flag register 5
Since the output of 1 is "0", the output of the AND gate 53 is "1". The output of the AND gate 53, that is, the search result (hit flag or hit information) is the hit flag register 53a provided corresponding to each memory word.
Is input to the hit flag clock line 50, and its value is held by applying a clock pulse to the hit flag clock line 50.
Here, the signal line extending from the output of the hit flag register 53a is also referred to as the match line 140. This match line 1
The reference numeral 40 extends to the priority encoder 15 shown in FIG. 5 instead of the matching line 14 in the conventional case. Also,
The output of the AND gate 53 is also input to the second flag register 55 via the OR gate 54. The second flag register 55 is provided corresponding to each memory word, and when resetting collectively corresponding to all the memory words 11 regardless of the immediately preceding search result, that is, the state of the match line 140. Is a history flag reset control line 74
Of the history flag reset signal lines 56a and 56b, the two-input AND gate 72 having these signal lines 56a and 56b as inputs, and the inverted output OR gate 7 having the output of the AND gate 72 as one input.
0, an inverted output of the OR gate 70 and a 2-inversion input AND gate 77 having the history flag reset control line 74 as an inverting input, and an inverting output OR gate 75 having the output of the AND gate 77 as one input The reset pulse input to the reset inverting input R of the flag register 55 causes the corresponding memory word 11 to store “0” indicating that there is no match in the past.

Further, irrespective of the immediately preceding search result, when the second flag register 55 is reset when data is entered in each memory word, the history flag reset control line 74 remains inactive. , The word reset signal line 56c and the word line 24 are activated so that the signal line 56c and the word line 24 are input.
An inverting output OR gate 70 having the output of 1 as the other input,
The reset pulse can be reset by the reset pulse input to the reset inverting input R of the second flag register 55 via the AND gate 77 and the OR gate 75 described above. This word line 24 is the main decoder line 5
2a and the sub-decoder line 52b are defined as the output of the AND gate 67, and only the specific word selected by these decoder lines 52a and 52b is provided to be active.

When the second flag register 55 is reset in accordance with the immediately preceding search result, the history flag reset control line 74 is kept in the active state, and, for example, if the match search result is the match "1", If the memory word is reset all at once, the history flag reset signal lines 56a and 56b and the AND gate 7 described above are used.
2, an OR gate 70, a 3-input AND gate 7 having an inverted input of the inverted output of the OR gate 70 and a history flag reset control line 74 and a match line 140 as non-inverted inputs
6. The second flag register 5 via the inverting output OR gate 75 which receives the output of the AND gate 76 as the other input
The reset pulse input to the reset inverting input R of 5 enables resetting. Further, the history flag reset control line 74 is activated, and the reset inversion input of the second flag register 55 is performed via the word reset signal line 56c, the word line 24, the AND gate 71, the OR gate 70, the AND gate 76, and the OR gate 75. By the reset pulse input to R, the second flag register 55 corresponding to the memory word for which the immediately preceding search result is coincidence "1" can be reset when data is entered in each memory word. In the present invention, the circuit for controlling the reset of the second flag register 55 is not limited to the application of the two kinds of composite gates in the illustrated example, and the configuration thereof is not limited.
For example, contrary to the above embodiment, the second flag register 55 may be reset when the immediately preceding search result does not match, or the second flag register 55 may be selectively selected according to the immediately previous search result. Of course, it may be configured so that 55 can be reset.

Here, as a result of the coincidence with the search data in this memory word as described above, the AND gate 5
The output of 3 becomes "1" indicating a match, and the match signal is applied to the second flag register 55 via the OR gate 54. Here, by applying a clock pulse to the history flag clock line 57, “1” indicating that there is a match with the search data is stored in the second flag register 55. Once "1" is stored in the second flag register 55, the second flag register 55
Is output to the second flag register 55 again via the OR gate 54, so that it is always set to "1" every time a clock pulse is applied to the history flag clock line 57 until the next reset. 1'will continue to be overwritten. The Q output of the second flag register 55 is input to itself via the OR gate 54 and the word line 2
It is also connected to the flag data lead wire 55a via a 3-state buffer 73 whose control input is 4. Thus, by activating the word line 24, the second
It is designed to be able to read out the Q node output of the flag register 55 of.

Further, the Q output of the second flag register 55 is a 2-input AND gate 80 having the control line 78 as an inverting input and the Q output as a non-inverting input by deactivating the control line 78. A select circuit 59 is provided via an OR gate 79 that receives the output of the AND gate 80 as one input and a signal line 58 that transmits the output of the OR gate 79.
Entered in. In addition, by activating the control line 78, the Q output is set as the inverting input and the control line 78 and the matching line 140 are set as the non-inverting input when the search result is "1". The 3-input AND gate 81, the inverted output of the AND gate 81, and the OR gate 79 which receives the other input, and the signal line 58 can be input to the select circuit 59. Of course, when the search result at this time is a mismatch “0”, the select circuit 59 outputs “1” regardless of the Q output of the second flag register 55.
Is entered. In the present invention, the circuit that controls the input of the Q output of the second flag register 55 to the select circuit 59 is not limited to the composite gate in the illustrated example, and the configuration thereof is not limited. The inverted output Q bar of the Q output may be input to the select circuit 59 when there is a match, and when there is a mismatch, Q is output.
It may be configured such that "0" is output regardless of the output, and when the immediately preceding search result does not match, the Q output or its inverted output Q bar is directly input to the select circuit 59, and when it matches, Q is output. Of course, it may be configured so that "1" or "0" is input regardless of the output.
With this configuration, the second flag register 5
It is possible to control (switch) the input of either the Q output of No. 5 or the output of a predetermined value not depending on the Q output to the select circuit 59 according to the immediately preceding search result, that is, hit information. A signal line 60 connected to the word line 24 and four selection signal lines 61, 62, 63a, 63b are also connected to the select circuit 59.

FIG. 2 is a circuit diagram showing the configuration of select circuit 59. The select circuit 59 includes 5-input AND gates 590a and 590b, a 3-input AND gate 591,
3-input AND gate 59 in which all signals on the input side are inverted
2, 3 inputs AND gate 593 in which only one input side signal is inverted, and AND gates 590a, 5
Each of the outputs 90b, 591, 592, 593, and a 6-input OR gate 594 connected to the selection signal line 61.

The selection signal line 61 collectively stores an empty flag "1" indicating that the memory word 11 is in an empty state in all of the first flag registers 51 corresponding to each memory word 11. It is a signal line for making it. When a signal of logic “1” is applied to the signal line 61, the signal is input to the AND gate 64 shown in FIG. 1 via the OR gate 594. An empty flag clock signal line 65 is also connected to the AND gate 64, and the select circuit 5
Since the signal of logic '1' is input to the AND gate 64 from 9, the clock pulse passes through the AND gate 64 when the clock pulse is applied to the empty flag clock signal line 65, and the first flag register It is input to the clock input terminal 51. At this time, if a signal of logic "1" is placed on the empty flag data line 66, the empty flag "1" is set in the first flag register 51, whereby all the memory words 11 are collectively in the empty state. Becomes As described above, the output of the first flag register 51 is connected to the inverting input terminal of the AND gate 53, and even if a match is detected in the empty memory word 11, the match line 14 becomes "1". Mo and gate 53
Then, the AND gate 53 remains at "0".

Further, three selection signal lines 61, 62, 63
When a is all "0" and the selection signal line 63b is "1", the second flag register 55 stores "0" indicating that there is no match in the past, and the control is performed. When the line 78 is in the inactive state, or when the control line 78 is active and the previous search result is a match, that is, the match line 140 is “1”, the signal line 58 is “0”. In this state, the output of the AND gate 592 becomes "1", and "1" is output via the OR gate 594. In that state, when a signal of “1” is applied to the empty flag data line 66 and a clock pulse is applied to the empty flag clock line 65, the empty flag is stored in the first flag register 51. That is, in this case, the memory word 11 corresponding to the second flag register 55 in which “0” indicating that there is no match in the past is stored, or the immediately preceding search result of such memory words 11 is matched. Only the memory word 11 that was ('1') is collectively changed to the empty state.

Further, the selection signal lines 61 and 63a are set to "0",
When the selection signal lines 62 and 63b are kept at "1", the second flag register 55 stores "1" indicating that there is a match in the past, and the control line 78 is If the control line is active “1” and the previous search result is mismatch “0” regardless of the value of the second flag register 55, the signal line is inactive “0”. 58 is in the state of "1", the output of the AND gate 593 becomes "1", and "1" is output via the OR gate 594. That is,
In this case, the memory word 11 corresponding to the second flag register 55 in which “1” indicating that there is a match in the past is stored, or the memory word 11 in which the immediately preceding search result is a mismatch “0” is All of them are changed to free status. In the above cases, only the value of the second flag register 55, or the second flag register 55 and the match line 1
According to the value of 40 (combination with the control line 78),
This is a method of determining whether data is valid or invalid.

Similarly, a method of deciding whether the data of each word is valid or invalid will be described below. First, the structure of the entry data stored in the associative memory of the present invention, the structure of the memory word for storing the entry data, and the operation of the associative memory of the present invention will be described. First, FIG. 3 (a)
As shown in, the entry data ED used in the present invention
Consists of the data DD to be searched for, the attribute bit PB indicating the attribute of this data, and other bits,
It is assumed that there is at least a specific bit called a permanent bit in the attribute bit that indicates whether the attribute bit is retained permanently or semi-permanently regardless of the hit history.
In the illustrated example, it is assumed that the permanent bit PB is in the first bit of the entry data, the data DD to be searched is subsequently in a predetermined bit, and the remaining bits are other bits.

The entry data EDa having such a structure,
, EDn are a plurality of memory words of the associative memory 10 of the present invention, for example, 11 as shown in FIG.
It is assumed that the data is written in a, 11b, ..., 11n. Here, the entry data EDa, EDb, ..., In the first memory cell of each memory word 11a, 11b ,.
The value of the first bit of EDn is written, and in the illustrated example, the first memory cell of the memory word 11a is permanently or semi-permanently irrespective of the hit history indicating whether or not the entry data EDa has been previously searched for a match. The remaining memory word 11 is written with "1" indicating that it is valid data to be retained (that is, permanent data).
It is assumed that "0" indicating that the data can be invalid data is written in each of the first memory cells b, ..., 11n according to the hit history. Each of the memory words 11a, 11b, ..., 11n has a hit flag register 53a that stores a hit flag (HF) indicating the result of the current or previous match search, and whether or not there is a match at least once in the past multiple searches. A second flag storing a second flag (history flag (AB)) indicating whether
A flag register 55 and a first flag register 51 for storing a first flag (empty flag (EB)) indicating whether the data is valid data or invalid data are provided. Here, all memory words 11a, 11b, ..., 11n
Regarding all the hit flag registers 53a, there is no match "0", all the second flag registers 55 have no match "0" in the past, and all the first flag registers have "0" indicating that they are valid data. It has been written.

In the above configuration, the attribute bit P
Search target data DD by masking B and other bits
If only the entry data EDb stored in the memory word 11b match and the others do not match as a result of repeating the data search for a plurality of types of search data RD a plurality of times, the memory word 11b is hit. The flag register 53a and the second flag register 55 indicate "1" indicating that there is a match and that there is a match in the past.
Is written.

Here, as in the conventional case, when the validity or ineffectiveness of the data for each word is determined only by the information of the history flag of the second flag register 55, that is, in the present invention, the control line 78 is made inactive. By doing the second
When the Q output of the flag register 55 is directly input to the select circuit 59 via the signal line 58, the contents of the first flag register 51 can be rewritten by the following two methods.

First, the selection signal line 63a is kept at "1" and the selection signal lines 61, 62, 63b are kept at "0", and it is determined that the second flag register 55 has no match in the past. The value "0" is stored, and AND gate 8
Since the composite gate composed of 0 and 81 and the OR gate 79 outputs the Q output of the second flag register 55 as it is, the signal line 58 is in the state of “0”, and the specific memory word 11 is selected and the word line thereof is selected. 24, therefore, when the signal line 60 is in the state of "1", the output of the AND gate 590a becomes "1", and "1" is output via the OR gate 594. In that state, when a clock pulse is applied to the empty flag clock line 65 and at the same time a signal of logic "1" is placed on the empty flag data line 66, the empty flag "1" is set in the first flag register 51. It That is, according to this control method, only a specific memory word that has not been matched in the past, for example, as shown in FIG.
In the example shown in (b), memory words 11a, 11c, ...
It is possible to make only 11d free data.

Next, select signal lines 63a and 62 are set to "1",
If the selection signal lines 61 and 63b are kept at "0" and the second flag register 55 stores "1" indicating that there is a match in the past, the AND gate 8
Since the composite gate composed of 0 and 81 and the OR gate 79 outputs the Q output of the second flag register 55 as it is, the signal line 58 is in the state of “1”, and the specific memory word 11 is selected and its word line 24 is selected. When the (signal line 60) is in the state of "1", the AND gate 590
The output of b becomes "1", and "1" is output via the OR gate 594. In this state, if a clock pulse is applied to the empty flag clock line 65 and at the same time a signal of logic "1" is placed on the empty flag data line 66, the empty flag "1" is set in the first flag register 51. It That is, only a specific memory word that has matched in the past, for example, memory word 1 in the example shown in FIG.
Only 1b can be used as empty data.

Similarly, the selection signal lines 63a, 63
By setting b to "1" and selecting the specific memory word 11 and setting the word line 24 (signal line 60) to "1",
The output of the AND gate 591 becomes "1", and as a result, "1" is output via the OR gate 594. Therefore, the empty flag "1" is set in the first flag register 51 in the same manner as described above. , Any particular memory word can be freed.

On the other hand, in the present invention, when the validity / invalidity of the data for each word is determined, not only the information of the history flag of the second flag register 55 of each memory word but also the memory flag is stored in each memory word. It is possible to take into account the attribute bit information of the entry data, that is, the hit information indicating the result of searching this attribute bit. First,
As shown in FIG. 3C, the search target data DD and other bits are masked and only the attribute bit PB is searched for "0" for all memory words 11a, 11b, ..., 11n. Here, in the illustrated example,
Entry data E stored in memory word 11a
Since Da is permanent data and the attribute bit PB is "1", the search results do not match and "0" is written in the hit flag register 53a, but the remaining memory words 11b, ... The attribute bit PB of the data EDb, ..., EDn is “0” and the search results match, so that “1” is written in the hit flag register 53a.
The search result at this time, that is, the hit information written in the hit flag register 53a is not reflected in the second flag of the second flag register 55.

Here, in the present invention, by activating the control line 78 as shown in FIG. 1, the output of the AND gate 80 becomes "0", and the hit flag register 53a showing the immediately preceding search result. , Which is written with "1" indicating that the memory word 11c, ...,
11n (see FIG. 3 (c)), the AND gate 81 operates only when the output of the match line 140 is "1", the Q output of the second flag register 55 is "0", and the inverted input Q bar thereof is "1".
Outputs an inverted output "0", the output of the OR gate 79 becomes "0", and the state of the signal line 58 becomes "0". On the other hand, the memory word 11 in which the output of the match line 140 is “1” and the Q output of the second flag register 55 is “1”
b (see FIG. 3C), the inverted output of the AND gate 81 is "1" when the inverted output Q bar is "0".
The OR gate 79 outputs "1" and the signal line 58
The state of becomes "1". On the other hand, at this time, since the output of the match line 140 is "0" in the memory word 11a (see FIG. 3C) in which "0" indicating that there is a mismatch in the hit flag register 53a is written, The AND gate 8 regardless of the value of the Q output of the second flag register 55.
Since the inverted output of 1 becomes "1", the OR gate 79 outputs "1" and the state of the signal line 58 becomes "1".

Here, as described above, the signal line 60 and the selection signal line 63a are set to "1", the selection signal lines 61, 62, and
If 63b is kept at "0", the signal line 58
All memory words 11c, ..., 11 in which is "0"
In n, the output of the AND gate 590a becomes "1",
Since "1" is output from the OR gate 594, the empty flag "1" can be set in the first flag register 51 via the AND gate 64. That is, the permanent data is not stored and the memory words 11c, ..., 11n that have not been matched in the past can be used as empty data. On the other hand, not only the memory word 11b in which the entry data EDb having the match “1” in the past is stored but also the search result does not match “0”, that is, the permanent data EDa is stored even if there is no match in the past. In the written memory word 11a, the state of the signal line 58 is "1", so that even if the signal line 60 and the selection signal lines 61, 62, 63a,
Even if 63b is kept in the same state, the outputs of all five AND gates 590a, 590b, 591, 592, and 593 become "0", and "0" is output from the OR gate 594, so the first flag register 51 It is not possible to set the empty flag '1'. That is, the memory word (11a) in which the permanent data is stored and the specific memory data (11b) that have been matched in the past are not set as empty data.

In the above example, the control line 78 is made active, and only the memory word whose search result is coincident and which is not coincident in the past is made into the rewritable invalid data. However, the present invention is not limited to this, a memory in which an attribute bit such as a permanent bit of entry data stored in a memory word is searched, the attribute bit has a specific value, and the value of the history flag of the second flag register 55 is a specific value. Any circuit configuration including the configuration of the composite gate may be used as long as it is possible to make only the word invalid data or invalid data.

Further, in the present invention, the attribute bit of the entry data written in the memory word 11 is used as a classification attribute in the multi protocol, and the entry data is classified into a group so that the attribute bit is searched. As a result, that is, the hit information can be used to selectively reset the second flag register 55 as a group. That is, as described above, the history flag reset control line 74 is activated,
By activating the history flag reset signal lines 56a and 56b, it is possible to collectively reset the second flag registers 55 of the group of the memory words 11 whose search results are coincident '1'.

An example of management of the writing time for each data, that is, the registration time (entry time) in such a configuration will be described with reference to FIG. First, in order to perform aging (registration time management) of entry data, as shown in FIG. 4, an aging table 43 that registers the aging data 40 in association with the entry data registration time series, as shown in FIG. make. Here, the entry address 40a indicates the address when the entry data is registered in the associative memory, and the entry time 40b
Is data corresponding to that time, and at least these two types of data are stored as the aging data 40 at the position indicated by the entry pointer 41. Once the aging data 40 is stored, the entry pointer 41
It is configured to sequentially indicate the next storage position.

Further, when this entry data is registered in the memory word 11 of the associative memory, the second flag register 55 is reset by the above-mentioned method to "0" indicating that there is no match in the past. The address of this memory word 11 is set in advance and is registered in the aging table 43 of FIG. 4 as the entry address EAi and its registration time as ETi. The data once registered in the associative memory is input to the output of the OR gate 54 to which the output of the AND gate 53 is input by the pulse input to the history flag clock line 57 every time the data is searched. That is, information indicating whether or not there is a match is accumulated in word units.

The aging pointer 42 shown in FIG. 4 stores the data in order from the oldest entry (the one higher in the figure) in a cycle ts sufficiently shorter than the minimum retention time T of the entry data. The entry indicates a position where aging data is checked completely asynchronously. For example, the aging pointer 42 is now shown in FIG.
, The entry time 40 of this aging data 40 is shown.
When b is compared with the current time and the holding time is equal to or longer than the minimum holding time T, the memory word 11 on the associative memory having this entry address 40a as address data is accessed. At this time, the word line 24 is set to "1" and the value of the flag data read line 55a of the Q node output of the second flag register 55 is read. Here, if this value is "1",
That is, it is assumed that there is a match in the past. Assuming that the entry data is controlled to be retained for the next minimum retention time T when there is a match within the minimum retention time T, the control line 74 remains inactive at this time. A reset pulse is input to the line 56c to reset the second flag register 55. Further, the highest aging data 40 in the aging table 43 of FIG. 4 is invalidated, and the EAo of this entry address 40a is rewritten (re-registered) in the EAi of the entry possible area indicated by the entry pointer 41, and at the same time, ETi The data corresponding to the writing time is written in. This means that the entry data in the associative memory indicated by EAo of the entry address 40a is newly registered as a target to be held for the next minimum holding time T. At this time, the aging pointer 42 and the entry pointer 41 of the aging table 43 are lowered one by one.

Of course, in the above example, if the minimum holding time T is less than the current time, all the data is held until the next check of the aging pointer 42 after ts time.

Further, when compared with the current time, when the minimum holding time is T or more, the value of the flag data lead wire 55a is "0", and there is no match in the past, the control line 74 is used.
While the signal is inactive, a reset pulse is input to the control line 56c to reset the second flag register 55, and at the same time, as described above, the selection signal lines 63a and 63b are set to "1" and the selection signal lines 61 and 62 are set to "1". With the state kept at 0 ', by applying a clock pulse to the empty flag clock line 65 and at the same time applying a logic' 1 'to the empty flag data line 66, the first word of the selected memory word
The empty flag “1” is set in the flag register 51 of FIG. That is, with this control method, it is possible to make only the specific memory word that has not been matched in the past free data.

At this time, the aging data 40 designated by the aging pointer 42 of the aging table 43
Is invalidated, the aging pointer 42 is lowered by one,
In the next cycle after ts time, the next aging data 4
Check for 0. The position of the entry pointer 41 does not move because the highest aging data 40 is not rewritten. In this way, the minimum retention time T can be finely controlled for each entry data stored in the associative memory.

The memory word 11 corresponding to the first flag register 51 in which the empty flag "1" is stored.
Writing data to the bit lines 23-1, ..., 23
-N and bit bar lines 26-1, ..., 26-n are loaded with data to be stored in the memory word 11,
This is performed by activating the word line 24 of the memory word 11 selected by the main decoder line 52a and the sub decoder line 52b via the AND gate 67.

[0062]

As described above, the associative memory of the present invention has the first flag indicating whether valid data is stored and the second flag indicating whether a match has been detected in the past. Correspond to each memory word, and the second flag state is held or erased for each word depending on the result of the search of the specific bit of the memory word. Alternatively, only those that do not match and need not be held can be erased and reset for each word. Further, according to the present invention, the state of the second flag can be selectively reset as a group using the result of the search for the specific bit of the memory word.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a characteristic portion corresponding to one memory word in an associative memory according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a select circuit used in the associative memory shown in FIG.

3A is data stored in the associative memory shown in FIG. 1, and FIGS. 3B and 3C are explanatory diagrams of the operation of the associative memory shown in FIG.

FIG. 4 is an explanatory diagram showing an example of an aging table.

FIG. 5 is a circuit block diagram showing an example of a conventional associative memory.

FIG. 6 is a detailed circuit diagram showing one memory word in an associative memory.

7 (A), (B) and (C) are all LA
It is a figure showing an example of N.

FIG. 8 is a functional explanatory diagram of a bridge.

[Explanation of symbols]

10 associative memories 11, 11a, 11b, 11c, 11d, 11e, ...
11n memory word 11-1, 11-2, ..., 11-n memory cell 12 search registers 14, 14a, 14b, 14c, 14d, 14e ,.
14n Matching line 15 Priority encoder 16 Address decoder 17a, 17b, 17c, 17d, 17e, ..., 17
n, 24 word line 18 output registers 20-1, 20-2, ..., 20-n first inverters 21-1, 22-2, ..., 21-n second inverters 22-1, 22-2 ..., 22-n, 25-1, 25-
2, ..., 25-n, 27-1, 27-2, ..., 27-
n, 28-1, 28-2, ..., 28-n, 36-0, 3
6-1, 36-2, ..., 36-n N-channel transistors 23-1, 23-2, ..., 23-n bit line 26-1, 26-2, ..., 26-n bit bar line 30 control line 31 Sense Inverters 32, 33 P Channel Transistor 40 Entry Data 40a Entry Address 40b Entry Time 41 Entry Pointer 42 Aging Pointer 43 Aging Table 50 Hit Flag Clock Line 51 First Flag Register 52a Main Decoder Line 52b Sub Decoder Lines 53, 64 , 67, 71, 72, 76, 77, 80, 8
1 AND gate 53a Hit flag register 54, 70, 75, 79 OR gate 55 Second flag register 55a Flag data lead line 56a, 56b History flag reset signal line 56c Word reset signal line 57 History flag clock line 58, 60 Signal line 59 Select circuit 61, 62, 63a, 63b Select signal line 65 Free flag clock signal line 66 Free flag data line 73 Tristate buffer 74 History flag reset control line 78 Control lines 590a, 590b 5 inputs AND gates 591, 592, 593 3 inputs AND gate 594 6-input AND gate

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11C 15/00-15/06

Claims (3)

(57) [Claims] 1. A plurality of memory words for respectively storing respective data and a match / mismatch between the data stored in the corresponding memory words and the input search data. In an associative memory having a match detection circuit for detecting, provided corresponding to each of the plurality of memory words,
The corresponding memory word is the memory word in the first storage state in which the valid data to be searched is stored, or the valid data is not stored in the second storage word and therefore the second writing is permitted. A first flag register that stores a first flag indicating whether the memory word is in the storage state of, and the first flag register is provided corresponding to each of the plurality of memory words,
The corresponding memory word is a memory word in the first history state in which a match has been detected at least once in the past multiple searches, or the second history in which all matches have not been found in the past multiple searches. A second flag register that stores a second flag indicating whether the memory word is in a state; and the first history state and the second history among the memory words in the first storage state. A memory word corresponding to the second flag register in which the second flag indicating one of the states is stored,
And a memory state changing circuit for changing a memory word whose search result of each specific bit of the plurality of memory words is coincident or non-coincident to the second memory state. memory. 2. The associative memory according to claim 1, further comprising a memory state reset circuit for collectively changing the memory words in the first memory state to the second memory state. 3. The second flag register of the memory word in which the search result of each specific bit of the plurality of memory words is either a match or a mismatch, the second history register indicating the second history state. The associative memory according to claim 1, further comprising a history state reset circuit that stores a flag.