JP2868976B2 - Semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rewritable semiconductor memory such as an SRAM.

[0002]

2. Description of the Related Art Rewritable semiconductor memories such as SRAMs have been used in a wide range of fields. here,
A usage example in the field of image transmission will be described. It is assumed that a semiconductor memory for storing image data for one frame is prepared, the image data is temporarily stored in the semiconductor memory, and the stored image data is read from the semiconductor memory and transmitted. At this time, in order to reduce the information to be transmitted, a frame to be transmitted from now on,
It is preferable to detect whether or not the image data has changed for each pixel between the immediately preceding frame and the transmitted frame, and transmit only the changed image data.

Conventionally, to determine whether input data is the same as data already stored in a semiconductor memory, data is read from the semiconductor memory, and the read data is compared with the newly input data. Are compared by the ALU in the computer system, and it is detected whether or not they match.

[0004]

However, when the above-mentioned conventional determination method is adopted, in order to check whether or not there is a change in a large number of data, it is necessary to repeat the detection operation as many times as the number of data. If it takes 1 μsec to read and compare one data, and if one frame of the image is composed of 1 megapixel, it takes 1 μsec × 1M = 1 sec to detect coincidence / mismatch of data of one frame. There is a problem that it takes too much time for the detection.

The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor memory in which the detection speed of data match / mismatch is improved.

[0006]

According to the present invention, there is provided a semiconductor memory having a large number of memory areas for rewritably storing data of one word. (2) A comparison circuit that compares whether or not the new data matches the data before rewriting stored in the memory area when the new data is written. A flag register corresponding to each of the memory areas to be reset is provided.

Here, in the semiconductor memory of the present invention, in addition to the above (1) and (2), (3) a memory area corresponding to the flag register in one of the set and reset states among the flag registers It is preferable to provide an address output circuit for outputting the address of (i).

[0008]

According to the semiconductor memory of the present invention, when rewriting each memory area, the semiconductor memory itself detects a match or mismatch between data before rewriting and data after rewriting, and sets a flag register accordingly. In order to check whether or not the data has changed, it is only necessary to detect one bit of set / reset data for each flag register.
Rather than comparing one word of data such as 6 bits,
For example, the detection can be performed in about 1/3 time.

Here, in the comparison circuit of the present invention (1), for example, as shown in an embodiment to be described later, at the time of writing, data already stored in the memory area and data to be written from now on. However, the present invention is not limited to this. For example, at the time of writing, when data is written, the data already stored in the memory area may be detected. It may be possible to detect a current consumed in the memory area, which changes in accordance with the match or mismatch with the data.

In the present invention, if the address output circuit of the above (3) is provided, it is possible to directly know the address of only the memory area where the data different from the stored data is written, The operation of reading the contents and detecting the set / reset state is not required, and the operation of extracting only the changed data is further speeded up.

The address output circuit of the above (3) is a so-called associative memory (associative memory).
Memory, content addressable memory; Content
A so-called priority encoder circuit frequently used for sAddressable Memory can be used.

[0012]

Embodiments of the present invention will be described below. FIG. 1 shows an embodiment of a semiconductor memory according to the present invention,
FIG. 2 is a diagram showing an internal circuit of an M-structure basic memory cell.
FIG. 2 is a diagram showing an array of basic memory cells shown in FIG. 1.

First, when an address AD of a memory area to be written is input from the outside, the memory area to be written is selected by the decoder 10. At this time, as described below, the write data is compared with the storage contents of the memory area to which the write data is to be written.
Is set to "1", and at the same time, write data is written. On the other hand, if the write data matches the storage content of the memory area, there is no need to write the data, and the mismatch flag register 20 is reset ('0' is set).

Here, one basic memory cell A will be described with reference to FIG. First, when the address AD is input and the comparison control line 12 is set to "1" for data comparison, the basic memory cell A corresponding to the address AD is set.
Becomes Ｗ1 ’. The write data is applied to the bit line b and its inverted data bit bar line b_.

If the write data is "1" and the data held in the memory is "0", the bit line b = "1" and the node Q of the inverter latch 13 =
'0', Q _ = '1'. At this time, in the basic memory cell A shown in FIG. 1, the transistors T1 and T2 are turned on, and the signal b = '1' of the bit line b is applied to the gate of the transistor T5.
5 turns on. For this reason, the mismatch search line 16 pre-charged by the pre-charge circuit 14 is used.
Is discharged. This is detected by the dynamic sense amplifier 18 to obtain a mismatch output “1”, which is stored in the mismatch flag register 20.

In the opposite case, that is, when the write data is '0',
Similarly, when the memory holding data is "1", the "1" signal of the bit bar line b_ is applied to the gate of the transistor T5 via the transistors T4 and T3, and a mismatch output "1" is obtained. After the non-coincidence output is obtained, the comparison control line 12 is set to "0", thereby causing the word line WC to fall and the word line WRW to rise. Then
The transistors T1 and T4 are turned off, and the transistors T6 and T6 are turned off.
When T7 is turned on, the data on the bit line b and the bit bar line b_ is input to the inverter latch circuit 13 and held.

On the other hand, the write data and the basic memory cell A
Is the same, for example, if the write data is “1” and the data held in the basic memory cell is also “1”, then Q = “1” and Q _ = “0”, so that the transistor T3 Turns on and the transistor T2 turns off. The transistors T1 and T4 are turned on by the rising of the word line WC. At this time, the bit line b =
'1', but because transistor T2 is off,
The signal of b = '1' is not applied to the gate of the transistor T5. Although the transistors T4 and T3 are on, but the bit bar line b _ = '0', the transistor T5 stays off and this basic memory cell A
Does not discharge the mismatch search line 16 precharged in advance. The same applies to the opposite case, that is, the case where the write data is “1” and the memory holding data is “0”.

In the circuit shown in FIG. 2, a plurality of basic memory cells as shown in FIG. 1 are arranged in the same row direction for each same word, and the transistor T5 forms a wired OR, and one transistor in one word. Bit (basic memory cell 1
However, if there is a mismatch, a mismatch is detected for the entire word. As a result, it is possible to perform the control of writing the data in the case of a mismatch, and to eliminate the need of writing the data in the case of a match.

Further, the addresses of the mismatched words can be sequentially read out by the priority encoder circuit which receives the mismatch flag register provided for each word. FIG. 3 is a circuit diagram showing an example of the priority encoder circuit. The mismatch flag register 20 provided for each memory area is input to the priority encoder circuit 30 shown in FIG. In the priority encoder circuit 30, the higher the mismatch flag register 20 shown in the figure, the higher the priority is assigned, and among the encoder input lines 32 provided corresponding to the respective mismatch flag registers 20, '1 ', Ie
Among the mismatch flag registers 20 in which "mismatch" is stored, the mismatch flag register 20 having the highest priority (in FIG. 3, the second mismatch flag register 20 from the top).
Is output only to the encoder input line 32 corresponding to. The encoder input line 32 is connected to an encoder 34 constituting the priority encoder circuit 30.
In accordance with whether the signal '1' has been input from 2, the decoded signal, that is, the address AD of the SRAM shown in FIGS. 1 and 2, is generated and output. This address AD
Is read, and the corresponding mismatch flag register 20 is changed to "0" (match). This time, the address AD corresponding to the mismatch flag register 20 storing the next highest priority "1" (mismatch) is stored. Is output.

As described above, the addresses of the rewritten memory areas in the SRAM can be sequentially obtained.
The contents of only the rewritten memory area can be read. Thus, for example, in image processing in which a still image and a moving image are combined, if the number of pixels that change every frame is 5% of the total, the time required to detect the address of the changed data is reduced by 5% of the conventional method. Can be short-circuited.

It should be noted that the semiconductor memory of the present invention can be used not only for transmitting or processing image data, but can be widely used when it is necessary to detect whether or not data has changed.

[0022]

As described above, in the semiconductor memory of the present invention, when rewriting each memory area, the semiconductor memory itself detects the coincidence / mismatch between the data before rewriting and the data after rewriting. Since the configuration for setting and resetting the flag register accordingly is provided, the speed of detecting data coincidence and non-coincidence can be improved.

When an address output circuit for outputting an address of a memory area corresponding to a flag register in one of the set and reset states is provided in the present invention, the operation of extracting only changed data is performed at a higher speed. Be transformed into

[Brief description of the drawings]

FIG. 1 shows an embodiment of a semiconductor memory according to the present invention, SR
FIG. 3 is a diagram showing an internal circuit of a basic memory cell having an AM structure.

FIG. 2 is a diagram showing an array of basic memory cells shown in FIG. 1;

FIG. 3 is a circuit diagram illustrating an example of a priority encoder circuit.

[Explanation of symbols]

 10 Decoder 20 Mismatch flag register A Basic memory cell

Claims (2)

(57) [Claims] In a semiconductor memory provided with a large number of memory areas for rewritably storing data of one word, when new data is written to the memory area, the new data and the new data are stored in the memory area. A comparison circuit for comparing whether the data before rewriting matches the data before rewriting, and a flag register corresponding to each of the memory areas, which is set or reset according to a comparison result by the comparison circuit. Semiconductor memory. 2. The semiconductor memory according to claim 1, further comprising an address output circuit for outputting an address of said memory area corresponding to a flag register in one of a set state and a reset state among said flag registers. .