JP3369960B2 - Image display device with on-screen function and image display method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device having an on-screen function for displaying desired characters such as characters on a CRT image.

[0002]

2. Description of the Related Art As an image display device, a video from an image of a surveillance camera is received, the image is displayed on a CRT, and characters such as recording characters are independently displayed on the screen in association with the image. 1 illustrates an example of a device. FIG. 8 is a schematic diagram showing the connection between the image display device (5) and the CRT (4). The image display device (5) is provided with a plurality of terminals (50) (50) to which an image from the surveillance camera is input, specifically, four terminals. The image display device (5) has a screen division function of dividing the screen into, for example, two vertically and two horizontally, a total of four, and displaying an image from each terminal (50) (50) on each divided screen. Depending on the mode signal input by the user, it is possible to switch between a state in which one screen is displayed as it is and a state in which the screen is divided. Figure 9
FIG. 3 is an internal block diagram of the image display device (5). The four terminals (50) (50) are connected to the screen division control circuit (2).
The screen division control circuit (2) displays an image from the respective terminals (50) (50) at each section of the CRT (4),
Detailed description will be given later. A character string which is an additional signal from the on-screen circuit (3) is superimposed on the output signal from the screen division control circuit (2). The additional signal includes a character string indicating the installation location of the surveillance camera, for example. In the following description, a character is exemplified as a character, but it may be a symbol or a figure.

FIG. 10 is an internal block diagram of the on-screen circuit (3) (see Japanese Patent Laid-Open No. 7-131734). The character generator (30) generates character data to be displayed as an on-screen image and writes it as pattern data in dot units in a video RAM (hereinafter abbreviated as "VRAM") (31) as shown in FIG. One pixel of the on-screen character corresponds to one bit in the VRAM (31). VRAM
The counter (33) connected to (31) has a synchronizing signal of the video signal displayed on the CRT (4) and an on-screen circuit (3).
A clock (CLK) signal is input from a frequency generator (not shown) located outside the. The counter (33) outputs the row selection number VR according to the position of the scanning line based on the clock signal.
Supply to AM (31). The VRAM (31) inputs one line of on-screen characters to the shift register (32) by the line selection number. The shift register 32 outputs characters as an on-screen signal for each column in response to a clock signal from a frequency generator. Since the length of one pulse of the clock signal corresponds to the width of one pixel of the on-screen character, if the clock signal has a constant frequency as shown in FIG. The character 12 (a) is output. Therefore, the on-screen circuit (3) causes characters to be superimposed on each divided image as shown in FIG.

Since the length of one pulse of the clock signal corresponds to the width of one pixel of the on-screen character, FIG.
As shown in, when the frequency of the clock signal is high, the width of the on-screen character is reduced, and when the frequency is low, the width of the on-screen character is expanded. Assuming that FIG. 12 (a)
Assuming that the frequency corresponding to the size of the letter A is 5 MHz,
The frequency corresponding to the size of the letter A in 2 (d) is 10 MHz. The on-screen circuit (3) is a general-purpose product composed of one IC, and the same product is mass-produced, so that it is inexpensive. In such a general-purpose on-screen circuit (3), since the capacity of the character generator (30) is small, the number of characters generated from the character generator (30) is small.

[0005]

On-screen characters output by a clock signal with a low frequency have a wide character width. Therefore, if the characters are copied as they are into each divided screen as shown in FIG. The characters are large compared to the size, which causes a feeling of strangeness. Therefore, an on-screen character having a narrow character width may be output by a clock signal having a high frequency and displayed on a divided screen. However, if the character width is simply reduced, the character string is offset to the left end of the screen as shown in FIG. In this case, the generation timing of the clock signal can be shifted so that it is centered in the horizontal direction of the screen as shown in FIG. Remain. Also, if a large number of characters are generated from the character generator (30) and the character string can be displayed seamlessly across the left and right of each split screen, the problem that the character string is offset to the screen is solved, As described above, since the number of characters generated from the character generator (30) is small, such a display cannot be made unless a character generator having a large number of characters is specially ordered and manufactured. Further, as shown by the alternate long and short dash line in FIG. 9, an on-screen circuit (3a) is provided for each divided screen, and the timings of the clock signals supplied to both on-screen circuits (3) and (3a) are different, and shown in FIG. As described above, it is possible to copy the character string to the left and right center portions of each divided screen. However, the extra on-screen circuit (3) is required, which leads to an increase in cost. It is an object of the present invention to copy an on-screen signal to each divided screen without any discomfort by using a general-purpose on-screen circuit.

[0006]

An image display device includes division control means for arranging and displaying divided screens in the screen width direction, and character generating means for continuously outputting characters to be displayed on the screen. A frequency generating means for outputting the reference clock and a width varying means for changing the width of the character based on the frequency of the reference clock and outputting the changed width on the screen. The frequency generating means, the timing adjusting means for controlling the generation timing of the frequency is connected, the timing adjustment
A timer (15) is connected to the adjusting means. The timing adjusting means, based on the width length of the screen divided in the width direction and the width length of the character string to be displayed in the divided screen ,
A scan in which the first character of each character string should be displayed
Determine the time T1 from the start and scan using the timer (15)
After a lapse of time T1 from the start , the character string is displayed at a desired position in each screen width direction.

[0007]

[Action and Effect] The timing adjusting means, the width length of the screen is divided in the width direction, dividing the character string to be displayed
Based on the width and width of the screen, the start character of each character string
Determine the time T1 from the start of scanning when the lacquer should be displayed
To do. After the lapse of time T1 from the start of scanning,
Display the character string at the desired position. That is, the character string can be displayed at a desired position in the width direction of each divided screen by changing the output timing of the pulse from the frequency generating means. The character string is displayed at a position desired by the user in each divided screen, and it is possible to prevent the character string from being displayed unevenly on each divided screen as in the conventional case.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION An example of the present invention will be described in detail below with reference to the drawings. The same configurations as those of the related art will be denoted by the same reference numerals and detailed description thereof will be omitted. FIG. 1 is an internal block diagram of an image display device (5) according to this example. As before,
The four video signals are input to the image display device (5). In the image display device (5), a controller (6) which issues a mode signal by a user operation, a screen division control circuit (2) which divides the screen of the CRT (4), and an internal frequency generation circuit (1).
2) and a control circuit (1) including a synchronization signal generation circuit (11),
It has an on-screen circuit (3). On-screen circuit
The configuration of (3) is the same as the conventional example shown in FIG. The sync signal from the sync signal generation circuit (11) is the screen division control circuit.
(2) and the on-screen circuit (3). As before, the on-screen characters from the on-screen circuit (3) are superimposed on the split image.

The control circuit (1) includes a mode discriminating circuit (10) and a timing adjusting circuit (13) in addition to the frequency generating circuit (12) and the synchronizing signal generating circuit (11). The mode discrimination circuit (10) receives the mode signal input from the controller (6),
A signal indicating whether to divide the screen is transmitted to the screen division control circuit (2). The timing adjustment circuit (13) has an auxiliary memory (14).
It is a characteristic part of the present invention that is connected to the timer (15) and controls the timing of generation of the clock signal from the frequency generation circuit (12) as described later. The frequency generation circuit (12) is composed of, for example, a crystal oscillator, and the timing adjustment circuit (13) generates a pulse by supplying power to the crystal oscillator.

FIG. 6 is an internal block diagram of the screen division control circuit (2). The screen division control circuit (2) has various configurations, but this was previously disclosed by the applicant in Japanese Patent Publication No. 61-1562.
This is similar to the structure disclosed in Japanese Patent Laid-Open No. 9-98353 and No. 9-98353. The screen division control circuit (2) has four memories (20) (20a) (20b) corresponding to the number of divided screens.
(20c) is provided, and the video signal from the plurality of terminals (50) and (50) is converted into a digital signal by the A / D converter (21), and then the changeover switch (22) and the combination control circuit.
It is stored in the memories (20) (20a) (20b) (20c) via (23). The changeover switch (22) is switched by the synthesizing control circuit (23), and the synthesizing control circuit (23) is based on the synchronization signal and is used for one scanning line in the memories (20) (20a) (20b) (20c). Stores video signal. The synthesis control circuit (23) also issues a latch signal to the memory (20) (20a) (20b) (20c), and the memory (20) (20a) (20b) (20c) that receives the latch signal scans the stored signal. The video signal for one line is output.

First, the synthesis control circuit (23) triggered by the pulse of the synchronizing signal stores the video signal of the first scanning line in the first memory (20). The video signal of the first scanning line is supplied from one terminal (50). Next, based on the next pulse of the synchronization signal, the synthesis control circuit (23)
Switches the selector switch (22) so that the video signal of the second scanning line , that is, the signal supplied from the other terminal (50)
The latch signal is stored in the memory (20a) of
To memory (20). Scan lines from the first memory (20)
One video signal is output. After that, this operation is the first
Between the second memory (20a) and the second memory (20a).
From the 262.5th scanning line, the third memory (20b) and the fourth memory
The video signals are alternately stored in the memory (20c).

The video signals output from the memories (20) (20a) (20b) (20c) are input to a multiplexer (24). FIG. 7 is a diagram showing signal processing in the multiplexer (24).
The video signal S1 for one scanning line stored in the first memory (20) is compressed in the multiplexer (24) and stored in the H / 2 time domain from the beginning of 1H. Next memory
The video signal stored in (20a) is stored in the remaining H / 2 time domain. That is, scan line 1 in the multiplexer (24)
The signal S from the two memories (20) (20a) is provided in the area for this line.
1 and S2 are multiplexed and combined as a single video signal. From the 262.5th scanning line , the remaining two memories (20
b) The signals S3 and S4 from (20c) are combined. In this way, an image of 525 scanning lines is formed for each vertical synchronization signal period, and when this is converted into an analog signal by the D / A converter (25) and displayed on the CRT (4), it is divided into four. The displayed screen will be displayed. In FIG. 6, four memories (20) (20
Although a), (20b), and (20c) are used, in reality, one large-capacity memory free area is often divided into four and used. Further, the memories (20) (20a) (20b) (20c) used are those capable of storing video signals of 525 scanning lines , and for each vertical synchronization signal,
You may output to a multiplexer (24) and synthesize | combine a screen.

The present invention is characterized by the clock signal generation timing of the frequency generation circuit (12) for generating on-screen characters. As described above, when the screen is divided, if the on-screen characters are large, the ratio of the characters to the screen increases, which causes imbalance. Therefore, the frequency of the clock signal is increased to narrow the width of the on-screen characters. . At this time, the timing adjustment circuit (13) shown in FIG. 1 operates the clock signal generation timing to display an on-screen character at an arbitrary start position for each divided screen. The user controls the mode signal (6)
When the input is made, the mode discrimination circuit (10) judges whether or not the screen should be divided, and when the screen is to be divided, a signal to that effect is issued. When the screen is divided and on-screen characters are to be displayed, a signal to that effect is issued to the timing adjustment circuit (13). The timing adjustment circuit (13) receives the signal and changes the frequency generation timing of the frequency generation circuit (12).

The user inputs a character string and the number of characters to be displayed on each screen from the controller (6). As shown in FIG. 3 and FIG. 2 (a), for example, a character string from letters A to H is displayed on the lower half of the screen in the left half, and letters K to R are written on the lower half of the screen on the right half. Each character string is displayed. The start position of each character string is adjusted and displayed in the center of the divided screen in the width direction. Each character has a size corresponding to a frequency of 10 MHz, as indicated by the character "A" in Fig. 12 (d). Is. Further, in FIG. 3, the character strings are displayed in upper and lower two stages, which is the synchronizing signal generation circuit (11) of FIG.
On-screen circuit (3) based on the horizontal sync signal from
This is because the character strings are displayed at the upper and lower portions of the screen. I, which is the middle character in the character string from A to R
The reason why and J are not displayed will be described later.

The procedure for displaying the character strings from A to R is shown in the flowchart of FIG. controller
After the mode signal is input from (6) (S1), the timing adjustment circuit (13) first calculates the time T1 (see FIG. 2B) from the left end of the screen until the first character A is generated (S2). ). left
Since the length of the character string from A to H to be displayed on the split screen is known in advance, in order to display the character string in the central part of the split screen, the first character of the character string is displayed at any position on the screen. It is easy to determine whether to set to. In other words,
Since the frequency of the clock signal is known, onscreen
The width of the character is known, and the length of the character string from A to H is known.
It Since the width of the split screen is also known, the character string is split
Position the first character of the string to display it in the center of the surface
The distance L1 (see FIG. 3) from the left edge of the screen to be displayed is known. Ta
The aiming adjustment circuit (13) reaches this distance L1 from the start of scanning.
Then, the time T1 until it is reached is obtained. The time T1 is calculated and calculated by the timing adjustment circuit (13) from the ratio of the distance L1 (see FIG. 3) from the left end of the divided screen to the character A and the width of the entire screen. That is, the time for scanning the entire screen horizontally is 1H.
That is, since 1 sec / 15750≈64 μsec in the NTSC system, the time T1 is a value obtained by distributing the time of 1H by the ratio of the distance L1 and the width of the entire screen. This time T1 is
It is temporarily stored in the auxiliary memory (14) connected to the timing adjustment circuit (13). The timing adjustment circuit (13) has a timer (1
5) is operated to measure the time T1, and during this period, no pulse is generated from the frequency generation circuit (12) (S3).

Next, after the lapse of time T1, the frequency generating circuit (1
A pulse is generated from 2) and an on-screen character is displayed (S4, S5). In FIG. 2A, one character corresponds to one pulse, but this is for convenience of illustration. Actually, as described above, a plurality of pulses are used to display a character. The time from displaying A to the last character H is shown in Fig. 2 (b).
Is T2, and this time T2 is easily obtained by the length of the character string from A to H. This time T2 and T3 which will be described later are similar to the time T1 in the timing adjustment circuit (1
Calculated in 3) and stored in auxiliary memory (14).

The timing adjusting circuit (13) stops the output of the pulse from the frequency generating circuit (12) after the lapse of time T2.
(S6, S7). Next, after a lapse of time T3, a pulse is again generated from the frequency generation circuit (12) (S8, S9). This time T
3 corresponds to the distance L2 (see FIG. 3) from the character H displayed on the divided left half screen to the character K displayed on the right half screen. The distance L1 and the string from A to H
Since the length is known, the distance L2 and the distance L2 are scanned.
The time T3 required for the calculation can also be calculated. The time for displaying the character string from the characters K to R is the same as T2 because the number of characters is the same as from A to H, and the timing adjustment circuit
(13) stops the pulse output after the lapse of time T2 (S1
0, S11). After that, scanning is repeated from the left end of the screen. Since the times T1, T2, and T3 are stored in the auxiliary memory (14), when the CRT (4) is de-energized and the character string is displayed again on the split screen, the character string is displayed at the left-right center of each split screen. Displayed in the section.

In this way, by adjusting the output timing of the pulse from the frequency generation circuit (12), the character string can be displayed at a desired position in the left-right direction on each screen. Therefore, it is possible to prevent the character strings from being displayed unevenly on the divided screens as in the related art. In addition, in FIG. 3, among the characters from A to R, I and J located in the middle
Is not displayed. This is for the following reason. Characters A to R are sequentially output from the character generator 30 (see FIG. 10) at regular intervals, and the order cannot be changed because the on-screen circuit 3 is a general-purpose product. Therefore, as long as this on-screen circuit (3) is used, it is not possible to change only the time interval between specific adjacent characters, specifically, the time interval between H and I and J and K. When a pulse is generated during the time T3, the letters I and J are displayed at the right end of the divided screen,
This is contrary to the original purpose of displaying a character string in the left and right center of the split screen. In particular, when a pulse of level Hi is continuously output at time T3, the character I as shown in FIG.
And J are displayed horizontally, which makes it rather unattractive. Therefore, the section between the letters I and J is left blank without being displayed.

The content of the present invention is not limited to a device for dividing a screen into four parts. That is, since the display position of the on-screen characters is adjusted according to the number of divided screens, the screen is divided into 16 parts as shown in FIG. 16 and the divided screens as shown in FIG. Even if one of them is further divided, it is possible to display the on-screen characters in correspondence with the screen.

The above description of the embodiments is for explaining the present invention, and should not be construed as limiting the invention described in the claims or reducing the scope. The configuration of each part of the present invention is not limited to the above-mentioned embodiment, and it goes without saying that various modifications can be made within the technical scope described in the claims.

[Brief description of drawings]

FIG. 1 is an internal block diagram of an image display device.

FIG. 2A is a character string displayed on left and right divided screens, and FIG. 2B is a pulse waveform for displaying the character string.

FIG. 3 is a front view showing a state in which a character string is displayed at the center of each split screen.

FIG. 4 is a front view showing a state where a character at the center of the screen is enlarged.

FIG. 5 is a flowchart showing a procedure for displaying a character string on each split screen.

FIG. 6 is an internal block diagram of a screen division control circuit.

FIG. 7 is a diagram showing video signal processing in a multiplexer.

FIG. 8 is a front view of the image display device.

FIG. 9 is a block diagram of a conventional image display device.

FIG. 10 is a block diagram of an on-screen circuit.

FIG. 11 is a diagram showing a storage state of a character string in a VRAM.

FIG. 12 (a) is a character string output when a pulse having a constant frequency is received, (b) is a pulse at that time, (c) is a pulse whose frequency is changed over time, (d) Indicates the character strings output when the pulse is received.

FIG. 13 is a front view showing a state in which large characters are displayed on a split screen.

FIG. 14 is a front view showing a state in which a character reduced in the width direction is displayed in the center of the split screen.

FIG. 15 is a front view showing a state in which the characters reduced in the width direction are displayed in a one-sided manner at the left end of the split screen.

FIG. 16 is a front view of a screen divided into 16 pieces.

FIG. 17 is a front view of a screen in which one of the divided screens is further divided.

[Explanation of symbols]

(1) Control circuit (2) Screen division control circuit (3) On-screen circuit (5) Image display device

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Claims (3)

(57) [Claims] 1. A division control means for displaying divided screens arranged in the screen width direction, a character generating means for continuously outputting characters to be displayed on the screen, and a frequency generating means for outputting a reference clock. In the image display device having the width changing means for changing the width of the character based on the frequency of the reference clock and outputting the changed width on the screen, the frequency generating means has a timing adjusting means for controlling the frequency generation timing. Connected and timing adjustment means
A timer (15) is connected to the timing adjustment means , and the timing adjustment means adjusts the width of the screen divided in the width direction.
Length and width of the character string to be displayed within the split screen
The first character of each character string is displayed based on
Determine the time T1 from the start of scanning, and set the timer (15)
An image display device, wherein a character string is displayed at a desired position in each screen width direction after a lapse of time T1 from the start of scanning using . 2. The timing adjusting means outputs the last character of the character string displayed on one screen among the plurality of divided screens, and the character after the last character string,
From the frequency generating means in the section between the first character of the character string displayed on the screen adjacent to the first screen
The image display device according to claim 1, which emits a signal not to generate a pulse . 3. A division control means for arranging and displaying the divided screens in the screen width direction and a character generating means for outputting a character to be displayed on the screen are provided, and the character generating means continuously outputs. From the character, a step of selecting a character string to be displayed on each screen divided into a plurality of screen width directions, and at the time of displaying the plurality of character strings, the size of the divided screen and each character string to be displayed are divided screens. The first character of each character string
Determines the time T1 from the start of scanning that the data should be displayed
A screen display method including the steps of displaying each character string at a desired position in each screen width direction after a lapse of time T1 from the start of scanning.