JP3366634B2 - Integrated electronic shutter for charge-coupled devices - Google Patents

Description

FIELD OF THE INVENTION The present invention relates to electronic shutters for use in charge coupled devices (CCDs), and in particular to providing high speed computation and CCDs.
The invention relates to a new electronic shutter integrated in a backside illuminated frame transfer CCD structure to reduce smearing that frequently occurs when transferring an image from the detection area to the image storage area of the device.

BACKGROUND OF THE INVENTION Photodetector arrays require fast shuttering to eliminate image blurring caused by smear and / or to separate light pulses that are close in time. In high speed frame transfer applications where the image transfer time is comparable to or greater than the image gaze or integration time, image smear under such conditions can significantly impair the image information, thus eliminating image smear. is important. Requires short exposure times and /
Or, as an example of a device having high sensitivity to smear, a high-speed photographic device, a target tracking device, a range gating (range
gating) devices and real-time adaptive optics.

Many CCD type frame transfer photodetector arrays are
The image integration time, or image exposure time, is substantially longer than the image transfer time and is usually operated such that image smear is not a problem. However, such methods severely limit the use of imaging devices of the above type and cannot be used in applications where it is desirable to provide high frame transfer rates or short exposure times. Other solid state image sensors (shutter function)
nsor) can be configured to provide high frame transfer rates or short exposure times, but in order to do so, it loses the ability to obtain high pixel fill factors or has a relatively high degree of complexity. Are often required, thus increasing costs and making manufacturing more difficult.

To provide a CCD imager using a high speed electronic shutter that can be specifically incorporated into the structure of a CCD, for example a backside illuminated frame transfer CCD, to provide a device with a simpler structure that can be manufactured at a reasonable cost. desired.
Such devices have substantially reduced or eliminated smear, high pixel fill factors (substantially 100% or close to), variable integration times, and low noise operation. Occurs, and near-reflec-limited quantum efficiency (near-reflec) in the visible spectrum.
motion-limited quantum efficiency).

Other solutions to the image smear problem have been proposed when the integration time is less than or equal to the transfer time, but none of them achieve the desired operation as described above. For example, it has been proposed that image smear can be eliminated by performing post-processor data operations on image data using a suitably designed algorithm. However, such a method is time consuming and expensive to achieve. Another proposed method is to place an electro-optical shutter such as a Pockel or a Kersel in front of the CCD. Such electro-optical shutters have a relatively high speed, i.e. switching times on the order of nanoseconds, but have other problems, for example requiring very high operating voltages (i.e. often in the kilovolt range). They also have a relatively high loss of unpolarized light (eg 50%), are temperature sensitive and tend to produce optical aberrations.

In yet another method, it has been proposed to fabricate electronic shutters in CCD structures by various methods. A typical example of this is a line-to-line transfer CCD in which photoelectrons collected in the light sensitive area are transferred into the channels of adjacent CCDs at the end of the image capture operation. Adjacent CCD channels are covered by a blocking layer that prevents further collection of photoelectrons. In such devices, the image signal contains reasonably negligible image smear and can be clocked out of the chip. Shuttering in this manner takes the time it takes to transfer charge from the photosite to the CCD channel (typically a single clock cycle).
Only needed. However, in such a structure, the pixel fill factor is significantly reduced (eg, less than 100%) because a significant portion of each pixel area must be used by the CCD transfer channel.

Another example of a method is a frame transfer CCD imager that performs a shutter function by transferring the entire image, or all of its pixels, from the imaging array into the frame storage array. Here, the frame storage array is covered by an opaque material. According to such a shutter function, image smear depending on the pixel position occurs, and the image smear effect is
It occurs and is significant in the pixels in the imaging array that are furthest from the frame store array. The number of "smear" photoelectrons in such a pixel is inversely proportional to the clock rate times the number of pixels in the imaging array column.

Yet another CCD imager creates a shutter function by placing a light sensitive area on the CCD transfer channel. Such a method provides a light collecting pixel with a high pixel filling factor and can shutter the optoelectronic signal relatively quickly. Unfortunately, however, the photosensitive layer causes other operational problems of the CCD, such as image lag,
The device has a high operating voltage and is prone to relatively large and unwanted dark currents.

SUMMARY OF THE INVENTION The present invention is an electronic shutter developed to be integrally formed within a backside illuminated frame transfer CCD imager, which has a fast switching time, which is extremely high or substantially 10%.
0% pixel filling factor and high extinction ratio (extinction rati
o), while providing an electronic shutter that eliminates or minimizes the above-mentioned problems that occur in other structures.

According to the invention, a charge coupled device responsive to an input optical signal comprises a pixel array formed in a substrate,
Each pixel has a depletion well region. Means are provided that are operable in the first image exposure state (shutter "open" state) to extend the depletion well region of each pixel into the substrate. During such a first state, substantially all of the incident photoelectrons generated by the input optical signal at each pixel are
Accumulates in the expanded depletion well area. In addition, it is operable in a second storage state (shutter “closed” state) to reduce the depletion well region of each pixel and substantially prevent further photoelectrons from accumulating within the reduced depletion well region. Means are provided. Following storage, stored photoelectrons can easily be transferred from the reduced depletion well area to the framed array area. Such operation substantially eliminates smear, provides high speed shutter operation, and also provides high extinction ratio, high pixel fill factor and high data rate. Such operation is accomplished with a relatively simple structure that can be relatively easily manufactured at reasonable cost.

Details of the invention   The present invention will be described more clearly with reference to the accompanying drawings.

FIG. 1 is a plan view of a frame transfer CCD device of the present invention.

  2 is a plan view of an example pixel of the device of FIG.

FIG. 3 is an enlarged view of a cross section along the line segment 3-3 of the pixel example of FIG.

FIG. 4 is a cross-sectional view of an example pixel of the device of FIGS. 1-3 in the shutter “open” state.

FIG. 5 is a cross-sectional view of an example pixel of the device of FIGS. 1-3 in the shutter “closed” state.

FIG. 6 is a graph showing the normalized CCD output signal measurements as a function of time in the shutter rise and fall regions of a typical device of the present invention.

FIG. 7 is a graph showing the pixel response of a typical device of the present invention as a function of shutter integration time.

FIG. 8 is a graph showing an example of typical impurity concentration in a predetermined region of the device of the present invention.

FIG. 9 is a graph showing an example of typical impurity concentration in another predetermined region of the device of the present invention.

FIG. 10 shows the FIG. 1 used in the “iris” mode of operation.
4A-4C are cross-sectional views of example pixels of the device of FIG.

FIG. 1 illustrates three-phase inputs π1, π2 and π known to those skilled in the art.
3 is a schematic diagram of a frame transfer CCD device 10 including a 3-phase imaging array 11 of pixels having terminals suitable for 3 and an input gate terminal 12. FIG. The input diode 13 of each pixel is connected to the input diode electrode 14, and the shutter drain region 15 between each pixel has a shutter drain electrode 16 connected to it as shown. The frame storage array 17 is formed adjacent to the imaging array 11, and in the array 17,
The charges of all the frames accumulated in each pixel of the imaging array 11 are transferred according to the known frame transfer CCD operation. Normal three-phase control inputs π1, π2 and π3
Is also included in the frame storage array 17. Array 17
The frame data stored in the frame is clocked out from the frame store to the output register 18, from which the output gate
18A and video output 19 are provided using the appropriate three-phase clock signals .pi.1, .pi.2 and .pi.3 associated with output register 18. As is known to those skilled in the art who are familiar with the general structure and operation of frame transfer CCD devices,
Suitable channel stop regions 20 are formed between each vertical charge transfer channel group 21.

FIG. 2 is a plan view of an example of one backside illuminated pixel in the imaging array 11 of the n-channel frame transfer CCD device 10 of FIG. This device includes the electronic shutter of the present invention as described in detail below. FIG. 3 shows a side view of the line segment 3-3 of the pixel of FIG. As can be seen, each pixel is formed in a p-type semiconductor material substrate 22, such as a p-type silicon substrate. The structure shown here, except for the integrated electronic shutter structure that is integrally formed therein,
It is a nearly standard frame transfer pixel structure. Such a shutter includes an n ⁺ shutter drain region 15 disposed between longitudinal transfer channels within the imaging array and a stepped p-type buried layer 26. The p-type buried layer 26 extends across the pixel and its depth varies between a first depth 23 and a second depth 24 as shown in FIG. The portion of the p-type buried layer 26 that is at the first depth typically serves as the n ⁺ buried channel 25 and shutter drain region 15 that acts as the collection portion of the pixel.
Centered under both of, and between these,
That is, the portion of the p-type buried layer 26 at the second depth functions as a storage area for the already collected charges.

8 and 9 show general curves representing the impurity concentrations in the regions of the typical pixels shown in FIGS. 2 and 3. FIG. 8 shows an n-type buried channel region 25 and p in the center of the pixel.
The logarithmic concentration in the mold burying layer region 22 is calculated as the line segment 8-8 in FIG.
FIG. 9 shows the logarithmic concentration in the n-type shutter drain region 15 and the p-type buried layer region 22 on the left side of the pixel along the line segment 9-9 in FIG. Expressed as a function of depth.

The operation of the device of FIGS. 1-3 is best described with reference to FIGS. 4 and 5, which show shutter “open” (FIG. 4) and shutter “closed” (FIG. 5) operating modes, respectively, in a normal pixel. .

When the shutter is in the open mode, it is desired to capture all the photoelectrons of the incident light image illuminating each pixel from the back surface 30 of the substrate 22, as indicated by the dashed arrow 31. In such a mode, photoelectrons are collected in the n-type channel depletion region 25 formed in the substrate. For this purpose,
During image capture, or shutter open mode, a voltage V _IA having an appropriately selected value is applied to the gate electrode area 33 of the imaging array clock electrode 32 (this electrode is connected to each pixel as shown in FIG. 4). Applied). When the voltage V _IA is applied, the n-type buried channel depletion region 25 (see FIG. 3) expands to form an expanded n-type buried channel depletion region 25A. This region 25A extends from the gate dielectric region through the p-type buried layer 26 (shown in phantom in FIG. 4) into the p-type lightly doped substrate. In order to maintain the junction at a reverse bias, the voltage V _SD is applied to each pixel via the shutter drain electrode 34, as shown in FIG. The voltage V _SD depends on the p-type buried layer 26 when the depletion in the drain region is
Should not penetrate. Photoelectrons (ie, negative charges) generated by the optical signal entering the substrate are attracted to the n-type buried channel depletion region 25A expanded by the electric field established by the voltage V _IA in each pixel, and the charge is accumulated therein. To be done. The non-depletion region of the p-type buried layer 22 is
An electric field is generated to repel photoelectrons from the shutter drain region 15.

Therefore, photoelectrons enter the n-type buried depletion channel 25A from the p-type substrate through the region 35 in the shallower portion of the p-type buried layer 26 near the center of the pixel. A potential barrier similar to that at n + shutter drain is p
It prevents photoelectrons from directly entering the n-type buried channel region above the region 36 in the deeper part of the mold buried layer 26. The potential well in the n-type buried channel adjacent to the deeper p-type buried layer region 36 has a shallower region 35.
Have a higher positive charge than those adjacent to. As a result, the electrons moving toward the shallower p-type buried layer portion 35 are transferred to the n-type buried channel storage depletion region 25B above that portion of the p-type buried layer 26. The depletion region 35 below the central collection portion of the pixel is insensitive to approximately the maximum amount of trapped photoelectrons, ie the expansion remains constant. Photoelectrons exceeding this maximum value are shared between the accumulation depletion region and the collection depletion region below the p-type buried layer 26 of the pixel, and the entire depletion region is gradually collapsed.

When the electronic shutter is closed (FIG. 5), a voltage V _IA having another selected value is applied to the imaging array electrode 32. This voltage has a lower value than when the shutter is open and is not sufficient for the depletion region 25 to decay and expand through the p-type buried layer 22 and the depletion region 25A to the region 25B as shown. It has a value that reduces. However, such a voltage is sufficient to transfer charge from pixel to pixel. During the shutter closed mode, a potential barrier is created by the p-type buried layer 26 between the reduced n-type buried channel region 25B and the p-type substrate. This barrier is accompanied by an electric field that rejects photoelectrons from the reduced n-type buried channel 25B. The voltage V _SD applied to the n + shutter drain during the shutter close mode is greater than that applied during the shutter open mode, causing the drain depletion region 15 to
As shown by the region 15A in FIG. 5, it extends deeper than the p-type buried layer to the inside of the p-type substrate. Under such conditions, photoelectrons (negative charges) are attracted to the enlarged shutter drain region 15A by the electric field established therein, so that they are neither detected nor collected within the reduced n-type buried channel region 25.

In summary, when the shutter is open, the enlarged n-type buried channel depletion region 25A in each pixel captures substantially all of the photoelectrons incident on it from the incident light image,
Accumulate them in the depletion zone 25B. The p-type buried layer 26 is
Prevent such incident optoelectronic charge from being attracted to the drain area so that substantially all charge entering each pixel is captured (in effect giving 100% pixel fill factor) when the shutter is in open mode .

In the shutter-closed mode, the reduced n-type buried channel region retains the charge that was trapped when the shutter was open, so that no additional charge was trapped, and no additional charge was buried. Entry into the channel is blocked by the p-type buried layer 26, and the incoming charge is drained from the substrate through the expanded drain depletion region 15A.

Full shutter operation produces a fast-acting shutter having a high extinction ratio such that substantially all incident photoelectron charge is stored when open and substantially no charge is stored when closed. The accumulated charge can be transferred from the n-type buried channel area 25 of each pixel to the corresponding frame storage area of the array 17 using a conventionally known frame transfer technique without smear.

Unlike previously proposed shutter devices that require high voltage for operation, the device described herein uses electrodes 32 and
Use a relatively low voltage for 34. That is, during the shutter open mode, the voltage V _IA is 18V ≦ V _IA ≦ 25V and the voltage V _SD is 0V.
V ≦ V _SD ≦ 6V. The voltage during shutter close mode is
-6 ≤ V _IA ≤ 12V and 6V ≤ V _SD ≤ 18V.

It has been found that in such an operation, the extinction ratio increases as the wavelength becomes shorter. The extinction ratios for the three wavelength examples in the prototype device manufactured according to the present invention were as follows. @ (Nm.) Extinction ratio 450> 5500 543.5 5100 632.8 107 As can be seen from the table above, the extinction ratio is higher than 5000 at wavelengths of about 540 nm and below, and this ratio at wavelength 450 nm is
It was higher than could be measured depending on the experimental conditions used.

The shutter rise and fall times of an exemplary embodiment of the invention are measured by stepwise applying light pulses through the shutter transition region (i.e., from closed mode to open mode and from open mode to closed mode). CCD output response vs. time step was recorded). Shutter function S representing the intrinsic shutter speed
(T) can be defined as the fraction of detected photoelectrons with respect to the total number of photoelectrons present, and the extinction ratio is assumed to be infinite. The CCD output response O (t) can be expressed as a composite product of the shutter function S (t) and the photoelectron pulse input I (t), and is written as O (t) = S (t) * I (t). It FIG. 6 shows a normalized value of the measured CCD output signal as a function of shutter rise and fall operation time, and the switching time is 10% to
Taken between 90% values, it turns out to be less than 55ns.

The use of a stepped or dual depth p-type buried layer 26 allows the use of n-type buried depletion regions that are independent of the signal stored in the well to approximately the maximum amount. FIG. 7 shows a dual depth p-type buried layer 26 (see triangle plot points in FIG. 7) compared to using a single depth p-type buried channel (see square plot points in FIG. 7). Shows the pixel response (ie, the number of electrons captured per pixel) versus the integration time (ie, shutter open time). In such an operation, the shutter drain was biased so that the enlarged n-type buried depletion region 25A in each case penetrated the p-type buried layer and slightly exceeded it.
As long as the depletion zone related to the detection area is constant, the pixel response should depend almost linearly on the integration time (solid line in Figure 7). The results in FIG. 7 show that the pixel response in the dual depth p-type buried layer remains linear until the "filled" state of about two-thirds of the pixels as shown. The deep p-type buried layer is shown to be non-linear at relatively low signal levels.

Therefore, according to the present invention, the electronic shutter is successfully incorporated into the structure of a frame transfer backside illuminated CCD imager. The electronic shutter has a high extinction ratio, for example, an extinction ratio of 5000 or more for wavelengths shorter than 540 nm, and can be effectively switched in a very short time, for example, about 55 ns or less.

In addition, the stepped or double depth p as described above
The use of a buried mold layer produces a pixel having separate photoelectron collection and storage areas, which results in a substantially linear response up to a substantial "filled" fraction of the pixel.

In addition to operating the device of the present invention as an electronic shutter, such device can also be operated in the form of a voltage controlled diaphragm. In such an operation, the depletion region 15A associated with the n + shutter drain and the depletion region 25A associated with the n-type buried channel extend beyond the n-type buried layer 26 and into the p-substrate 22 as shown in FIG. . Each shutter drain region and n-type buried channel region collects a portion of the photoelectrons (charges) from the incident optical signal. The photoelectron fraction collected by the n-type buried channel collection area 25A is
It can be reduced by raising the shutter drain voltage V _SD or lowering the imaging array gate electrode voltage V _IA . As the shutter drain voltage increases, the aperture is closed by expanding the depletion region 15A into the substrate 22 and creating an electric field that attracts more photoelectrons from the n-type buried channel region 25A to the n + shutter drain 15. The shutter drain eliminates a larger fraction of the total number of input signal photoelectrons present as the shutter drain voltage increases. Therefore, less input signal electrons are collected by the n-type buried channel detection area 25A. That is, aperture opening can be controlled by adjusting the value of either V _IA or V _SD or a combination thereof.

The use of electronic shutters in such "aperture" mode of operation makes it possible, for example, to maintain a suitable contrast, especially under highly illuminated imaging conditions, for example under very bright incident signals. Conventional optical detector arrays that are unable to provide such aperture control tend to lose pixel contrast at high input signal levels, that is, because all pixels are at substantially the same level and thus lose contrast, with little or no contrast. The image has no texture, which is effectively a blank screen.

While the particular embodiments of the invention described above represent preferred embodiments of the invention, those skilled in the art will be able to make modifications within the spirit and scope of the invention. Therefore, the invention is not limited to the specific embodiments described herein except as set forth in the claims.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Koshiki, Bernard Bee, USA, Masachi Yousets-01720, Acton, Huart Pond Road 39 (72) Inventor Savoy, Eugene Day USA, Masachi Yousets-01742, Concord, Bethford Ord Street 689 (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 27/148 H04N 5/335

Claims (12)

(57) [Claims] 1. A charge-coupled device having an array of pixels formed in a substrate, wherein each of said pixels has a depletion well region, said array being responsive to an input optical signal, Expanding the well area of each pixel to accumulate substantially all of the incident photoelectrons generated by the input optical signal in each pixel in the expanded depletion well area, and the expanded depletion of each pixel. Charge coupled device comprising means for reducing a well region and means for substantially inhibiting accumulation of photoelectrons generated by the input optical signal in each pixel within the reduced depletion well region. . 2. An electronic shutter for use in a charge-coupled device having an array of pixels formed in a semiconductor substrate, said array being responsive to an input optical signal, each of said pixels comprising: A gate electrode on the surface of the substrate, a depletion well region formed in each pixel, a plurality of drain depletion regions formed between adjacent pixels of the array, and in each pixel A buried layer formed below the depletion well region and its drain depletion region, and an enlarged depletion well region spreading inside the substrate below the buried layer of each pixel during the shutter open mode. , A first voltage means for applying a first voltage to the gate electrode in each pixel, and a reverse voltage bias between the drain depletion region and the buried layer of each pixel A second voltage means for applying a second voltage to the drain depletion region between the pixels, the second voltage means for applying a second voltage from the input optical signal to the substrate in each pixel during the shutter opening mode. An electronic shutter in which given photoelectrons are accumulated in the enlarged depletion well region and the buried layer inhibits the photoelectrons from migrating to the drain depletion region. 3. In a shutter-closed mode, the first voltage means reduces the enlarged depletion well region to a substantially smaller reduced depletion well region above the buried layer at each pixel. A third voltage is applied to the gate electrode, and the second voltage means extends the drain depletion region to the inside of the substrate below the buried layer in each pixel, and the drain between the pixels is provided. A fourth voltage is applied to the depletion region, whereby photoelectrons imparted to the substrate in each pixel are attracted to the enlarged drain depletion region during the shutter closing mode, and the reduced depletion well. The electronic shutter according to claim 2, wherein movement to the area is prohibited. 4. A portion of the buried layer is at a first depth,
4. The electronic shutter according to claim 2, wherein the other portion of the buried layer is at a second depth below the depletion well region and the drain depletion region that is larger than the first depth. 5. A portion of the buried layer at the first depth is below the central region of the depletion well region, and another portion at the first depth is of the drain depletion region. The electronic shutter of claim 4, wherein a portion of the buried layer below and at the second depth is below a region between the central region and the drain depletion region. 6. The first voltage has a value of about 18V to about 25V, and the second voltage has a value of about 0V to about 6V.
The electronic shutter according to. 7. The electronic shutter of claim 3, wherein the third voltage has a value of about −6V to about 12V and the fourth voltage has a value of about 6V to about 18V. 8. The electronic shutter according to claim 2, wherein the substrate includes a p-type buried layer, the depletion well region includes an n-type depletion channel, and the drain depletion region is an n-type drain channel. . 9. The p-type buried layer has a logarithmic concentration of about 12.
atoms / cm ³ has an impurity concentration such that in the range of about 16atoms / cm ^3, the n-type buried layer, the range that log concentration of about 12atoms / cm ³ ~ about 16.5atoms / cm ³ Each of the n-type drain channels has a logarithmic concentration of about 12 atoms / cm ³ to about 20 atoms / c.
9. The electronic shutter according to claim 8, having an impurity concentration in the range of m ³ . 10. An electronic aperture for use in a charge coupled device having a pixel array formed in a semiconductor substrate, each of said pixels having a gate electrode on the surface of said substrate, A plurality of drain depletion regions formed respectively between adjacent pixels of the array; a buried layer formed below the depletion well region and its drain depletion region in each pixel; and below the buried layer of each pixel. First voltage means for applying a first voltage to the gate electrode in each pixel to create an enlarged depletion well region extending inside the substrate; and the substrate below the buried layer in each pixel. A second voltage means for applying a second voltage to the drain depletion region between the pixels in order to expand the drain depletion region. An electron controlled by the first voltage means or the second voltage means to adjust a portion of the photoelectrons applied to the substrate from the input optical signal and stored in the enlarged depletion well region in each pixel. Aperture. 11. The drain depletion region within the substrate for controlling the portion of photoelectrons provided to the substrate from the input optical signal and stored in the expanded depletion well region by the second voltage means. The aperture according to claim 10, wherein the aperture is controlled to adjust the degree of enlargement. 12. The depletion well region and the drain depletion region for controlling the portion of photoelectrons provided from the input optical signal and accumulated in the expanded depletion well region, by the first and second voltage means. 11. The diaphragm according to claim 10, wherein each of the diaphragms is controlled to adjust a degree of expansion inside the substrate.