JP3366480B2 - Semiconductor chip - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip adapted to relieve external stress applied to the peripheral portion of the semiconductor chip.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, some documents were described in the following documents. Reference: Japanese Patent Laid-Open No. 61-269333. A semiconductor chip is mounted on a lead frame, bonded, and then molded and sealed with a plastic such as a resin. At this time, the difference in thermal expansion between the plastic and the semiconductor chip is very large, and since the thermal expansion of the plastic is larger than that of the semiconductor chip, the surface of the semiconductor chip, especially the surface of the corner portion of the semiconductor chip, in the process of curing and shrinking of the plastic. A very large stress acts on the corners, and cracks are likely to occur at the corners, especially the stepped portions.
In addition, when cracks occur, water enters and metal wiring such as aluminum of the semiconductor chip causes a corrosion reaction, and in the case of two-layer aluminum wiring, there is a problem that aluminum shorts. As a countermeasure, there is one described in the above-mentioned document. In the above-mentioned document, a pattern of aluminum or the like having no electrical function is placed as a stress sharing member at a corner portion of a semiconductor chip, in a line outside an aluminum wiring that is actually electrically functioning, and the stress sharing member is formed. By sharing the stress, the effect of external stress is reduced.

[0003]

However, the conventional stress sharing member for a semiconductor chip has the following problems. The strength of the stress sharing member is not sufficient, and the stress sharing member cannot mechanically withstand the external stress sufficiently, and the stress sharing member slides, and the aluminum wiring slides following it, so that the other aluminum wiring aluminum corrosion due to the short and cracks disadvantageously possible.

[0004]

In order to solve the above problems, the present invention provides a semiconductor chip, a semiconductor substrate, and
A first interlayer insulating film formed on the semiconductor substrate;
Internal wiring formed on a first interlayer insulating film, and the first layer
Formed on the inter-layer insulating film and parallel to the outer periphery of the semiconductor substrate
And at predetermined intervals on the corners of the semiconductor substrate.
A plurality of placed first stress sharing members and the first stress sharing
On the first interlayer insulating film between the member and the internal wiring,
Formed parallel to and adjacent to the first stress sharing member.
And a plurality of second stress distributions that are arranged at a predetermined distance from each other
And a member. And between the first stress sharing members
Second gap portion between the first gap portion and the second stress sharing member
Means that from the outer periphery of the semiconductor substrate to the inner side of the semiconductor chip
They are arranged so that they are not on the same straight line
It

[0005]

According to the present invention, for example, external stress is usually
Occurs from the outer periphery of the conductor board toward the inside of the semiconductor chip
Therefore, when external stress is applied to the first stress sharing member,
Part of the stress is absorbed by the first stress sharing member, and the remaining stress
Is on a straight line from the first gap to the inside of the semiconductor chip
Transmitted along. The second gap is located on this straight line
Not, that is, the second stress sharing member is placed on this straight line.
Since it is placed, the stress from the first gap is equal to the second stress.
It is absorbed by the bearing member. As a result, the first and second
It is possible for the stress sharing members to share the external stress respectively.
It is possible and external stress is applied from the first gap to the internal wiring.
It is possible to suppress the extension.

[0006]

EXAMPLES (First Embodiment) FIG. 1 is a layout diagram of a semiconductor chip showing a first embodiment of the present invention. This semiconductor chip 1 is composed of a stress sharing member 2 for relieving external stress, a pad 3 used for wire bonding, and an internal wiring 4.
A plurality of stress sharing members 2 are arranged outside the internal wiring 4 of the semiconductor chip 1 and in a region close to the pad 3, and in particular,
It is arranged in an L-shape in the outer cornering portion of the internal wiring 4. The stress sharing members 2 have a rectangular shape, and the sides of the two stress sharing members 2 that are parallel to each side of the outer periphery of the semiconductor chip 1 and that are adjacent to each other in the inner direction of the semiconductor chip 1 are as straight as possible. For example, the stress sharing members 2 having different sizes are arranged so as not to be located on the line and are arranged in a staggered pattern.
It is arranged in steps. Innermost stress sharing member 2
The internal wiring 4 is arranged close to the inside of the semiconductor device, and the semiconductor element is arranged in the region inside the internal wiring 4.

FIGS. 2 (a) and 2 (b) are structural views of the stress sharing member 2 in FIG. 1 when a single-layer aluminum wiring is used as the metal wiring, and FIG. 2 (a) is a plan view and FIG. 3B is a sectional view. As shown in FIG. 2, the stress sharing member 2 and the semiconductor substrate 10, the impurity diffusion layer 11 is an impurity layer formed in the semiconductor substrate 10, the impurity diffusion layer 1
A field oxide film 12 formed on both sides of the 1, an interlayer insulating film 13 formed on the semiconductor substrate 10, the impurity diffusion layer 11 through the contact hole 14 is an opening formed in the interlayer insulating film 13 and <br/> metal 15 is a metal member connected, and a passivation film 16 serving as a dielectric film formed on the metal 15. A resin 18 is formed on the stress sharing member 2 to seal the semiconductor chip 1. Reference numeral 17 indicates the direction of external stress applied to the step of the stress sharing member 2 when the resin 18 is sealed.

Next, a method of manufacturing the stress sharing member 2 will be described with reference to MOS.
The case of the FET will be described as an example. LOC on the semiconductor substrate 10
Field oxide film 12 for element isolation by OS method or the like
And then a gate electrode is formed. Next, using the gate electrode as a mask, impurities having an attribute different from that of the semiconductor substrate 10 are ion-implanted into the semiconductor substrate 10 to form the impurity diffusion layer 11. At this time, at the same time
Source / drain region of the tape I blanking region is formed. Attributes of the semiconductor substrate 10 in the case of p-type phosphorous, or n-type impurity ions are implanted, such as arsenic, in the case of n-type ion implantation of p-type impurities such as boron. As a result, the bulk of the semiconductor substrate 10 and the impurity diffusion layer 11 of the stress sharing member 2 are pn
Are electrically insulated been joined, even if short-circuited with other semiconductor elements, it is possible to prevent a leakage current from flowing from the bulk of the semiconductor substrate 10, it does not affect the electrical operation.

Next, an interlayer insulating film 13 such as a silicon oxide film is formed.
Is formed on the entire surface, and a contact hole 14 is formed in the interlayer insulating film 13 on the impurity diffusion layer 11 by a lithography process. Then, aluminum or the like is deposited by sputtering, and the aluminum is patterned by lithography to form the metal 15. At this time, the pad 3 and the internal wiring 4 in FIG. 1 are simultaneously formed. Metal 15
Is connected to the impurity diffusion layer 11 through the contact hole 14. After that, the passivation film 16 as an insulating protection film is deposited on the entire surface, and the production of the stress sharing member 2 is completed. During the process of forming the semiconductor element in this way,
Since each element of the stress sharing member 2 is created, the stress sharing member 2 can be created without any additional process in manufacturing.

Next, the operation of the stress sharing member 2 will be described.
When the semiconductor chip 1 having such a structure is mounted on the lead frame, bonded, and then molded and sealed with the resin 18, the corner portion of the resin 18 and the passivation film 16 of the stress sharing member 2 adjacent to the pad 3 are formed. External stress acts on the surface of the step portion in the direction of arrow 17. Since the stress sharing member 2 is arranged at the location where the external stress is applied, the metal 15 of the stress sharing member 2 shares this external stress. The stress applied to the metal 15 is applied to the interlayer insulating film 13 and the impurity diffusion layer 11 . Impurity diffusion layer 1
Since 1 is formed in the semiconductor substrate 10, the stress applied to the impurity diffusion layer 11 can be sufficiently endured. As a result, the metal 15 can withstand external stress mechanically, so that there is no change in shape such as sliding, and the generation of cracks in the passivation film 16 can be suppressed. Furthermore, since the stress sharing members 2 are arranged in multiple stages and the external stress is shared by the plurality of stress sharing members 2, the occurrence of cracks can be further suppressed.

Next, the operation and effect of the zigzag arrangement of the stress sharing members 2 will be described. FIG. 3 (a),
(B) is a figure explaining an effect by arranging the stress sharing members 2 of this embodiment in a zigzag manner, and (a) of the same figure shows the stress sharing members on the same straight line in the inner direction of the semiconductor chip 1. This is a case where they are arranged side by side, and FIG. 9B shows a case where the stress sharing members are arranged in a staggered manner. As shown in FIG. 3A, when the stress sharing members are arranged on the same straight line in the inner direction of the semiconductor chip 1, the stress sharing members 2-1 adjacent to each other in the direction parallel to the outer periphery of the semiconductor chip 1 are arranged. And an insulating film 13-1 formed between the 2 and 2-2, and a stress sharing member 2-
The interlayer insulating film 13-2 formed between 3 and 2-4 is located on the same straight line, and the interlayer insulating films 13-1 and 13-2 are exposed to external stress as in the case of stacking blocks. Cracks are likely to occur along this straight line. On the other hand, as shown in FIG. 3B, when the stress sharing members are arranged in a staggered manner, the first stress sharing members 2-5 and 2-6 adjacent to each other in the direction parallel to the outer periphery of the semiconductor chip 1 are provided. First between
An interlayer insulating film 13-3 formed in the gap portion, an interlayer insulating film 13-4 formed on the second gap between the second stress sharing member 2-7 and 2-8, the second stress sharing Members 2-8 and 2-
Interlayer insulating film 13-5 formed in the second gap between
The term "corresponds to a joint portion when bricks are piled up" and is not located on the same straight line, so that cracks due to external stress can be further prevented.

As described above, the first embodiment has the following advantages. The stress sharing member 2 on the semiconductor substrate 10.
Since they are provided and arranged in zigzag in multiple stages, it is possible to suppress the occurrence of cracks and prevent corrosion of the internal wiring 4 due to the cracks. Thereby , the reliability of the semiconductor chip 1 can be further improved. Furthermore, it was mitigate the effects of external stress in the periphery of the semiconductor chip 1, since the corner portion of the semiconductor chip 1 can be placed while maintaining the reliability of the wiring and the semiconductor element, efficient semiconductor chip 1 Various designs are possible. Further, since the disposed L-shaped stress sharing member 2 in cornering portion facilitates pattern design.

( Second Embodiment ) FIGS. 4 (a) and 4 (b) are structural views of a stress sharing member of a semiconductor chip according to a second embodiment of the present invention, showing the stress in the case of two-layer metal wiring. It is a sharing member, the figure (a) is a top view and the figure (b) is a sectional view. This stress sharing member is arranged at the same position as in the first embodiment shown in FIG.
As shown in FIG. 4B, the stress sharing member is the semiconductor substrate 20 and the impurity layer formed in the semiconductor substrate 20.
That the impurity diffusion layer 21, a field oxide film 22 formed on both sides of the impurity diffusion layer 21, a first interlayer insulating film 23 of the first layer formed on the semiconductor substrate 20, the first interlayer insulating film the first layer being connected to the impurity diffusion layer 21 through the contact hole 24 is an opening formed in the 23 second
A first metal 25 , which is a first metal member, and a second-layer second interlayer insulating film 26 formed on the first metal 25.
And the through hole 2 opened in the second interlayer insulating film 26.
Second second layer which is connected to the first metal 25 via the 7
A second metal 28 is a metal member, and a passivation film 29 serving as a dielectric film formed on the second metal 28. A resin 30 is formed on the passivation film 29 to seal the semiconductor chip. Reference numeral 31 indicates the direction of external stress applied to the step of the passivation film 29 of the stress sharing member when the resin 30 is sealed.

Next, a method of manufacturing the stress sharing member according to the second embodiment will be described by taking the case of MOSFET as an example. A field oxide film 22 for element isolation is formed on the semiconductor substrate 20 by the LOCOS method or the like, and then a gate electrode is formed. Next, the semiconductor substrate 20 using the gate electrode as a mask
Within, the ion implanted impurities of a different attribute from the semiconductor substrate 20 to form an impurity diffusion layer 21. At this time, the source / drain regions of the Make Active regions of a semiconductor device is simultaneously formed. If the semiconductor substrate 20 is of p-type phosphorous, or n-type impurity ions are implanted, such as arsenic, in the case of n-type ion implantation of p-type impurities such as boron.

Next, a first interlayer insulating film 23 is formed on the entire surface, and the impurity diffusion layer 2 is formed by a lithography process.
A contact hole 24 is formed in the first interlayer insulating film 23 on the first layer. Then, aluminum or the like is deposited by sputtering, and the aluminum is patterned by a lithography process to form the first metal 25 of the first layer. As a result, the first metal 25 is connected to the impurity diffusion layer 21 via the contact hole 24. afterwards,
The second interlayer insulating film 26 of the second layer is formed on the first metal 25, and the second interlayer insulating film 2 is formed by a lithography process.
A through hole 27 is opened at 6. Then, aluminum or the like is deposited by sputtering, and the aluminum is patterned by lithography to form the second metal 28 of the second layer. As a result, the second metal 28 of the second layer passes through the through hole 27 and the metal 25 of the first layer
Connected to. Next, a passivation film 29 as an insulating protection film is deposited on the entire surface, and the production of the stress sharing member is completed. As described above, in the case of the two-layer metal wiring, since the respective elements of the stress sharing member are sequentially created during the process of forming the semiconductor element, the stress sharing member is created without newly adding a manufacturing step. be able to.

Next, the operation of this stress sharing member will be described. When the semiconductor chip having such a structure is mounted on the lead frame, bonded, and then molded and sealed with the resin 30, the corner portion of the resin 30 and the stepped portion of the passivation film 29 of the stress sharing member near the pad are formed. External stress acts on the surface in the direction of arrow 31. Since the stress sharing member is arranged at the location where the external stress is applied, the second metal 28 of the third stress sharing member shares the external stress. The stress applied to the second metal 28 is applied to the second interlayer insulating film 26 of the second layer and the first metal 25 of the first layer. The stress applied to the first metal 25 is 1
The first interlayer insulating film 23 and the impurity diffusion layer 21 of the layer are to be covered. Since the impurity diffusion layer 21 is formed in the semiconductor substrate 20, the stress applied to the impurity diffusion layer 21 can be sufficiently endured. As a result, since the second metal 28 can mechanically withstand external stress, there is no change in shape such as sliding, it is possible to suppress the generation of cracks in the passivation film 29, and slide the metal wiring. It is possible to prevent the metal wiring from being short-circuited.

As described above, the second embodiment has the following advantages. The second metal 28 constituting the third stress sharing member is connected to the first metal 2 via the through hole 27.
5 and connect the first metal 25 to the contact hole 24
Since it is connected to the semiconductor substrate 20 via the third stress sharing member, external stress can be mitigated even in the two-layer metal process, and the occurrence of cracks is suppressed to prevent corrosion of the internal wiring 4 due to the cracks. In addition, it is possible to prevent the short circuit of the metal wiring due to the sliding of the second metal 28. The present invention is not limited to the above embodiment, and various modifications can be made. The following are examples of such modifications. (1) When the impurity diffusion layers 11 and 21 are CMOS, by introducing the same impurity as the semiconductor substrates 10 and 20 into the well into which the impurities different from the semiconductor substrates 10 and 20 are introduced, the stress sharing member and the semiconductor substrate It can be insulated from 10, 20 bulks. (2) Even when manufacturing a bipolar transistor, the stress sharing member according to the present invention can be prepared.

[0018]

As described above in detail, the present invention
According to the invention of claim 1, the plurality of first stress sharings
A member and a plurality of second stress sharing members,
A first gap between the bearing members and a second gap between the second stress sharing members
The gap is defined from the outer periphery of the semiconductor substrate to the inner side of the semiconductor chip.
Since it was placed so that it would not be on the same straight line,
For example, in the vertical direction with the outer periphery of the semiconductor substrate,
Even if a large stress is applied, this stress is
Material and the second stress sharing member share the effect of stress
It can be mitigated. As a result, even the internal wiring is
Partial stress is applied and cracks occur in the interlayer insulating film, causing wiring corrosion.
Can reduce the chance of eating, or
It is possible to prevent a short circuit of the wiring. Claim 2
According to the invention, in the semiconductor chip according to claim 1,
Partial wiring, first and second stress sharing members, and on the first interlayer insulating film
A second interlayer insulating film having an opening is formed on the
The first or the second stress component is formed on the interlayer insulating film.
The bearing member is connected through the opening of the second interlayer insulating film.
A third stress sharing member is formed. Further claims
According to the invention of claim 3, the semiconductor chip according to claim 1
Internal wiring, the first and second stress sharing members, and the first insulation layer.
A second interlayer insulating film having a plurality of openings is formed on the edge film
Is formed on the second interlayer insulating film, and
A plurality of openings in the second stress sharing member and the second interlayer insulating film
A third stress sharing member connected via the
It Therefore, also in the inventions according to claims 2 and 3,
There is almost the same effect as the invention according to claim 1. Claim 4
According to the invention of claim 1, any one of claims 1 to 3
In the conductor chip, the first interlayer insulating film has an opening,
The first or second stress sharing member is the first interlayer insulation
Since it is connected to the semiconductor substrate through the opening of the film,
That is, the first or second stress sharing member is
Since it is connected to a strong semiconductor substrate,
It is possible to further increase the strength against stress. Claim
According to the invention of claim 5, any one of claims 1 to 3
In the semiconductor chip of, the first interlayer insulating film has an opening.
However, the first or second stress sharing member is the first interlayer
Connected to the semiconductor substrate through the opening of the insulating film,
1 In the semiconductor substrate exposed by the opening of the interlayer insulating film
Forms an impurity layer of the opposite conductivity type to the semiconductor substrate.
The first or second stress sharing member is
Since it is connected to the pure material layer, it is almost the same as in claims 1 and 4.
There is a similar effect.

[Brief description of drawings]

FIG. 1 is a layout diagram of a semiconductor chip according to a first embodiment of the present invention.

FIG. 2 is a structural diagram of a stress sharing member in FIG.

FIG. 3 is a diagram for explaining the effect of the zigzag arrangement of the stress sharing members of this embodiment.

FIG. 4 is a structure showing a stress sharing member according to a second embodiment of the present invention.
It is a drawing.

[Explanation of symbols]

10, 20 Semiconductor substrate 11, 21 Impurity diffusion layer 12, 22 Field oxide film 13 Interlayer insulating film 14, 24 Contact hole 15 Metal 16 Passivation film 18 Resin 23 First interlayer insulating film 25 First metal 26 Second interlayer Insulation film 27 Through hole 28 Second metal 29 Passivation film 30 Resin

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/321 H01L 21/3213 H01L 21/768

Claims (5)

(57) [Claims] And 1. A semiconductor substrate, wherein the first interlayer insulating film formed on a semiconductor substrate, the internal wiring formed on the first interlayer insulating film, is formed on the first interlayer insulating film, Outside the semiconductor substrate
Parallel to the circumference and at a predetermined corner of the semiconductor substrate
A plurality of first stress sharing members arranged at intervals, and the first between the first stress sharing member and the internal wiring
On the interlayer insulating film, parallel to the first stress sharing member, and
Plural pieces that are formed adjacent to each other and are arranged at predetermined intervals.
And a second gap between the first stress- bearing members, and the second stress
The second gap between the sharing members is the outer periphery of the semiconductor substrate.
Should not be located on the same straight line from the
A semiconductor chip characterized by the fact that 2. The internal wiring and the first and second stress components
A second member having an opening on the bearing member and the first interlayer insulating film.
An interlayer insulating film is formed , and the first or second interlayer insulating film is formed on the second interlayer insulating film.
Contact with the stress sharing member through the opening of the second interlayer insulating film.
A continuous third stress sharing member is formed.
The semiconductor chip according to claim 1, further comprising: 3. The internal wiring and the first and second stress components
A plurality of openings are formed on the bearing member and the first interlayer insulating film.
A second interlayer insulating film is formed , and the first or second interlayer insulating film is formed on the second interlayer insulating film.
Through the stress sharing member and the plurality of openings of the second interlayer insulating film.
The third stress sharing member connected by
The semiconductor chip according to claim 1, which is a characteristic. 4. The first interlayer insulating film has an opening, and the first or second stress sharing member is the first stress sharing member.
Connected to the semiconductor substrate through the opening of the interlayer insulating film
The method according to any one of claims 1 to 3, characterized in that
Semiconductor chip. 5. The first interlayer insulating film has an opening, and the first or second stress sharing member is the first
Connected to the semiconductor substrate through the opening of the interlayer insulating film.
And the semiconductor exposed through the opening of the first interlayer insulating film.
An impurity layer of the opposite conductivity type to the semiconductor substrate is formed on the substrate.
And the first or second stress sharing member is
It connects with the said impurity layer, The 1-3 characterized by the above-mentioned.
The semiconductor chip according to any one of 1.