JP3429715B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of elements formed on a semiconductor substrate at intervals and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit device, in order to secure the degree of integration as much as possible, a contact hole of an electrode wiring is brought close to an element isolation region such as a selective oxide film (LOCOS film) for electrically isolating elements. (Contact hole) is arranged. FIG. 4 shows a manufacturing process of a conventional semiconductor device.

As shown in FIG. 4A, on the semiconductor substrate 1 into which P-type impurities have been introduced, the minimum dimension 3 required for element isolation (hereinafter, "minimum dimension required for element isolation" is referred to as "minimum dimension"). The element isolation region 2 made of an insulating material such as a LOCOS film is formed while ensuring the "minimum element isolation dimension". The layer below the element isolation region 2 is a channel stop layer 13
Is.

A semiconductor substrate 1 on which an element isolation region 2 is formed
N-type impurities are introduced by ion implantation to form N-type impurity introduction layers 4 on both sides of the element isolation region 2.
Next, the interlayer insulating film 7 is formed so as to cover the entire surface of the semiconductor substrate 1.
Then, as shown in FIG. 4B, a contact hole 6 is formed in the interlayer insulating film 7 located above the N-type impurity introduction layer 4 by etching.

Finally, as shown in FIG. 4C, the contact plug 6 is filled with the connection plug 8 and the interlayer insulating film 7 is formed.
A wiring 9 mainly composed of an Al alloy film is formed on the top surface of the wiring 9 to obtain conduction between the wiring 9 and the N-type impurity introduction layer 4. In the semiconductor device configured as described above, it is preferable that the element isolation region 2 and the contact hole 6 be as close to each other as possible in order to secure the degree of integration between semiconductor elements as much as possible.

[0006]

However, if the contact hole 6 is formed too close to the element isolation region 2, the contact hole 6 is separated due to misalignment in the photolithography process or change in the opening dimension due to dry etching. In some cases, the N-type impurity layer 4 and the channel stop layer 13 are exposed at the bottom of the opening of the contact hole 6 at the same time as overlapping with the region 2 and a short circuit is caused by the connection plug 8.

Therefore, in the step of FIG. 4B, the distance d3 between the adjacent contact holes 6 is larger than the width d4 of the element isolation region 2 and is operated in advance on both sides of the minimum element isolation dimension 3. It is necessary to secure the distance by adding the obtained maximum amount of positional deviation [machining margin] (hereinafter, the “maximum amount of positional deviation obtained by operating in advance” is referred to as the “maximum amount of positional deviation”) 5. Is a constraint when designing a circuit with high density.

An object of the present invention is to solve the above problems and to provide a semiconductor device in which a contact hole is brought close to an element isolation region and the degree of integration of a semiconductor element can be secured, and a manufacturing method thereof.

[0009]

The semiconductor device of the present invention comprises:
It is characterized in that the width of the element isolation region and the distance between contact holes adjacent to each other with the element isolation region interposed therebetween are substantially equal. According to the present invention, it is possible to minimize the distance between the contact holes that are adjacent to each other with the element isolation region interposed therebetween, so that a semiconductor device with a higher density can be realized.

According to the method of manufacturing a semiconductor device of the present invention, the element isolation region is formed so that the width of the element isolation region is substantially equal to the sum of the minimum dimension of the element isolation and the maximum amount of displacement of the contact hole. Characterize. According to the present invention, the semiconductor device of the present invention can be easily realized.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to claim 1 of the present invention is a semiconductor device in which a plurality of elements are formed on a semiconductor substrate at intervals, and an impurity introduction layer on the semiconductor substrate side of the element. A wiring layer formed on the impurity introduction layer via an interlayer insulating film is connected to the contact hole formed in the interlayer insulating film by filling a connection plug, and the connection hole is formed between the contact holes of the adjacent elements. An element isolation region in which impurities are introduced is formed between the interlayer insulating film and the semiconductor substrate, and the width of the element isolation region is set to the maximum amount of positional deviation when processing the contact hole into the interlayer insulating film and the element. Is approximately equal to the minimum dimension required for electrical isolation, and the distance between adjacent contact holes is approximately equal to the width of the element isolation region. .

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein when manufacturing a semiconductor device in which a plurality of elements are formed on a semiconductor substrate at intervals, an element made of an insulating material is formed on the semiconductor substrate. Forming an isolation region, forming an impurity introduction layer on the semiconductor substrate other than the element isolation region, forming an insulating film on at least the impurity introduction layer, and forming an interlayer insulating film on the interlayer insulation film. A step of forming a contact hole with the element isolation region sandwiched therebetween, the width of the element isolation region is set to a maximum amount of misalignment when processing the contact hole into the interlayer insulating film and electrical isolation of the element. It is characterized in that it is made substantially equal to the required minimum size and the distance between adjacent contact holes is made substantially equal to the width of the element isolation region.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, impurities having the same conductivity type as the impurity introduction layer are introduced into the semiconductor substrate through a contact hole formed in the interlayer insulating film. Is characterized by. Hereinafter, a semiconductor device and a method for manufacturing the same according to the present invention will be described based on specific embodiments.

Components similar to those in FIG. 4 showing the above-mentioned conventional example will be described with the same reference numerals. The semiconductor device of the present invention is manufactured through the steps of FIGS. In the step of FIG. 1A, the element isolation region 2 made of an insulating material such as a LOCOS film is formed on the semiconductor substrate 1 into which the P-type impurity has been introduced.

The width d1 of the element isolation region 2 must be equal to the sum of the minimum element isolation dimension 3 and the maximum positional deviation amount 5. A channel stop layer 13 in which a P-type impurity having a concentration higher than that of the semiconductor substrate 1 is introduced is formed below the element isolation region 2. N-type impurities are introduced into the semiconductor substrate 1 in which the element isolation regions 2 are formed by an ion implantation method, and N-type impurities are formed on both sides of the element isolation regions 2.
The type impurity introduction layer 4 is formed.

Next, an interlayer insulating film 7 is formed so as to cover at least the N-type impurity introduction layer 4, and as shown in FIG. The contact hole 6 for electrically connecting to the type impurity introduction layer 4 is etched. The distance d2 between the contact holes 6 that are adjacent to each other with the element isolation region 2 interposed therebetween is designed to be substantially equal to or extremely close to the width d1 of the element isolation region 2.

Therefore, the distance d2 between the adjacent contact holes 6 is substantially equal to the sum of the minimum dimension 3 of element isolation and the maximum amount of positional deviation 5. In addition, when a pattern of the contact hole 6 is formed, a mask shift or the like occurs,
When a region where the contact hole 6 overlaps with the element isolation region 2 occurs, as shown in FIG. 1C, the P-type channel stop layer exposed together with the N-type impurity introduction layer 4 after the contact hole 6 is etched. It is preferable to introduce the N-type impurity 10 into 13 by an ion implantation method to change the P-type layer of the channel stop layer 13 into the N-type impurity introduced layer 11.

Finally, as shown in FIG. 1D, the contact hole 6 has a connection plug 8 made of tungsten or the like.
Are filled in and the wiring 9 containing Al alloy as a main component is formed on the interlayer insulating film 7 to obtain electrical continuity between the wiring 9 and the N-type impurity introduction layer 4. Distance d2 between adjacent contact holes 6
Is almost equal to the width d1 of the element isolation region 2, and its size is the sum of the minimum element isolation dimension 3 and the maximum positional displacement amount 5.

On the other hand, the distance d3 between the contact holes 6 shown in FIG. 4 showing the above-mentioned conventional example is the sum of the minimum dimension 3 of element isolation and the maximum amount 5 of positional deviation. Therefore, according to the present invention, the distance d2 between the adjacent contact holes 6 can be narrowed by a value corresponding to the maximum positional deviation amount 5 as compared with the conventional case.
The circuit can be designed by further increasing the density of the semiconductor device.

FIG. 2 shows a plane layout of the semiconductor device of the present invention, and the sectional view taken along the line AB is shown in FIG.
Indicates. Even when the mask shift amount of the contact holes 6 arranged to face each other in the width direction of the element isolation region 2 becomes the maximum amount 5, the distance between the facing contact holes 6 can ensure the minimum dimension 3 of element isolation.

Further, on the line AB, there is a wiring 9 across the element isolation region 2 in order to establish conduction with the N-type impurity introduction layer 4 of the semiconductor substrate 1 through the contact hole 6. When a voltage is applied to the wiring 9, an inversion layer is formed on the semiconductor substrate 1 below the element isolation region 2. That is, when a potential difference is applied to the N-type impurity introduction layer 4 provided with the contact hole 6, current leakage tends to increase.

However, in an ordinary semiconductor integrated circuit, since the interlayer insulating film 7 of about 1 μm or more exists from the surface of the semiconductor substrate 1 to the wiring 9, application of a voltage of several V has almost no effect on the element isolation characteristics. it is conceivable that. Figure 3
Shows a sectional view taken along the line C-D. A gate electrode / wiring 12 that intersects the element isolation region 2 is formed on the element isolation region 2. When a voltage is applied to the gate electrode / wiring 12, the semiconductor substrate 1 below the element isolation region 2 is inverted. It is greatly affected by the formation of layers.

Since the active region 14 of the MOS transistor without the N-type impurity introduction layer 4 is formed on the element isolation region 2, in principle, no potential difference can be made between the two sides of the element isolation region 2. However, the gate electrode / wiring 12
Of the N-type impurity introduction layer 4 to the end of the element isolation region 2
When a potential difference is applied to the N-type impurity introduction layers 4 on both sides of the same, a part of the depletion layer of the semiconductor substrate 1 also wraps under the isolation region under the gate electrode / wiring 12 to promote leakage. there is a possibility.

The minimum dimension 3 required for electrically separating the elements is determined in consideration of such a planar layout.

[0025]

As described above, according to the semiconductor device of the present invention, in a semiconductor device in which a plurality of elements are formed on a semiconductor substrate at intervals, the impurity introduction layer on the semiconductor substrate side of the element and the impurity A wiring layer formed on the introduction layer via an interlayer insulating film is connected by filling a contact plug formed in the contact hole formed in the interlayer insulating film, and between the contact holes of the adjacent elements. An element isolation region having impurities introduced therein is formed between the interlayer insulating film and the semiconductor substrate, and the width of the element isolation region is set to the maximum amount of misalignment when the contact hole is processed into the interlayer insulating film and the electrical conductivity of the element. The distance between adjacent contact holes should be approximately equal to the sum of the minimum dimensions required for dynamic separation.
By configuring the width to be substantially equal to the width of the element isolation region, while securing a necessary dimension for element isolation,
The distance between the contact holes between the element isolation regions can be minimized.

According to the method of manufacturing a semiconductor device of the present invention,
When manufacturing a semiconductor device in which a plurality of elements are formed on a semiconductor substrate at intervals, a step of forming an element isolation region made of an insulating material on the semiconductor substrate, and a step of forming the element isolation region other than the element isolation region And a step of forming an insulating film on at least the impurity introducing layer, and a step of forming a contact hole with the element isolation region sandwiched in the interlayer insulating film, The width of the element isolation region is substantially equal to the sum of the maximum amount of positional deviation when processing the contact hole into the interlayer insulating film and the minimum dimension required for electrical isolation of the element, and the distance between adjacent contact holes. The semiconductor device of the present invention can be easily realized by forming the device so as to have a width substantially equal to the width of the element isolation region.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a C- of the semiconductor device according to the embodiment of the present invention.
Sectional view along line D

FIG. 4 is a diagram showing a conventional semiconductor device manufacturing process.

[Explanation of symbols]

1 Semiconductor substrate 2 element isolation region Minimum element separation size 4 N-type impurity introduction layer 5 Maximum displacement 6 contact holes 10 N-type impurities 11 N-type impurity introduction layer

Claims (3)

(57) [Claims] 1. A semiconductor device in which a plurality of elements are formed on a semiconductor substrate at intervals, and an impurity introduction layer on the semiconductor substrate side of the element and an interlayer insulation film formed on the impurity introduction layer. The contact layer formed in the interlayer insulating film is connected to the formed wiring layer by connecting plugs, and an impurity is interposed between the interlayer insulating film and the semiconductor substrate between the contact holes of the adjacent elements. The introduced element isolation region is formed, and the width of the element isolation region is almost equal to the sum of the maximum amount of positional deviation when processing the contact hole in the interlayer insulating film and the minimum dimension required for electrical isolation of the element. A semiconductor device in which the distances between adjacent contact holes are made substantially equal to the width of the element isolation region. 2. When manufacturing a semiconductor device in which a plurality of elements are formed on a semiconductor substrate at intervals, a step of forming an element isolation region made of an insulating material on the semiconductor substrate, other than the element isolation region. Forming an impurity introduction layer on the semiconductor substrate, forming an insulating film on at least the impurity introduction layer, and forming a contact hole in the interlayer insulating film with the element isolation region sandwiched therebetween. And the width of the element isolation region is made substantially equal to the sum of the maximum amount of positional deviation when processing the contact hole into the interlayer insulating film and the minimum dimension required for electrical isolation of the element, and A method of manufacturing a semiconductor device, wherein the distance of the contact hole is formed to be substantially equal to the width of the element isolation region. 3. The method of manufacturing a semiconductor device according to claim 2, wherein impurities having the same conductivity type as the impurity introduction layer are introduced into the semiconductor substrate through a contact hole formed in the interlayer insulating film.