JP3365480B2 - Test circuit and test method for semiconductor integrated circuit and semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit test circuit and method for performing an operation test of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art As a method for testing a semiconductor integrated circuit such as an LSI, a test pattern is input to an LSI, which is a device under test, from an LSI tester, and output data output from the LSI and expected values prepared in advance are used. Is generally compared to determine whether or not the LSI is operating normally. Therefore, the operating frequency of the LSI tester must be higher than or at least equal to the operating frequency of the LSI, which is the device under test.

However, since a general LSI tester does not have a high operating frequency, it may not be possible to test an LSI developed in recent years with a high operating frequency. In particular, this becomes a problem when performing the maximum speed test of the LSI.

In order to solve such a problem, for example, in Japanese Patent Laid-Open No. 8-62297, n-phase clock signals that do not temporally overlap with each other are synthesized to generate a high-frequency single-phase clock signal. A test circuit for testing a semiconductor integrated circuit is described.

A conventional method for testing a semiconductor integrated circuit will be described with reference to FIG.

In this semiconductor integrated circuit testing method, the operation of the signal processing circuit 2 provided in the digital signal processing LSI 51 is confirmed using the LSI tester device 3.

Here, the test circuit of the semiconductor integrated circuit means a circuit provided inside the digital signal processing LSI 51 for performing an operation test of the signal processing circuit 2.
Flip-flop circuits 4 and 5 are shown in FIG.

Here, the normal LSI has a plurality of inputs, but here, in order to simplify the explanation, it is assumed that the digital signal processing LSI 51 has only one input.

The LSI tester device 3 includes an LSI tester 10
, A pattern generation circuit 8, switch circuits 6 and 7, and an OR circuit 9.

The LSI tester 10 outputs clock signals C ₁ and C ₂ having different phases, and test pattern data P ₁ synchronized with the clock signal C ₁ and test pattern data P ₂ synchronized with the clock signal C _2. Is output. Then, the expected value obtained from the output test pattern data P ₁ and P ₂ is compared with the device output data 13 output from the digital signal processing LSI 51 to confirm the operation of the digital signal processing LSI 51. Also, L
In the SI tester 10, the operating frequency of the signal processing circuit 2 is LS.
When performing a normal test that is lower than the maximum operating frequency of the I tester 10, the test mode control signal 14 is made inactive, and the operating frequency of the signal processing circuit 2 is higher than the maximum operating frequency of the LSI tester as in the maximum speed test. The test mode control signal 14 is activated when a certain test is performed.

The logical sum circuit 9 calculates the logical sum of the clock signals C ₁ and C ₂ and outputs the calculation result.

The switch circuit 7 outputs the output signal of the OR circuit 9 as the test clock signal 12 when the test mode control signal 14 is active, and outputs the clock signal C ₁ when the test mode control signal 14 is inactive. It is output as the test clock signal 12.

The pattern generation circuit 8 performs a logical operation between the test pattern data P ₁ and the test pattern data P ₂ and outputs a signal whose cycle is half. Here, in order to simplify the description, a case where an exclusive OR is used as a certain logical operation will be described.

The switch circuit 6 outputs the output signal of the pattern generating circuit 8 as the test pattern data 11 when the test mode control signal 14 is active, and the test pattern data P ₁ when the test mode control signal 14 is inactive. Is output as the test pattern data 11.

The digital signal processing LSI 51 has a signal processing circuit 2 and flip-flop circuits 4 and 5.

The signal processing circuit 2 is a circuit for performing a certain calculation or processing on an input signal and outputting it.

The flip-flop circuit 4 operates by using the test clock signal 12 as a clock, holds the test pattern data 11 once, and then inputs it to the signal processing circuit 2.

The flip-flop circuit 5 operates by using the test clock signal 12 as a clock, temporarily holds the output signal from the signal processing circuit 2, and then outputs it as the device output data 13.

Next, the operation of the test circuit of the conventional semiconductor integrated circuit will be described with reference to FIG.

First, a case where a test is performed in which the operating frequency of the signal processing circuit 2 to be tested is within the maximum operating frequency of the LSI tester 10 will be described.

In this case, the LSI tester 10 makes the test mode control signal 14 inactive. for that reason,
The clock signal C ₁ is output from the switch circuit 7 as the test clock signal 12. Further, the test pattern data P ₁ is transferred from the switch circuit 6 to the test pattern data 11
Is output as.

Therefore, the signal processing circuit 2 is subjected to an operation test at the operation frequency of the LSI tester 10.

Next, a case where a test is performed in which the operating frequency of the signal processing circuit 2 to be tested is higher than the maximum operating frequency of the LSI tester 10 will be described.

In this case, the LSI tester 10 activates the test mode control signal 14. Therefore, the output signal from the OR circuit 9 is output from the switch circuit 7 as the test clock signal 12. Since the test clock signal 12 is the operation result of the logical sum operation of the clock signals C ₁ and C _{2 having} different phases, the clock frequency is doubled. Further, since the test mode control signal 14 is active, the output signal from the pattern generation circuit 8 is output from the switch circuit 6 as the test pattern data 11. The test pattern data 11 is a signal whose period is halved because it is the calculation result of the test pattern data P ₁ and P _{2 having} different phases.

Therefore, the signal processing circuit 2 is subjected to an operation test at an operating frequency twice that of the LSI tester 10. However, the flip-flop circuit 5
Since the device output data 13 output from is a signal having a frequency twice the operating frequency of the LSI tester 10, the LSI tester 10 cannot read the data content as it is. Therefore, the LSI tester 10
Repeats the same test twice, changes the read timing for each test, and changes the device output data 13
Must be taken in a way that reads.

However, when the test circuit of the conventional semiconductor integrated circuit is used, there is a problem that the same test must be performed twice and the time required for the test becomes long. In addition, the operating frequency of the device under test increases and
When using four-phase and four-phase signals, a test time of 3 times and 4 times is required.

[0027]

The conventional test circuit for a semiconductor integrated circuit described above has a problem that the test time becomes long when a test is performed in which the operating frequency is higher than the maximum operating frequency of the LSI tester. It was

An object of the present invention is to provide a test circuit for a semiconductor integrated circuit capable of testing a semiconductor integrated circuit whose operating frequency is higher than the maximum operating frequency of an LSI tester without increasing the test time. .

[0029]

In order to achieve the above object, a test circuit for a semiconductor integrated circuit according to the present invention inputs test pattern data to the semiconductor integrated circuit and outputs output data from the semiconductor integrated circuit. In a test circuit of a semiconductor integrated circuit for performing an operation test of the semiconductor integrated circuit by comparing with an expected value prepared in advance, the output data output from the semiconductor integrated circuit is continuously output.
Data that are positioned before and after the data
By calculation to, and having a data compression circuit for outputting compressed into a smaller number of data than the number of data of the output data.

According to the present invention, the output data of the frequency higher than the maximum operating frequency of the LSI tester output from the semiconductor integrated circuit is compressed by the data compression circuit to lower the frequency and then output.

Therefore, a semiconductor integrated circuit whose operating frequency is equal to or higher than the maximum operating frequency of the LSI tester can be tested by a test circuit of a semiconductor integrated circuit having a low operating frequency without increasing the test time.

According to the embodiment of the present invention, the data compression circuit divides the test clock signal, which is used as a reference for the operation of the semiconductor integrated circuit, by a constant dividing value and outputs the divided clock signal. A frequency divider circuit, a flip-flop circuit that operates using the divided clock signal as a clock, and temporarily holds the output data and then outputs the output data;
And a logic circuit that performs a logical operation between the output data and the output from the flip-flop circuit.

According to the present invention, the output data output from the semiconductor integrated circuit is temporarily held by the flip-flop circuit,
The value held by the flip-flop and the next output data are calculated by a logic circuit and output.

Therefore, since the output data output from the semiconductor integrated circuit is two data that are temporally located before and after the output data as one data, a test circuit operating at an operating frequency half the frequency of the output data. The operation test can be performed by.

According to another embodiment of the present invention, the logic circuit is an exclusive OR circuit.

Further, according to another embodiment of the present invention, the data compression circuit operates by using the test clock signal as a clock to temporarily hold the output data and then output the first flip-flop. Circuit, a second flip-flop circuit that operates using the test clock signal as a clock, and temporarily holds and outputs the output signal from the first flip-flop circuit, the output data and the first flip-flop circuit. A logical operation is performed on the output signal from the flip-flop circuit and a logical operation is performed on the output data and the output signal from the second flip-flop circuit. A second logical circuit that outputs the result, performs a logical operation of the output signal from the first logical circuit and the output signal from the second logical circuit, and performs the operation. Composed of the third logic circuit for outputting the result.

According to an embodiment of the present invention, the first logic circuit, the second logic circuit and the third logic circuit are exclusive OR circuits.

According to another embodiment of the present invention, the data compression circuit divides the test clock signal, which is used as a reference for the operation of the semiconductor integrated circuit, by a constant division value to divide the divided clock signal. And a plurality of flip-flop circuits that operate using the divided clock signal as a clock to temporarily hold the plurality of output data, and then output the plurality of output data. And a full adder for adding the output data from the flip-flop circuit and outputting the operation result.

[0039]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 is a diagram for explaining a test method for a semiconductor integrated circuit according to a first embodiment of the present invention. The same numbers as in FIG. 5 indicate the same components.

In the semiconductor integrated circuit testing method of this embodiment, the operation of the signal processing circuit 2 provided in the digital signal processing LSI 1 is confirmed by using the LSI test apparatus 3.

The digital signal processing LSI 1 has a data compression circuit 15 in addition to the digital signal processing LSI 51 shown in FIG.

Here, the test circuit of the semiconductor integrated circuit refers to a circuit provided inside the digital signal processing LSI 1 for performing an operation test of the signal processing circuit 2. In FIG. 1, the flip-flop circuits 4 and 5 are shown. And the data compression circuit 15.

The data compression circuit 15 includes a frequency dividing circuit 20 and
It is composed of a flip-flop circuit 21, a logic circuit 22, and a switch circuit 23.

The frequency divider circuit 20 includes a test clock signal 12
Is divided by 2 and output as a 1/2 divided clock signal 24.

The flip-flop circuit 21 operates by using the 1/2 divided clock signal 24 as a clock, temporarily holds the output data D ₁ output from the flip-flop circuit 5, and then outputs it as the output data D _2. To do.

The logic circuit 22 performs a logical operation between the output data D ₁ and the output data D ₂ and outputs it as the output data D ₃ .

In the present embodiment, the case where an exclusive OR is used for this logical operation will be described for simplification of description, but the present invention is not limited to this, and a logical operation having another logic. May be used.

The switch circuit 23 outputs the output data D ₁ as the device output data 13 when the test mode control signal 14 is inactive, and outputs the output data D ₃ as the device output data when the test mode control signal 14 is active. Output as 13.

Next, the operation of this embodiment will be described with reference to FIGS.

First, a case where a normal test is performed in which the operating frequency of the signal processing circuit 2 to be tested is within the maximum operating frequency of the LSI tester 10 will be described.

In this case, the LSI tester 10 makes the test mode control signal 14 inactive. Therefore, the clock signal C ₁ is output from the switch circuit 7 as the test clock signal 12. Further, the test pattern data P ₁ is output from the switch circuit 6 as the test pattern data 11. The output signal from the signal processing circuit 2, which is the test result, is input to the data compression circuit 15 as output data D ₁ via the flip-flop circuit 5. Since the test mode control signal 14 is inactive, the output data D ₁ is output from the switch circuit 23 as the device output data 13.

As a result, the signal processing circuit 2 is tested up to the maximum operating frequency of the LSI tester 10 as described above. The operation up to this point is the same as the operation of the test circuit of the conventional semiconductor integrated circuit.

Next, a case where a test is performed in which the operating frequency of the signal processing circuit 2 to be tested is higher than the maximum operating frequency of the LSI tester 10 will be described.

In this case, the LSI tester 10 activates the test mode control signal 14. Therefore, the output signal from the OR circuit 9 is output from the switch circuit 7 as the test clock signal 12. Since the test clock signal 12 is the operation result of the OR operation of the clock signals C ₁ and C _{2 having} different phases, the clock frequency is LSI.
It is twice the operating frequency of the tester 10. Further, since the test mode control signal 14 is active, the output signal from the pattern generation circuit 8 is output from the switch circuit 6 as the test pattern data 11. The test pattern data 11 is a signal whose period is halved because it is the calculation result of the test pattern data P ₁ and P _{2 having} different phases. The state of these signals is shown in the timing chart of FIG.

As a result, the signal processing circuit 2
Is subjected to an operation test at an operating frequency twice the frequency of the clock signals C ₁ and C ₂ , and the test result is output as output data D ₁ via the flip-flop circuit 5 to the data compression circuit 1.
Enter in 5.

In the data compression circuit 15, as shown in FIG. 2, the frequency divider circuit 20 divides the test clock signal 12 into 1 /
It is divided by 2 and output as a 1/2 divided clock signal 24. Then, in the logic circuit 22, the exclusive OR operation of the output data D ₁ and the output data D ₂ is performed to output the output data D ₃
Is output as. Then, the test mode control signal 14
Is active, the switch circuit 23 outputs the output data D ₃
Is output as device output data 13. This situation is shown in the timing chart of FIG.

In FIG. 2, continuous data of the output data D ₁ is ... (n-1), (n), (n + 1),
(N + 2), ... will be described in order. Here, for example, when the output data D ₁ is the (n−1) th data, the output data D ₂ is the (n−2) th data, so the device output data 13 is (n−2) ·
The data is represented by (n-1).

Here, (n-2). (N-1) is (n-
The result of the logical operation of the (2) th data and the (n-1) th data is shown. In the present embodiment, since the exclusive OR is used for this logical operation, the result of the exclusive OR operation of the (n-2) th data and the (n-1) th data is actually shown. ing.

Then, in the LSI tester 10, data is read at the timing when the tester strobe shown in FIG. 2 is generated. The tester strobe is a signal generated inside the LSI tester 10 and indicates the timing of reading data.

Since the correct output of the signal processing circuit 2 for the test pattern data 11 output from the LSI tester device 3 is known in advance, the data of the correct prediction result is prepared as an expected value, and the expected value is set to the LSI. The signal processing circuit 2 is provided by comparing the expected value data given to the tester 10 with the read device output data 13.
You can check the operation of.

In the operation test using this embodiment, when the test pattern data 11 is sent to the signal processing circuit 2, L
A high-speed clock is generated and used from the clock signals C ₁ and C ₂ output from the SI tester 10, while the output data D ₃ from the signal processing circuit 2 is generated by combining the output data D ₁ and D _2. Therefore, the output data D ₃ is the LSI tester 10
Returned at its own clock frequency. As described above, the operating frequency of the output data D ₃ is lowered by combining the two output data D ₁ and D ₂ into one data, but this occurs unless the original data is continuously in error. The error can be detected. Since the probability of continuous error occurrence is very low, a practical problem does not occur by determining the logical operation result of continuous data and detecting the error.

As described above, in the test circuit of the semiconductor integrated circuit according to the present embodiment, a signal operating at a frequency up to twice the maximum operating frequency of the LSI tester 10 without repeating the same test. The processing circuit 2 can be tested.

(Second Embodiment) Next, a test circuit for a semiconductor integrated circuit according to a second embodiment of the present invention will be described. The same numbers as in FIG. 1 indicate the same components.

In this embodiment, the data compression circuit 15 in the first embodiment of FIG. 1 is replaced with a data compression circuit 35. FIG. 3 shows a block diagram of the data compression circuit 35.

The data compression circuit 35 includes exclusive OR circuits 31 to 33, flip-flop circuits 21 and 34,
And a switch circuit 23.

The flip-flop circuit 21 operates by using the test clock signal 12 as a clock, and holds the output data D ₁ output from the flip-flop circuit 5 and then outputs it.

The flip-flop circuit 34 operates by using the test clock signal 12 as a clock, temporarily holds the output signal from the flip-flop circuit 21, and then outputs it.

The exclusive OR circuit 31 outputs the output data D ₁
And an output signal from the flip-flop circuit 21 is subjected to exclusive OR operation and the operation result is output.

The exclusive OR circuit 32 outputs the output data D ₁
And an output signal from the flip-flop circuit 34 is subjected to an exclusive OR operation and the operation result is output.

The exclusive OR circuit 33 performs an exclusive OR operation on the output signal from the exclusive OR circuit 31 and the output signal from the exclusive OR circuit 32, and outputs the operation result.

The switch circuit 23 outputs the output data D ₁ as the device output data 13 when the test mode control signal 14 is inactive, and outputs from the exclusive OR circuit 33 when the test mode control signal 14 is active. The output signal is output as device output data 13.

Next, the operation of this embodiment will be described with reference to FIG.

Here, for example, in the output data D ₁ , (n),
It is assumed that data (n + 1) and (n + 2) are continuously input. In this case, at the timing when the data D ₁ is the data (n), the output signal from the flip-flop circuit 21 is (n + 1) and the flip-flop circuit 34 is
The output signal from is data of (n + 2). Therefore, from the exclusive OR circuit 31, (n)
The logic data (n + 1) is output, and the exclusive OR circuit 32 outputs the logic data (n). (N + 2). Therefore, the exclusive OR circuit 33 outputs logical data of ((n). (N + 1)). ((N). (N + 2)).

Here, (n) · (n + 1) indicates the result of the exclusive OR operation of the data (n) and the data (n + 1).

Then, the LSI tester 10 reads every other data and compares it with an expected value prepared in advance.

For example, using the case of the example described above, the LSI tester 10 has ((n). (N + 1)). Multidot.
After the data of ((n) ・ (n + 2)), ((n + 2))
-(N + 3))-((n + 2)-(n + 4)) logic data will be read.

With this method, in this embodiment, the output data (n), (n + 1) from the signal processing circuit 2,
If an error occurs in any of (n + 2), (n + 3), (n + 4), ..., The LSI tester 10 can detect the error.

In this embodiment, the exclusive OR circuits 31 to 31 are used.
The output data D ₁ was compressed using 33.
The present invention is not limited to this, and the same effect can be obtained by using a logic circuit having another logic instead of the exclusive OR circuits 31 to 33.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG. The same numbers as in FIG. 1 indicate the same components.

In this embodiment, four data compression circuits 15 are provided.
Is replaced with the data compression circuit 45 shown in FIG. However, in the present embodiment, the test mode control signal 14 does not switch since it does not have the function of switching the operating frequency for performing the operation test.

The data compression circuit 45 includes the frequency dividing circuit 20 and
It is composed of flip-flop circuits 26 to 29 and a full adder 36.

The flip-flop circuits 26 to 29 have 1 /
It operates by using the divided-by-two clock signal 24 as a clock, and each of the output data 40 ₁ to 40 ₄ is once held and then output.

The full adder 36 outputs 4-bit data output data 40 ₁ to 40 ₄ and the flip-flop circuit 26.
4 to 29 are added, and the result is added to the device output data 41 ₁ which is 5 bit data.
To 41 to output as a _5.

Then, in the LSI tester 10, the second
In the same manner as in the embodiment of the above, every other data is read and compared with the expected value prepared in advance. Thus, although the present embodiment has been described using a 4-bit full adder, the present invention is not limited to this, and an n (n is a positive integer) bit full adder is used. It is also applicable in the case.

In the first to third embodiments, the data compression circuit is provided in the semiconductor integrated circuit, but the present invention is not limited to this, and the data compression circuit may be provided in the LSI tester device. Good.

In the first and second embodiments, the signal output by the switch circuit 23 is switched to switch between a test requiring an operating frequency higher than the maximum operating frequency of the LSI tester 10 and a test not requiring it. However, the test may be performed at an operating frequency higher than the maximum operating frequency of the LSI tester without providing the switch circuit 23.

Further, although the case where a single-phase clock signal is generated by using a two-phase clock signal has been described in the first to third embodiments, the present invention is not limited to this. The present invention can also be applied to a case where a single-phase clock signal is generated using three-phase, four-phase, ... N-phase (n is a positive integer) clock signal. In this case, an operation test of the semiconductor integrated circuit is performed by generating a single-phase test clock signal having a frequency of n times using the n-phase clock signal and inputting the test clock signal. By compressing n pieces of data into one piece of data, the frequency of the output data is set to 1 / n and comparison with an expected value is performed.

[0089]

As described above, the present invention has the effect that a semiconductor integrated circuit whose operating frequency is equal to or higher than the maximum operating frequency of an LSI tester can be tested without increasing the test time.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a method for testing a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart of various signals for explaining the operation of the test circuit of the semiconductor integrated circuit of FIG.

FIG. 3 is a block diagram showing a configuration of a data compression circuit 35 according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a data compression circuit 45 according to a third embodiment of the present invention.

FIG. 5 is a diagram for explaining a conventional semiconductor integrated circuit test method.

[Explanation of symbols]

1 Digital signal processing LSI 2 Signal processing circuit 3 LSI tester device 4, 5 Flip-flop circuit (F / F) 6, 7 Switch circuit (SW) 8 Pattern generating circuit 9 OR circuit 10 LSI tester 11 Test pattern data 12 Test clock Signal 13 Device output data 14 Test mode control signal 15 Data compression circuit 20 Dividing circuit 21 Flip-flop circuit (F / F) 22 Logic circuit 23 Switch circuit (SW) 24 1/2 Dividing clock signal 26-29 Flip-flop circuit (F / F) 31 to 33 Exclusive OR circuit 34 Flip-flop circuit (F / F) 35 Data compression circuit 36 Full adders 40 ₁ to 40 ₄ Output data 41 _{1 to} 41 ₅ Device output data 45 Data compression circuit 51 digital signal processing LSI P _1, P ₂ test pattern data _1, C ₂ clock signals D _1, D _2, D ₃ output data

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G01R 31/28-31/3193 H01L 27/04

Claims (11)

(57) [Claims] 1. A semiconductor integrated circuit for inputting test pattern data to a semiconductor integrated circuit and comparing output data output from the semiconductor integrated circuit with an expected value prepared in advance to perform an operation test of the semiconductor integrated circuit. In the test circuit of the circuit, the test clock that the semiconductor integrated circuit uses as a reference for operation.
The clock signal is divided by a constant dividing value to obtain a divided clock signal.
And output the divided clock signal and the divided clock signal.
It operates as a clock and holds the output data once
Output the flip-flop circuit and the output
Between the data and the output from the flip-flop circuit.
Is composed of a logic circuit for performing a management operation, the output data that is output from the semiconductor integrated circuit, by calculating the data each other temporally located before and after the continuous data, than the number of data of the output data A test circuit for a semiconductor integrated circuit having a data compression circuit that compresses and outputs a small number of data. Wherein said logic circuit is an exclusive test circuit of a semiconductor integrated circuit according to claim 1, wherein the sum is a circuit. 3. A semiconductor integrated circuit for inputting test pattern data to a semiconductor integrated circuit and comparing output data output from the semiconductor integrated circuit with an expected value prepared in advance to perform an operation test of the semiconductor integrated circuit. A first flip-flop circuit that operates by using the test clock signal as a clock and temporarily holds the output data and then outputs the test data; and a test circuit of the circuit that operates by using the test clock signal as a clock. , A second flip-flop circuit that holds the output signal from the first flip-flop circuit and then outputs the signal, and a logical operation of the output data and the output signal from the first flip-flop circuit A first logic circuit for outputting a result, the output data and an output signal from the second flip-flop circuit. And a second logic circuit for performing a logical operation with respect to each other and outputting the operation result, and an output signal from the first logic circuit and an output signal from the second logic circuit are subjected to a logical operation to obtain the operation result. is composed of a third logic circuit for outputting the said output data that is output from the semiconductor integrated circuit, by calculating the data each other temporally located before and after the continuous data, the number of data of the output data A test circuit for a semiconductor integrated circuit, comprising a data compression circuit for compressing and outputting a smaller number of data. 4. The test circuit for a semiconductor integrated circuit according to claim 3, wherein the first logic circuit, the second logic circuit, and the third logic circuit are exclusive OR circuits. 5. A semiconductor integrated circuit for inputting test pattern data to a semiconductor integrated circuit and comparing output data output from the semiconductor integrated circuit with an expected value prepared in advance to perform an operation test of the semiconductor integrated circuit. In a circuit test circuit, a frequency dividing circuit that divides a test clock signal, which is used as a reference for operation of the semiconductor integrated circuit, by a constant frequency dividing value and outputs the divided clock signal, and the frequency dividing clock signal as a clock. A plurality of flip-flop circuits that operate using the above-mentioned output data and temporarily hold each of the plurality of output data, and add the plurality of output data and the output data from the plurality of flip-flop circuits to perform the operation is composed of a full adder for outputting a result, the output data that is output from the semiconductor integrated circuit, continuous data By calculating the data each other to be located before and after in time, the test circuit of the semiconductor integrated circuit characterized by having a data compression circuit for outputting compressed into a smaller number of data than the number of data of the output data. 6. A semiconductor device having a test circuit of a semiconductor integrated circuit according to any one of claims 1 to 5. 7. A test circuit for a semiconductor integrated circuit according to any one of the data compression circuit LSI tester device that is incorporated into the claims 1 to 5. 8. A semiconductor integrated circuit for inputting test pattern data to a semiconductor integrated circuit and comparing output data output from the semiconductor integrated circuit with an expected value prepared in advance to perform an operation test of the semiconductor integrated circuit. in the test method of the circuit, among the continuous data of the output data, the first three in a row in time, using the second and third data, said first data said second data A logical operation is performed to obtain the operation result as fourth data, a logical operation is performed to the first data and the third data to obtain the operation result as fifth data, and the fourth data and the fifth data are obtained. by performing a logical operation of data, and wherein the output data that is output from the semiconductor integrated circuit, and outputs the compressed smaller number of data than the number of data of the output data Method of testing a semiconductor integrated circuit that. 9. The method for testing a semiconductor integrated circuit according to claim 8 , wherein the logical operation is an exclusive OR operation. 10. A semiconductor integrated circuit for inputting test pattern data to a semiconductor integrated circuit and comparing output data output from the semiconductor integrated circuit with an expected value prepared in advance to perform an operation test of the semiconductor integrated circuit. In a circuit testing method, a plurality of the output data at a certain time and a plurality of the output data at a time different from the certain time by a time corresponding to one cycle of a test clock signal which is a reference of operation of the semiconductor integrated circuit. by adding with full adder, the said output data that is output from the semiconductor integrated circuit, the semiconductor integrated circuit and outputting compressed into a smaller number of data than the number of data of the output data Test method. 11. A test clock signal having a frequency n times and test pattern data corresponding to the test clock signal are generated by using n clock signals (n is a positive integer) having different phases, and the test clock is generated. An operation test of the semiconductor integrated circuit is performed by inputting a signal and the test pattern data, and the output data output from the semiconductor integrated circuit is compressed into one piece of n pieces of data that are temporally located before and after. Thus, a test method of a semiconductor integrated circuit for performing an operation test of the semiconductor integrated circuit by setting the frequency of the output data to 1 / n and then comparing it with an expected value prepared in advance.