JP3360706B2 - Silicon substrate surface treatment method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for treating a surface of a silicon substrate applied to the manufacture of an integrated circuit or the study of a crystal surface, and more particularly to a method of artificially controlling atomic steps existing on the surface of a silicon substrate. Separating the flat area and the area where steps are gathered on the atomic scale with an arbitrary pattern,
Or to realize a regular atomic step arrangement structure,
The present invention relates to a surface treatment method for a silicon substrate which forms a flat crystal plane in which atomic steps are partially absent or extremely low in atomic step density on the surface of the silicon substrate.

[0002]

2. Description of the Related Art A conventionally used silicon substrate is cut into a wafer and then subjected to mechanical chemical polishing, and atomic steps are randomly present on the surface of the silicon substrate. Atomic steps occur because of the slight angle between the low index crystal plane and the actual surface at the height of one or several atomic layers.

[0003] Atomic steps are defects on a flat surface and affect the characteristics of a device having a surface or interface as an active layer. Therefore, it is necessary to artificially control the atomic step distribution on the surface of the silicon substrate used as the substrate of the element, and to eliminate the atomic step from the element active layer. Also,
The atomic step also acts as a starting point for adsorption and epitaxial growth on the crystal surface. In a conventional silicon substrate, since the density of atomic steps is high, the influence of atomic steps always exists on adsorption and crystal growth. In order to elucidate the basic processes of adsorption and crystal growth, research in a situation without atomic steps has been desired.

[0004]

However, the conventional silicon substrate has the following problems because atomic steps exist randomly on the substrate surface. First, in the MOS transistor according to the prior art, as the gate oxide film becomes extremely thin, the irregularities at the interface of the oxide film on the atomic scale are affecting the withstand voltage and the long-term deterioration of the withstand voltage. That is, according to the prior art, it was not possible to avoid irregularities due to atomic steps randomly present on the surface.

[0005] In recent years, attempts have been made to form a fine structure using atomic steps on the surface. For example, using a molecular beam epitaxial growth method or a chemical vapor deposition method, a crystal layer having the first composition is grown only in a region along the atomic step from the end of the atomic step, and the crystal layer having the second composition is left. A fractional layer superlattice in which a long period parallel to the surface is provided by repeating the above process by growing in a region of the above type has been proposed.

However, when this fractional layer superlattice is formed by the conventional technique, the atomic step ends where crystal growth progresses are not regularly arranged over the entire surface of the wafer, so that only a part of the inside of the wafer is formed as designed. There is a problem that a region where a fractional layer superlattice is correctly formed cannot be specified.

In addition, it is extremely difficult to accurately match the actual surface of a silicon substrate manufactured by conventional mechanical chemical polishing with a low-index crystal plane. There was an error of about 0.3 degrees with the crystal plane. This is an atomic step density of 10 ⁵ / cm,
That is, one atomic step was present at 100 nm intervals. Therefore, an element active layer having a size of several hundred nm to several μm contains several to several tens of atomic steps, and the influence of the atomic steps on the element characteristics is inevitable.

Although it has been possible to improve the precision of the mechanical chemical polishing and improve the above-mentioned error to about 0.03 degrees, the cost of the silicon substrate is ten times or more, and it is used for general device manufacturing. I couldn't do that. On the other hand, basic research in surface science required a silicon substrate with a lower atomic step density, for example, a substrate with an atomic step interval of 10 μm or more, but it is practically impossible to obtain such a highly accurate silicon substrate. It was possible.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a method of surface treating a silicon substrate capable of arranging atomic steps at designated positions over the entire surface of a wafer. To provide.

Another object of the present invention is to provide a surface treatment method for a silicon substrate capable of forming a flat crystal plane having no atomic steps or an extremely low atomic step density at a designated position on the surface of the silicon substrate. Is to do.

[0011]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device in which a concave portion made of silicon for controlling the movement of an atomic step is previously formed on a silicon substrate. It is formed by processing technology, and then heat-treated in an ultra-high vacuum or an inert gas having the same effect as the ultra-high vacuum to artificially control the rearrangement of atomic steps that occur during the cooling process. It was done.

In another aspect of the present invention, a concave portion having an atomic step therein is formed at a predetermined position on a silicon substrate by a fine processing technique used in a normal integrated circuit manufacturing process. In a vacuum, in a reducing atmosphere or in an inert gas without a coating
Heat treatment at a temperature of 00 ° C or higher
From the part where the directions of the steps are opposite to each other,
The atomic steps are retreated in opposite directions according to the direction, so that the atomic steps are eliminated from the bottom surface of the concave portion.

[0013]

The silicon atoms on the clean surface of the silicon substrate are
At high temperatures in ultra-high vacuum, they are free to move, so that the atomic steps on the silicon substrate can also change their arrangement. It is known that when cooling from a high temperature to a low temperature, even in the process, the atomic steps rearrange in accordance with the inclination direction, the inclination angle, the cooling rate, etc. from the ideal low index surface of the silicon substrate surface. However, for example, there are 6.4 × 10 ⁵ steps per cm on the (100) plane inclined by 0.5 °, and it is impossible to form a uniform array over the entire silicon substrate as it is. However, if there are nuclei that restrict the movement of atomic steps when the atomic steps rearrange, and if they are arranged regularly, the steps will be arranged along those nuclei, and the arrangement control over the entire silicon substrate is possible Becomes

The nucleus for arranging such atomic steps has a certain effect even if it is a fine crystal of, for example, silicon carbide, but is harmful in the process of manufacturing an integrated circuit and should be avoided from being used. It is. In the present invention, after arranging atomic steps, recess of the wafer surface that was its core is completely flattened, in addition to atomic step are arranged in no difference between the wafer according to the prior art. Therefore, it has a feature that it has no effect on the subsequent integrated circuit manufacturing process and can be used as it is in the conventional manufacturing process.

When a clean silicon substrate surface without a coating is heat-treated in a vacuum, a reducing atmosphere or an inert gas,
Evaporation of surface atoms occurs. Since the evaporation of the surface atoms occurs selectively from the position of the atomic steps, the atomic steps move with the evaporation. In the recess formed on the surface,
There is always a portion where the direction of the atomic steps is reversed between the bottom surface and the side wall surface surrounding the bottom surface. In this part, since the moving direction of the steps is reversed, the terrace region without the atomic steps is enlarged by thermal evaporation.

By continuing the heat treatment, the atomic steps can be gathered to the side wall, and finally the atomic steps can be eliminated from the entire bottom surface of the concave portion. The shape and size of the concave portion can be arbitrary. Further, since the fine processing technique used in the integrated circuit manufacturing process is used, a required number of flat crystal planes without atomic steps can be formed at desired positions on the silicon substrate.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. (Embodiment 1) FIG. 1 is a perspective view of a silicon substrate for describing one embodiment of a method for treating a surface of a silicon substrate according to the present invention. In FIG. 1, 1 is a silicon substrate, 2 is a group of atomic steps (hereinafter referred to as a step bunch),
3 is a first area in which the step bunches 2 are regularly arranged;
Reference numeral 4 denotes a second region in which the step bunches 2 are regularly arranged. The first region 3 and the second region 4 are different from each other in the interval between the step bunches 2 and the like.

The present embodiment is a method for treating the surface of a silicon substrate in which atomic steps are regularly collected at predetermined positions. The number of atomic steps included in these step bunches 2 and the distance between the step bunches 2 are different. The distance can be freely selected at a place in the plane of the silicon substrate.

FIG. 2 to FIG. 5 are perspective views of a main part of each step for explaining the surface treatment method for the silicon substrate shown in FIG. In these figures, reference numeral 5 denotes the silicon substrate 1 described above.
, 6 are fine holes (hereinafter referred to as small holes) formed in the main surface of the portion 5 of the silicon substrate 1, and 7 is the silicon substrate 1.
Atomic steps existing on the main surface of a part 5 of the above, and steps 8 and 9 are step bunches.

Hereinafter, the process and principle of forming the silicon substrate of the first embodiment will be described. First, a silicon wafer manufactured by a normal process is prepared. This wafer has no particular restrictions, but the surface index, ie, (10
The arrangement of the atomic steps differs depending on whether the plane is the (0) plane, the (111) plane or another index plane, and the density of the atomic steps differs depending on the inclination angle from the ideal index plane. Therefore, the choice of the wafer surface should be determined by the use of the wafer produced according to the present invention.

In the present embodiment, a wafer having a silicon (111) plane inclined at one degree in the [1,1, bar 2] direction as a main surface is prepared, washed by a known method, and then placed on the main surface of the wafer. to form fine <br/> recess in a pattern corresponding to the desired atomic step structure, a structure shown in FIG. The processes used here are known photolithography and reactive ion etching, and do not require special techniques. In this embodiment, small holes 6 having a radius of 0.5 μm and a depth of 0.1 μm are formed at intervals of 2 μm.
It was formed on the entire surface of the wafer with a thickness of μm.

Next, after cleaning the wafer, the wafer was heated in a high vacuum apparatus. Here, the vacuum pressure is 10 ⁻¹⁰ Torr, 1
Heat treatment was performed at 200 ° C. for 5 minutes. Recess of the wafer surface in this process occurs the migration of silicon atoms on the surface to be flat. This movement will become very active if it exceeds 1100 ° C., the concave portion of the above-mentioned substrate surface is lost, will be substantially planarized. Note that, by flattening due to loss of the recessed portion is processed such subsequent element becomes easy.

At this time, the atomic steps existing on the surface are rearranged, but the movement of the atomic steps stops at the small hole 6 formed first and does not move any further. For this reason, all the atomic steps existing between the small hole 6 and the adjacent small hole 6 gather at the small hole 6 to form a step bunch 8 as shown in FIG. This step bunch 8
Does not change position until the small holes 6 are completely filled and the surface becomes flat.

Thereafter, when the substrate temperature is lowered, the step bunches 8 are maintained as they are, so that the rows of small holes 6 are first formed as shown in FIG. Thus, a wafer is obtained in which the small holes 6 shown in FIG. 2 have completely disappeared.

In the above-described embodiment, even if the interval between the rows of the small holes 6 is doubled, for example, the atomic steps between the rows of the small holes 6 are also collected at the position of the small holes 6. Step bunches are also formed simultaneously for a pattern having a row spacing of. Therefore, it is possible to rearrange the atomic steps on the wafer in different patterns as shown in FIG.

According to such a surface treatment method, atomic steps existing on the surface can be collected at a designated position on the wafer. For example, if the present invention is applied to the formation of a MOS integrated circuit, the element isolation in the circuit pattern can be achieved. Atomic steps can be collected in a portion that is not easily affected by atomic steps, such as a region or a wiring region. When a MOS integrated circuit is formed on such a wafer, there is no atomic step immediately below the gate oxide film, and the wafer is flat on a scale smaller than the atomic step. In addition, the reliability is not deteriorated, so that the gate oxide film can be further reduced in thickness.

(Embodiment 2) FIGS. 6 to 8 are perspective views of main parts of respective steps for explaining another embodiment of the method for treating the surface of a silicon substrate according to the present invention. In the present embodiment, an attempt is made to realize step arrays arranged at equal intervals required for a fractional layer superlattice or the like at designated positions. FIG. 6 shows the same structure as that of FIG. 4 described above, and is the same as the manufacturing process. However, in this embodiment, a silicon (111) plane tilted once in the [bar 1, bar 1, 2] direction is used. Is different.

In FIG. 6, the step bunch 9 is maintained until the small hole 6 formed first is completely filled. However, when the temperature is lowered after the small holes 6 are filled, the step bunch 9 is melted again as shown in FIG. 7, and after a sufficient time, finally, the atomic step is performed as shown in FIG. 12 are rearranged at equal intervals. Here, 9 is a step bunch already formed, 10 is an atomic step separated from the step bunch 9, 11 is an atomic step separated from the step bunch 10 and sufficiently separated, 1
Numeral 2 indicates each atomic step after rearrangement.

In this embodiment, the reason why such rearrangement of atomic steps occurs during cooling is that a step bunch is formed at room temperature on the silicon (111) plane inclined in the [1,1, bar 2] direction. Is stable while silicon (111) inclined in the direction of [bar 1, bar 1, 2]
This is because the surface is more stable when the atomic steps are apart from each other.

In this embodiment, after the small holes 6 are filled by a heat treatment at 1200 ° C., the temperature is immediately cooled to 900 ° C., and then the temperature is decreased by 10 ° C. per minute, and the step bunch 9 is sufficiently released to remove the atomic steps. Were equally spaced to obtain a structure as shown in FIG.

When the present invention is not used, countless atomic steps have no correlation over long distances, and when a certain place is designated, a regular step arrangement is not always realized at that position. However, in this embodiment, the atomic steps are once collected at the position specified by the small holes, and then the atomic steps are solved again.Therefore, the atomic steps are set at a fixed position on the wafer, for example, in a region where a fractional superlattice is to be formed. They can be arranged regularly.

In forming a fractional layer superlattice by the surface treatment method according to the present embodiment, it is necessary to arrange atomic steps on the wafer surface at equal intervals. Since the atomic steps have a repulsive force, they can be partially arranged at equal intervals by selecting appropriate conditions. By using this embodiment, the atomic steps can be arranged at a predetermined position. If appropriate heat treatment and cooling are performed from this state, the atomic steps are separated from each other and are arranged at equal intervals,
Since the initial state has an order over a long distance, a region in which atomic steps are regularly arranged and a boundary region between these regions are determined by the first microfabrication pattern.

In order to integrate a device using the fractional layer superlattice, a device pattern is allocated to a place where the fractional layer superlattice is formed as designed, and the boundary region is used as an element isolation region or a wiring region. Just do it.

In the above-described embodiment, the case where the silicon substrate is heat-treated in a high vacuum has been described. However, the present invention is not limited to this. For example, the heat treatment may be performed in a reducing atmosphere or in an inert gas. It goes without saying that the same effect as described above can be obtained even if heat treatment is performed.

(Embodiment 3) FIGS. 9A and 9B are diagrams for explaining another embodiment of the method for treating the surface of a silicon substrate according to the present invention. FIG. 9B is a plan view of the recess formed in FIG.
It is sectional drawing of a line. In FIG. 9, 21 is a silicon substrate, 22 is an atomic step, 23 is a low-index crystal plane, 24
Is a bottom surface of the concave portion, and 25 is a side wall of the concave portion.

In FIG. 9, steps and intervals of the atomic steps 22 are emphasized for convenience of explanation. Although the crater formed on the surface as the cross-sectional shape of the concave portion, the plane surrounded by the convex portion, and the three types of structures in which a part of the convex portion is opened are illustrated, the shape of the side wall 25 portion is different from these three types. The shape and the inclination angle are not limited and may be any shape. Any number of these concave portions can be formed at desired positions on the silicon substrate 21.

When a part of the convex portion is open,
The open part is taken on the high side of the atomic step stairs. As explained below, the side wall of the convex portion on the lower side of the step of the atomic step has an important effect on the movement of the atomic step.
FIG. 9 shows a general case where the direction of the atomic step 22 does not completely match the direction of the concave boundary pattern. The effect of this embodiment can be obtained regardless of the pattern direction for the atomic step 22.

FIGS. 10A to 10D are cross-sectional views for explaining the process of forming a region having no atomic steps by heat treatment using the crater as an example in the concave portion shown in FIG. Similar effects can be obtained for recesses having other shapes. Hereinafter, a process of forming a region without an atomic step will be described with reference to the drawings.

First, a silicon wafer manufactured by a normal process is prepared. Although there is no particular restriction on this wafer, the distribution and height of atomic steps differ depending on the plane index, that is, the (100) plane, the (111) plane, or other index planes. The atomic step density differs depending on the tilt angle. Therefore, the choice of the wafer surface should be determined by the use of the wafer produced according to the present invention.

In this embodiment, a wafer whose main surface is a silicon (111) plane inclined by 1.5 degrees in the [1,1, bar 2] direction is prepared, and is cleaned by a known method. A concave portion is formed in a desired pattern on the surface, and FIG.
The structure shown in FIG. The process used here is a known photolithography method and a reactive ion etching method, and does not require a special technique. In this embodiment, the depth is 1 μm.
m, a rectangular recess having an area of 20 μm × 100 μm and an interval of 2
It was formed on the entire surface of the wafer at 0 μm.

Next, the wafer is washed in a dilute hydrofluoric acid solution to remove an oxide film on the surface, and then thinned using an oxidizing solution, here, a mixed solution of sulfuric acid, hydrogen peroxide and water. An oxide film was formed. Next, the wafer was heated in a high vacuum apparatus. Here, the heat treatment was performed at a heating temperature of 1200 ° C. by electron beam irradiation in a high vacuum at a pressure of 10 ⁻¹⁰ Torr. The temperature is (7 × 7) on the silicon (111) surface.
The (1 × 1) phase transition temperature was calibrated at 830 ° C.

In the process of raising the temperature in a vacuum, the thin oxide film on the wafer surface is evaporated between 800 ° C. and 900 ° C. to obtain a clean surface. Heating a clean surface at a high temperature causes movement and evaporation of atoms on the wafer surface. When these temperatures exceed 1100 ° C., they become extremely active, and promote the movement of the steps described below, and flatten fine irregularities generated on the surface by reactive ion etching. Therefore, the heating temperature is 1100
It is preferable that the temperature is not lower than ° C.

By heating, the atoms on the surface become atomic steps 2
Evaporate selectively from position 2. As a result, FIG.
As shown in (b), the side wall 25 of the concave portion changes into a step bunch in which high-density atomic steps are gathered. On the other hand, at the point A on the bottom surface located on the lower side of the stairs of the atomic step, the atomic step retreats leftward on the side wall 25 side, whereas the atomic step 22 moves rightward on the bottom surface 24, The (111) crystal plane 23 expands. By continuing the heating, the (111) crystal plane 23 continues to expand as shown in FIGS. 10C and 10D, and finally the entire bottom surface 24 of the concave portion has no (111) crystal plane without the atomic step 22. 23.

FIG. 11 is a diagram showing the relationship between the heating time at 1220 ° C. and the width of the (111) crystal plane. As plotted with a circle in the figure, a region having a width of 20 μm could be changed to a (111) crystal plane without atomic steps by heating for about 20 minutes. As described above, the evaporation of surface atoms due to high-temperature heating mainly occurs from the end of atomic steps, but when the heating temperature is as high as 1200 ° C. or higher, (111)
If the width of the crystal plane exceeds 15 μm, evaporation occurs in the center of the terrace. In this case, one hole with a depth of one atomic layer is formed at the center of the terrace at an interval of about 10 μm and surrounded by atomic steps. However, the resulting step density is one or two per 10 μm, which is virtually negligible.

As described above, in FIG. 9, even if the sides of the rectangular recess do not match the directions of the atomic steps,
An intended flat surface can be obtained. However, as can be easily understood from geometrical considerations, a flat surface can be obtained in the shortest heating time when one side of the rectangular concave portion matches the direction of the atomic step. At this time, the side wall of the concave portion orthogonal to the atomic step does not contribute to the retreat of the atomic step, but has an action of isolating the atomic step on the bottom surface of the concave portion from the atomic step outside the concave portion. If this side wall does not exist, the retreat of the atomic step stops halfway because it is affected by the outer atomic step.

In the above-described embodiment, the electron beam heating in a vacuum is used. However, the present invention is not limited to this. For example, other known methods can be used for the heating means. Similar effects can be obtained by heating in a reducing atmosphere or an inert gas atmosphere.

(Embodiment 4) FIG. 12 is a cross-sectional view showing the vicinity of the surface of a concave portion formed in a silicon substrate for explaining another embodiment of the surface treatment method for a silicon substrate according to the present invention. In FIG. 12, reference numeral 26 denotes a DC power supply. In this embodiment, a direct current is directly supplied from a DC power supply 26 to the silicon substrate 21 to heat the silicon substrate 21 to form a wide flat surface without the atomic steps 22. FIG. 12 has the same structure as that of FIG. 9 described above, and has the same manufacturing process, cleaning, and temperature raising step. In this embodiment, however, a current is supplied in a direction substantially orthogonal to the atomic steps 22 of the silicon substrate 21 to supply current. Performing heating is different.

In the present embodiment, a wafer having a resistivity of about 10 Ωcm and having a silicon (111) plane inclined at 1.5 degrees in the [1,1, bar 2] direction as a principal surface is used, and the direction of the atomic step is lowered. A direct current was passed in the [1,1, bar 2] direction, and the substrate was heated to 1220 ° C. in a high vacuum at a pressure of 10 ⁻¹⁰ Torr. The combination of the heating direction and the energizing direction down the atomic step is a condition for inducing step bunching on a surface inclined with respect to the (111) plane. The temperature range in which step bunching is induced and the direction of energization to the atomic steps (in other words, the direction of the electric field) are described in known literature (for example, Y.
Homma, RJ McClell and H. Hibino: Jpn.J. Appl. Phys. 29
(1990) L2254).

According to this document, in a temperature range of 830 ° C. to 950 ° C. and 1200 ° C. to 1300 ° C., step bunching occurs when an electric field is applied in a direction down an atomic step. In addition, 1050 ° C to 1150 ° C and 1
In a temperature range higher than 300 ° C., a step bunching occurs when an electric field is applied in the direction in which the atomic steps rise. Therefore, in this embodiment, when an electric field is applied in a direction that induces step bunching, movement of surface atoms is promoted, and formation of a flat surface is accelerated.

In FIG. 11, the relationship between the heating time and the width of the (111) crystal plane according to the present embodiment is plotted with a black circle. Compared to Example 3, the width of the (111) crystal plane increased at twice the speed. Therefore, according to the present embodiment, a flat surface can be formed in a shorter time.

Although FIG. 11 shows an example in which the width of the (111) crystal plane is up to about 40 μm, a flat surface without atomic steps of the order of 100 μm can be easily formed by heating for a long time. it can. If a wafer having a small inclination angle from the (111) crystal plane is used, a wide flat surface can be obtained in a shorter time.

In this embodiment, electric heating in vacuum is used, but the present invention is not limited to this.
For example, the same effect can be obtained by conducting electric heating in a reducing atmosphere or an inert gas atmosphere. Further, the same effect can be obtained by disposing the silicon substrate in an electric field and heating by another known method instead of the direct current heating.

[0053]

As described above, according to the present invention,
Since atomic steps existing on the surface can be arranged at specified positions on the silicon substrate, dielectric breakdown voltage and long-term deterioration of breakdown voltage due to irregularities caused by atomic steps existing randomly on the surface are eliminated, and reliability and yield are improved. Performance can be improved without lowering.

According to the present invention, an atomic step existing on a surface is arranged at a designated position on a silicon substrate.
Then, the atomic steps are solved again, so that the atomic steps can be regularly arranged at a predetermined position on the silicon substrate (for example, a region where a fractional superlattice is to be formed),
High-density integration and high yield of devices using fractional layer superlattices can be achieved.

According to another aspect of the present invention, a flat surface without atomic steps can be formed at a position specified on a wafer. Steps can be excluded from a certain channel region, and atomic steps can be collected in a portion susceptible to the atomic steps, such as an element isolation region and a wiring region. When a MOS integrated circuit is formed on such a wafer, there is no atomic step immediately below the gate oxide film, and the wafer is flat on a scale smaller than the atomic step. In addition, there is no deterioration in reliability, and therefore, an extremely excellent effect that the thickness of the gate oxide film can be further reduced can be obtained.

Further, according to the present invention, a wide area of several tens to several hundreds μm or even on the order of mm can be formed as a crystal plane having a low index without any step. A flat surface without such a wide atomic step is practically impossible to realize by a conventional polishing method. Therefore, by using the silicon substrate manufactured according to the present invention, it is possible to conduct research on surface adsorption and epitaxial growth without being affected by atomic steps, and to make great progress in basic science research. This is an extremely excellent effect.

Further, the method for treating the surface of a silicon substrate according to the present invention can be applied to all fields of silicon integrated circuits, and has an extremely excellent effect that it can be used as a substrate for research and development or for experiments.

[Brief description of the drawings]

FIG. 1 is a perspective view of a silicon substrate for explaining one embodiment of a surface treatment method for a silicon substrate according to the present invention.

FIG. 2 is a perspective view of a main part of a step for explaining a surface treatment method for a silicon substrate according to the present invention.

FIG. 3 is a perspective view of a main part of a step that follows the step of FIG. 2;

FIG. 4 is a perspective view of a main part of a step that follows the step of FIG. 3;

FIG. 5 is an essential part perspective view of a step that follows the step of FIG. 4;

FIG. 6 is a perspective view of a silicon substrate for explaining another embodiment of the surface treatment method for the silicon substrate according to the present invention.

FIG. 7 is a perspective view of relevant parts in a step that follows the step of FIG. 6;

8 is an essential part perspective view of a step that follows the step of FIG. 7;

FIG. 9 is a plan view of a silicon substrate for explaining another embodiment of the surface treatment method for a silicon substrate according to the present invention, and FIG.
It is sectional drawing of the A 'line.

FIG. 10 is a perspective view of a main part in each step for explaining a surface treatment method for a silicon substrate according to the present invention.

FIG. 11 is a graph showing a heating time and a flat (11) for explaining the effect of the embodiment of the surface treatment method for a silicon substrate according to the present invention.
1) It is a diagram showing a relationship with the width of a crystal plane.

FIG. 12 is a cross-sectional view of a principal part of a silicon substrate, for explaining another embodiment of the method for treating the surface of a silicon substrate according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Group of atomic steps (step bunch), 3 ... 1st area, 4 ... 2nd area, 5 ... Part of silicon substrate, 6 ... Fine hole (small hole), 7 ... Atomic step, 8 ... step bunch, 9 ... step bunch, 1
0: atomic step, 11: atomic step, 12: atomic step, 21: silicon substrate, 22: atomic step, 2
3: low index crystal plane, 24: bottom surface of concave portion, 25: side wall of concave portion, 26: DC power supply.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/02 H01L 21/20

Claims (11)

(57) [Claims] 1. A method according to claim 1, wherein the silicon is located at a predetermined position on the silicon substrate .
Applying et configured recess, wherein in the silicon substrate high vacuum, heat treated at or in an inert gas in a reducing atmosphere, the specified atomic steps on the surface of the silicon substrate Te <br/> by the recess A surface treatment method for a silicon substrate, wherein the silicon substrate is arranged at different positions to give regularity to the structure of the atomic steps. 2. The silicon substrate according to claim 1, wherein
The silicon substrate whose surface is inclined with respect to the ideal index plane
The concave portion formed on the silicon substrate is
Of a row substantially parallel to the atomic steps on the surface of the silicon substrate
A method for treating a surface of a silicon substrate, characterized in that the surface treatment is performed only on the silicon substrate. 3. The method according to claim 1, wherein
A surface treatment method for a silicon substrate, wherein the temperature of the heat treatment is 1100 ° C. or higher . 4. The method according to claim 1, wherein the silicon substrate is tilted in a [1,1, bar 2] direction.
A surface treatment method for a silicon substrate, wherein the surface is a silicon (111) surface . 5. The method of claim 1, that it had contact <br/> to claim 2 or claim 3, wherein the silicon substrate [bar 1, the bar 2 is an inclined silicon (111) plane in the direction Characteristic surface treatment method for a silicon substrate. 6. A silicon substrate at a predetermined position inside the silicon substrate.
Forming a recess having a child step,
Vacuum, reducing atmosphere or non-
Heat treatment at a temperature of 1100 ° C. or more in an active gas,
The directions of the atomic steps inside the recess are mutually
From the opposite part each other according to the direction of the atomic step
By retracting the atomic step in the opposite direction to
The absence of the atomic step inside the recess of the silicon substrate
Forming a region having a very low atomic step density . 7. The semiconductor device according to claim 6, wherein the recess is formed in the silicon.
Crater with a flat bottom formed on the surface of the control board or
A method for treating a surface of a silicon substrate, wherein the surface is formed from a plane surrounded by convex portions . 8. The method of claim 6 or claim 7, the surface treatment method of a silicon substrate, wherein the shape of said recess is rectangular. 9. A part according to claim 6, 7 or 8, wherein a part of the convex part forming the side wall of the concave part is opened.
A method for treating a surface of a silicon substrate. 10. The method according to claim 6 , wherein the heat treatment is performed by step bunching.
A surface treatment method for a silicon substrate, wherein the method is performed by applying an electric field in an induced direction . 11. The 請 Motomeko 10, before the heat treatment
A surface treatment method for a silicon substrate, wherein a direct current is directly applied to the silicon substrate .