JP3357789B2 - Key scan circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a key scan circuit which scans a key matrix and generates key data corresponding to a pressed key.

[0002]

2. Description of the Related Art In order to detect which key of a key matrix has been pressed, a key scan signal which sequentially changes in the key matrix is generally transmitted. However, a key scan signal is always generated regardless of the key being pressed. In such a case, current consumption increases. Therefore, a key scan circuit that sends out a key scan signal only when a key is pressed has been conventionally proposed.

FIG. 4 shows the configuration of such a key scan circuit.
Shown in In FIG. 4, 1 is a key scan start signal ST
In response to the input, the key scan signals KS1 to KS5 in which the signals sequentially change as shown in FIG. 5 begin to be transmitted, and after transmission, all the signals output the H-level standby signal. The generation circuits 2a to 2e are key scan signals or standby signals KS1 to KS
5 is a key scan driver for outputting each of the output terminals 3a to 3e to the output terminals 3a to 3e.
A key matrix for inputting each signal sent from 3e in the column direction, 6a to 6e input row-direction output signals KM1 to KM5 from the key matrix 4 via the input terminals 5a to 5e, and shape output signals. 7 decodes the output signals KT1 to KT5 and the key scan signals KS1 to KS5 of the signal shaping circuits 6a to 6e, generates key data corresponding to the pressed key, and generates a key data storage circuit 8.
A key scan decoder circuit 9 outputs a scan start signal ST in accordance with output signals KT1 to KT5 of the signal shaping circuits 6a to 6e.

[0004] With the above-described configuration, an H level standby signal is input to the key matrix 4 when no key is pressed. Thus, for example, when a key 4a on the key matrix 4 is pressed, the H-level standby signal KS1 output via the key scan driver 2a is input to the input terminal 5e as an output signal KM5 via the key 4a. . Thereafter, this signal is shaped by the signal shaping circuit 6e, and the shaped signal KT5 is input to the key scan control circuit 9. When an H-level signal is input from any of the signal shaping circuits 6a to 6e, the key scan control circuit 9 sends a scan start signal ST to the key scan signal generation circuit 1, and responds to this signal ST. The key scan signal generation circuit 1 generates a key scan signal K at a predetermined timing.
Transmission of S1 to KS5 is started. Key scan signal KS
1 to KS5 are supplied from the output terminals 3a to 3e to the key matrix 4 by the key scan drivers 2a to 2e,
The key matrix 4 outputs a key scan signal as an output signal via the pressed key. In this case, the key 4a
Since only key is pressed, the key scan output signal KS1
Is input to the input terminal 5e as the output signal KM5,
After being shaped by the signal shaping circuit 6e at the next stage, it is input to the key scan decoder circuit 7. Since the key scan signal itself is also input to the key scan decoder circuit 7, key data corresponding to the pressed key is generated by these two signals and stored in the key data storage circuit 8. When the key scan signal generation circuit 1 has finished transmitting the key scan signals KS1 to KS5, it starts outputting the standby signal, and the state returns to the state described first.

As described above, the key scan circuit is configured to stop the key scan until any key of the key matrix 4 is pressed.

[0006]

In the conventional key scan circuit, each of the signal shaping circuits 6a to 6e includes a waveform shaping inverter 61 and a pull-down resistor 62 connected to its input side as shown in FIG. It was constituted by. Therefore, if an extremely small pulse such as noise enters the input side of the inverter 61 in a state where the key is not pressed, the output signal KT is generated from the signal shaping circuit,
The key scan control circuit 9 sends a scan start signal ST to the key scan signal generation circuit 1 based on this signal. Therefore, a key scan signal is generated even though the key is not pressed. That is, while the key is not pressed, the original function of stopping the key scan signal and suppressing the power consumption of the circuit cannot be satisfied.

Therefore, conventionally, in order to satisfy the original function, measures have been taken to remove noise by connecting capacitors to the input terminals 5a to 5e. However, signals other than the key scan signal and the standby signal are used. In order to surely remove a certain noise, it is necessary to increase the capacity of an external capacitor to be connected. Therefore, the number of external components increases, which is not a very preferable measure.

[0008]

According to the present invention, there is provided a key scan signal generating circuit for starting transmission of a key scan signal to a key matrix in response to a scan start signal and outputting a standby signal after the transmission, and a key matrix output circuit. A shaping circuit for shaping a signal, a key scan control circuit for judging an output signal of the shaping circuit and outputting the key scan start signal, and generating key data by decoding the key scan signal and an output signal of the shaping circuit A key scan circuit comprising: a first inverter having a low driving capability; a pull-down resistor or a pull-up resistor connected to an input side of the first inverter; Characterized by comprising a small-capacitance element connected to the output side of the inverter and an inverter for waveform shaping To.

In the present invention, the first inverter having a small driving capability and the small capacitive element connected to the output side of the first inverter cause the pulse waveform of noise or the like to be rounded. The effect is no longer transmitted to the output, thus preventing the generation of a key scan signal when no key is pressed.

[0010]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.
Is the same as the conventional configuration shown in FIG.
The configuration of 10e is different. Each of the signal shaping circuits 10a to 10e in the present embodiment, as shown in FIG.
The first inverter 100, which is constituted by a two-stage inverter and receives the input signal KM, is constituted by an inverter having a small driving ability, and has a pull-down resistor 1 on its input side as in the conventional case.
10 are connected. Further, a capacitance element 120 having a very small capacitance is connected between the output line of the first inverter 100 and the ground potential, and thereafter a second inverter 130 for waveform shaping is connected. Specifically, the first inverter 100 is formed by cascade-connecting a P-channel transistor 101 and an N-channel transistor 102 between power supply potentials. Inverter has been realized.

Therefore, when no key is pressed, the signal KM is not output from the key matrix 4, so that the first
The input Vin of the inverter 100 is a pull-down resistor 110
As a result, the output Vc becomes H level, and the capacitor 120 is charged. In this state, when a pulse-like noise A is input as shown in FIG. 3A, the N-channel transistor 102 of the first inverter 100 is turned on.
Even if the capacitance C of the capacitance element 120 is small, the time constant CR has a certain magnitude, and therefore, the output Vc of the first inverter 100 gradually decreases as shown in FIG. In the case of noise or the like, since the pulse width is very narrow, the output Vc is equal to the threshold level V of the second inverter 130.
Before reaching t, the output Vc stops decreasing and returns to the original H level again.
Return to level state. Therefore, even if the output Vc is input to the second inverter 130, the output Vout is not affected by pulse noise at all as shown in FIG.

As described above, in the state where the key is not pressed, the signal shaping circuits 10a to 10e do not output the H-level output signals KT1 to KT5 even if noise is input. Does not generate the scan start signal ST, and does not output the key scan signals KS1 to KS5. On the other hand, when any key of the key matrix 4 is pressed, a standby signal is output as an output signal through the pressed key as in the conventional case. For example, when the key 4a is pressed, an H-level output signal is output. KM5 is input to the signal shaping circuit 10e via the input terminal 5e.
In the signal shaping circuit 10e, although the edge of the input signal KM5 becomes round according to the time constant CR, the signal KM5 maintains the H level until the key scan is started.
The output Vc falls below the threshold level of the second inverter 130. Therefore, the second inverter 130 at the next stage is driven by the output Vc, and the output Vou
At t, an H level signal KT5 is generated.

When the signal KT5 is output, the key scan control circuit 11 sends a scan start signal ST to the key scan signal generation circuit 1, thereby starting to send the key scan signals KS1 to KS5. At the time of the key scan operation, a key scan signal KS1 having a sufficient pulse width shown in FIG.
Is input as
An L level signal is generated at the output of the inverter 100,
This signal allows the output Vout of the second inverter 130 to be output.
Becomes H level. Thereafter, key data corresponding to the pressed key is generated by the key scan decoder circuit 12 and stored in the key data storage circuit 8 as in the conventional example. Thus, when a key is pressed, the signal shaping circuit shown in FIG. 2 has no adverse effect.

As described above, the original function of performing key scan only when a key is pressed can be reliably satisfied. By the way, in the above-described embodiment, the configuration in which the pull-down resistor 110 is connected to each input stage of the signal shaping circuits 10a to 10e is shown, but a pull-up resistor may be connected instead. In this case, when the key is not pressed, the output of the first inverter 100 is at the L level, and the capacitor 120 is in a discharging state. Therefore, when noise enters, the capacitor 120 performs a charging operation. Therefore, an inverter in which the ON resistance of the P-channel transistor 101 is increased may be used as the inverter 100 having a small driving ability.

When the signal shaping circuit shown in FIG. 2 is used,
Since the output logic level is inverted from that of the related art, the key scan control circuit 11 and the key scan decoder 12 are configured to input the inverted signal and perform the same operation as the related art.

[0016]

According to the present invention, it is possible to reliably prevent the key scan circuit from operating when the key is not pressed due to the influence of noise or the like. Therefore, the key scan is performed only when the key is pressed. By doing so, the original function of reducing power consumption can be satisfied. Moreover,
Therefore, it is not necessary to use external parts,
A key scan circuit that is extremely suitable for SI can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a signal shaping circuit according to the present invention.

FIG. 3 is a timing chart for explaining the operation of the signal shaping circuit according to the present invention.

FIG. 4 is a block diagram showing the entire configuration of a conventional example.

FIG. 5 is a timing chart showing a key scan signal.

FIG. 6 is a circuit diagram showing a specific configuration of a conventional signal shaping circuit.

[Explanation of symbols]

 Reference Signs List 1 key scan signal generation circuit 4 key matrix 6a to 6e, 10a to 10e signal shaping circuit 7, 12 key scan decoder circuit 9, 11 key scan control circuit 61, waveform shaping inverter 62, 110 pull-down resistor 100 first inverter 101P Channel transistor 102 N-channel transistor 120 Capacitance element 130 Second inverter

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 3/023

Claims (2)

(57) [Claims] 1. A key scan signal generation circuit for starting transmission of a key scan signal to a key matrix in response to a scan start signal and outputting a standby signal after transmission, a shaping circuit for shaping an output signal of the key matrix, A key scan control circuit that determines an output signal of the shaping circuit and outputs the key scan start signal; and a key circuit that decodes the key scan signal and the output signal of the shaping circuit to generate key data. In the scan circuit, the shaping circuit includes: a first inverter; a pull-down resistor or a pull-up resistor connected to an input side of the first inverter; a capacitive element connected to an output side of the first inverter; An inverter for waveform shaping, based on a capacitance value of the capacitive element and an on-resistance value of the first inverter. Constants, is input to the first inverter
The capacitive element discharges or discharges in response to the pulsed noise.
Is an output of the first inverter when a charging operation is performed.
Voltage is the threshold of the waveform shaping inverter
The value is set so as not to reach the level, and the capacitance value of the capacitive element and the ON state of the first inverter are set.
A key scan circuit , wherein a resistance value is set to a value corresponding to the time constant . 2. When a pull-down resistor is connected to the input side of the first inverter, the pull-down resistor must be connected to the first inverter so that the time constant is obtained.
Increasing the on-resistance of the N-channel transistor constituting the first inverter in accordance with the capacitance value of the storage element ;
When connecting a pull-up resistor, the above time constant will be used.
2. The key scan circuit according to claim 1, wherein the on-resistance of the P-channel transistor forming the first inverter is increased in accordance with the capacitance value of the capacitance element .