JP3024036B2 - Output buffer circuit of semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit included in a semiconductor memory device, and more particularly to an output buffer circuit for outputting stored data read from a memory cell to the outside.

[0002]

2. Description of the Related Art Normally, a capacitive load such as a TTL (Transistor Transistor Logic) circuit is connected to an output terminal of a semiconductor memory device. Therefore, when the switching transistor of the output buffer circuit is turned on, when the output signal is inverted, a large charging / discharging current flows instantaneously to the power supply line and the ground line inside the semiconductor memory device. However, since these power lines and ground lines have parasitic inductance due to wire bonding and the like, when such a charge / discharge current flows, power supply noise and ground noise proportional to the magnitude of the change in current occur, This causes a malfunction of the semiconductor memory device.

However, if the driving capability of the switching transistor of the output buffer circuit is reduced, it is possible to suppress a sudden large charge / discharge current from flowing.
It is possible to reduce these noises. However, reducing the driving capability of the switching transistor requires a long time for signal output,
Contrary to recent demands for speeding up of semiconductor memory devices. Therefore, an output buffer circuit capable of reducing power supply noise and ground noise without deteriorating the speed of signal output has been developed by making various efforts.

FIG. 7 shows a configuration example of an output buffer circuit of a conventional semiconductor memory device having the above-described noise reduction effect. This output buffer circuit has two types of buffer circuits 11, 12
It has.

One buffer circuit 11 includes an N-channel MOS [Metal-Oxide-Semiconductor] • FET [Field Ef].
defective transistor] and a PMOS transistor Q22 composed of a P-channel MOS • FET. These MOS transistors Q21 and Q22 have their gate terminals connected together to form an input of the buffer circuit 11, and their source terminals connected together to form an output of the buffer circuit 11. The drain terminal of the NMOS transistor Q21 is connected to the VCC power supply, and the drain terminal of the PMOS transistor Q22 is grounded. Therefore, when an H level (power supply voltage VCC) is input, the buffer circuit 11
When the MOS transistor Q21 is turned on, the power supply voltage VCC
From the threshold voltage VTH of this NMOS transistor Q21.
When a low voltage is output as an H level and an L level (ground potential) is input, the PMOS transistor Q22 is turned on and a voltage higher than the ground voltage by the threshold voltage VTH of the PMOS transistor Q22. Is output as L level.

The other buffer circuit 12 also has a PMOS transistor Q23 comprising a P-channel MOS.
And an NMOS transistor Q24 comprising a channel MOSFET. However, this buffer circuit 12 is a normal CMOS inverter,
The gate terminals of the MOS transistors Q23 and Q24 are connected to form an input of the buffer circuit 12, and the drain terminals are connected to form an output of the buffer circuit 12. The source terminal of the PMOS transistor Q24 is connected to the VCC power source, and the NMOS transistor Q23
Are grounded. Accordingly, when the H level is input, the NMOS transistor Q24 is turned ON, so that the buffer circuit 12 outputs the L level of the ground potential. When the L level is input, the PMOS transistor Q23 is turned ON. Output the H level of the power supply voltage VCC.

The storage data read out by the internal circuit 13 of the semiconductor memory device is input directly to one buffer circuit 11 and inverted by an inverter circuit 14 and input to the other buffer circuit 12. . Outputs of these buffer circuits 11 and 12 are commonly connected to an output terminal 15 of the semiconductor memory device.

The stored data input to the conventional output buffer circuit having the above configuration changes from H level to L level, and then to H level again.
The operation at the time of switching to the level will be described with reference to FIG. When the input signal changes at time t21 and the storage data output from the internal circuit 13 switches from H level to L level at time t22, the output of the buffer circuit 11 changes from the H level of the voltage VCC-VTH to the voltage VTH. Switch to L level. The output of the inverter circuit 14 is at time t
At a time t23, which is a little later than the time t22, the level is switched to the H level.
The level is switched from the level to the L level of the ground potential. Therefore, when the output terminal 15 switches from the H level to the L level, at time t22, the power supply voltage VCC is temporarily switched from the H level to the L level of the voltage VTH, and the inverter circuit 14
At the time t23 after the elapse of the delay time, the L level of the ground potential is determined.

When the input signal changes again at time t24 and the storage data output from internal circuit 13 switches to H level at time t25, the output of buffer circuit 11 changes to H level of voltage VCC-VTH. Return. The output of the inverter circuit 14 is at time t25, which is slightly delayed from time t25.
26, the output of the buffer circuit 12 returns to the H level of the power supply voltage VCC. Therefore, when the output terminal 15 switches from the L level to the H level, at time t25, the output terminal 15 switches from the L level of the ground potential to the H level of the voltage VCC-VTH once, and the inverter circuit 1
At time t26 after the elapse of the delay time 4, the H level of the power supply voltage VCC is determined.

Therefore, in the conventional output buffer circuit shown in FIG. 7, the voltage at the output terminal 15 changes stepwise by the threshold voltage VTH, so that the charge / discharge current of the load circuit can also be abruptly reduced. As a result, power supply noise and ground noise can be reduced.

[0011]

However, the above MOS
Since the threshold voltage VTH of the transistors Q21 and Q22 is relatively small as compared with the potential difference between the power supply voltage VCC and the ground potential, the voltage change at the output terminal 15 is only slightly reduced in a stepwise manner. Further, if the delay time of the inverter circuit 14 becomes longer, the speeding up of the signal output is hindered, so that the period (t23-t22, t26-t25) in which the voltage change at the output terminal 15 is reduced is short. I have no choice.

For this reason, the conventional output buffer circuit has a problem that the effect of reducing noise is insufficient because the change in the voltage at the output terminal 15 is alleviated in only a few steps in a short time.

The present invention has been made in view of the above circumstances, and provides a sufficient noise reduction effect by outputting an intermediate level voltage to an output terminal before outputting a new output signal. It is an object of the present invention to provide an output buffer circuit of a semiconductor memory device that can be obtained.

[0014]

SUMMARY OF THE INVENTION An output buffer circuit according to the present invention is an output buffer circuit of a semiconductor memory device for outputting output data such as storage data read from a memory cell and an internally generated control signal to an output terminal. An output preparation period detecting means for detecting an output preparation period from a time before the start of the output of the new output signal to a start of the output of the new output signal, and a logic of the output signal output from the output terminal An intermediate level generating means for generating an intermediate level voltage between a high level and a low level in amplitude, and a single buffer circuit provided in the output preparation period detected by the output preparation period detecting means.
The intermediate level voltage is applied to the
During the period other than the high level
And output control means for applying the low-level voltage, thereby achieving the above object.

[0015] In one embodiment, the output preparation period starts when the input signal transmitted to the semiconductor memory device changes.

In one embodiment, the intermediate level is half the sum of the high level and the low level in the logic amplitude.

In one embodiment, the intermediate level generating means is constituted by a circuit using a back threshold effect, and the intermediate level is determined by a threshold value caused by the back threshold effect of a transistor present in the circuit. It is the sum of the voltages or the value obtained by subtracting the sum of the threshold voltages from the high level in the logic amplitude.

[0018]

When the output is permitted, the output buffer circuit normally outputs an output signal such as storage data read from a memory cell or an internally generated control signal to an output terminal. However, the output buffer circuit of the present invention outputs an intermediate-level voltage to an output terminal before outputting a new output signal.

That is, the output preparation period detection circuit detects an output preparation period from just before outputting a new output signal to starting output of this output signal. When a semiconductor memory device reads and outputs stored data from a memory cell in response to an external read request, this read operation requires a certain amount of time. Also, when outputting a control signal,
Often based on external access made a while ago. Therefore, when a new output signal is output, it is usually possible to detect this in advance. In the case of outputting the read stored data, in the read mode, for example, an internal control signal for detecting that the input signal has changed is issued, and a certain period of time is elapsed after the internal control signal is issued. It can be detected as a preparation period.

The intermediate level generating circuit generates a high or low intermediate level voltage in the logic amplitude of the output signal. This intermediate level generating circuit is configured as a bidirectional power supply circuit that can be displaced to an intermediate level regardless of whether the logic level of the immediately preceding output terminal is high or low. A charging power supply circuit that can be displaced to an intermediate level by supplying a charging current; and a discharge power supply circuit that can be displaced to an intermediate level by discharging a discharging current when the immediately preceding output terminal is at an H level. It can also be constituted by a combination.

The output control circuit outputs the intermediate level voltage generated by the intermediate level generating circuit to the output terminal in place of the original output signal during the output preparation period detected by the output preparation period detection circuit. However, at this time, if the intermediate level generating circuit is a combination of the charging power supply circuit and the discharging power supply circuit, one of the power supply circuits is switched according to the logic level of the output signal output to the output terminal immediately before. You have to choose.

As a result, according to the configuration of the present invention, before a new output signal is output to the output terminal, this output terminal is set to the intermediate level voltage, so that the new output signal becomes H level and L level. In any of the levels, the potential difference at the start of output is always sufficiently smaller than the entire logical amplitude. Therefore, the output current can be greatly reduced as compared with the case where the output signal inverts the logic amplitude in full swing, so that the change in this current is also small, so that power supply noise and ground noise can be reduced. Become. Further, since the potential difference at the start of the output is small, the time required for charging and discharging the load connected to the output terminal is also shortened, which can contribute to a high-speed signal output.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings.

1 to 4 show a first embodiment of the present invention. FIG. 1 is a circuit block diagram of an output buffer circuit, FIG. 2 is a time chart showing the operation of the output buffer circuit, and FIG. FIG. 4 is a time chart showing the transient characteristics of the charging voltage of the load capacitance.

In this embodiment, an output buffer circuit for outputting storage data read from a memory cell of a semiconductor memory device to the outside will be described. In this semiconductor memory device, storage data read from a memory cell is transferred to two data signal lines DATA and data signal lines D drawn from an internal circuit 1.
The inverted data signals are output to the ATA bar in a balanced manner. The data signal is amplified by a sense amplifier circuit 2 having two data signal lines DATA and DATA bar as differential inputs, and sent to a buffer circuit 4 via a latch circuit 3. The latch circuit 3 is a flip-flop circuit in which inputs and outputs of two inverter circuits 3a and 3b are connected in a circulating manner, and can hold a data signal output from the sense amplifier circuit 2.

The buffer circuit 4 includes a P-channel MOS
This is a CMOS inverter constituted by a PMOS transistor Q1 composed of an FET and an NMOS transistor Q2 composed of an N-channel MOSFET.
The gate terminals of the transistors Q1 and Q2 are connected to each other and connected to the output of the latch circuit 3, and the drain terminals are connected to each other and connected to the output terminal 5 of the semiconductor memory device. Further, the source terminal of the PMOS transistor Q1 is connected to the VCC power supply through the drain-source terminal of the PMOS transistor Q3 of the output control circuit 6, and NM
The source terminal of the OS transistor Q2 is grounded via the drain-source terminal of the NMOS transistor Q4 of the same output control circuit 6.

Therefore, the data signal read from the memory cell and output from the internal circuit 1 is applied to the sense amplifier circuit 2
, And is held in the latch circuit 3, inverted by the buffer circuit 4, and output to the outside via the output terminal 5. However, this buffer circuit 4 is used as the latch circuit 3
Is output only when the MOS transistors Q3 and Q4 of the output control circuit 6 are ON.

The two data signal lines DATA and DAT
A bar is connected to the VCC power supply through the drain-source terminals of the PMOS transistors Q5 and Q6 of the output preparation period detection circuit 7, respectively. These PMOS transistors Q5 and Q6 are both composed of P-channel MOS FETs, and the input signal change detection signal A output from the internal circuit 1 is output.
TD is commonly input to the gate terminal. The input signal change detection signal ATD is a signal that temporarily goes low when the internal circuit 1 detects a change in the input signal sent to the semiconductor memory device. Therefore, when the input signal changes and a new data signal starts to be output shortly thereafter, the input signal change detection signal A
When TD goes low, PMOS transistors Q5 and Q6
Is turned ON, the data signal lines DATA and DATA bar to which the inverted data signal is originally output are both pulled up to H level. Further, these two data signal lines DATA and DATA bar are similarly connected to the inputs of the exclusive OR circuit 7a of the output preparation period detection circuit 7, respectively. Exclusive OR circuit 7a
Is a logic circuit that outputs an H level when the logic levels of the two data signal lines DATA and DATA bar are different, and outputs an L level when they match. The output of the exclusive OR circuit 7a is inverted by the inverter circuit 7b and output from the output preparation period detection circuit 7.

The output of the output preparation period detection circuit 7 is sent to the output control circuit 6 and the intermediate level generation circuit 8. The intermediate level generating circuit 8 has a P-channel M
It has a PMOS transistor Q7 composed of an OS • FET and an NMOS transistor Q8 composed of an N-channel MOS • FET. The drain terminals of these MOS transistors Q7, Q8 are connected via a series circuit of two voltage dividing resistors R1, R2. Connected. These two voltage dividing resistors R1,
R2 have the same resistance value, and the voltage at the connection point between them is output from the intermediate level generation circuit 8. The output of the output preparation period detecting circuit 7 is directly connected to the gate terminal of the NMOS transistor Q8,
The gate terminal of the MOS transistor Q7 is connected via an inverter circuit 8a. The source terminal of the PMOS transistor Q7 is connected to the VCC power supply,
The source terminal of transistor Q8 is grounded. Therefore, when the output of the output preparation period detection circuit 7 is at the H level, the intermediate level
7 and Q8 are turned ON, and the power supply voltage VCC is divided by the resistors R1 and R2 to output an intermediate level of the voltage (1/2) VCC. When the output of the output preparation period detection circuit 7 is L
Level, the MOS transistors Q7 and Q8
Since the output becomes F, the output becomes high impedance, and in this case, current does not flow through the voltage dividing resistors R1 and R2, thereby preventing wasteful increase in power consumption.

The output control circuit 6 connects the output of the output preparation period detection circuit 7 directly to the gate terminal of the PMOS transistor Q3 and to the gate terminal of the NMOS transistor Q4 via the inverter circuit 6a. It has become. These MOS transistors Q
3 and Q4 are each composed of a P-channel MOSFET and an N-channel MOSFET. The output control circuit 6 has two NMOS transistors Q9 and Q10 composed of N-channel MOS FETs. The output of the output preparation period detection circuit 7 is
9, and also connected to the gate terminal of Q10. The drain terminal of the NMOS transistor Q9 and the source terminal of the NMOS transistor Q10 are commonly connected to the output of the intermediate level generation circuit 8. And the NMOS transistor Q
The source terminal 9 is connected to the source terminal of the PMOS transistor Q1 in the buffer circuit 4, and the drain terminal of the NMOS transistor Q10 is connected to the source terminal of the NMOS transistor Q2 in the same buffer circuit 4. Therefore, when the output of the output preparation period detecting circuit 7 is at the L level, the output control circuit 6 turns on the MOS transistors Q3 and Q4 and turns off the NMOS transistors Q9 and Q10.
It becomes an FF and causes the buffer circuit 4 to output the data signal. When the output of the output preparation period detecting circuit 7 changes to the H level, the MOS transistors Q3 and Q4 are turned off.
F, the NMOS transistors Q9 and Q10 are turned ON, and the voltage (1/1) generated by the intermediate level generation circuit 8 as described above.
2) Supply the intermediate level of Vcc to the buffer circuit 4 as power. Therefore, the buffer circuit 4 outputs an intermediate level of this voltage (1/2) VCC to the output terminal 5 regardless of the logical level output from the latch circuit 3.

The output terminal 5 of the output buffer circuit having the above configuration
Will be described with reference to FIG. 2 when the signal is switched from L level to H level again to L level.

At the first point in the drawing, the internal circuit 1 outputs an L level to the data signal line DATA and outputs an H level to the data signal line DATA bar, and the latch circuit 3 outputs an H level. 5 is at the L level. Then, when the input signal changes at time t1, the input signal change detection signal ATD is temporarily switched to the L level, and the data signal lines DATA and DATA are both at the H level. 7
Is switched to H level. Then, the point A in FIG. 1 serving as the source terminal of the PMOS transistor Q1 in the buffer circuit 4 and the point B shown in FIG. 1 serving as the source terminal of the NMOS transistor Q2 are output by the H level output of the output preparation period detection circuit 7. Since the power is supplied from the driven intermediate level generating circuit 8 to the intermediate level of the voltage (1/2) Vcc and the output of the latch circuit 3 is also switched to the L level, the current from the intermediate level generating circuit 8 becomes NMO.
The current flows to the output terminal 5 via the S transistor Q9 and the PMOS transistor Q1, and the output terminal 5 changes from the L level to an intermediate level of the voltage (1/2) VCC.

At a subsequent time t2, a new data signal read by the previous input signal is output from the internal circuit 1. In this case, the data signal line DATA bar switches to the L level, and the output preparation period The output of the detection circuit 7 also returns to the L level. Then, the points A and B also return to the original H level and L level, respectively, so that the buffer circuit 4 performs a normal inverter operation according to the new data signal latched by the latch circuit 3, and the output terminal 5 outputs the voltage. (1/2)
The level changes from the intermediate level of VCC to the H level.

When the input signal changes again at time t3, the input signal change detection signal ATD is temporarily switched to the L level, and the data signal lines DATA and DA are accordingly changed.
Since both TA bars are at the H level, the output of the output preparation period detection circuit 7 switches to the H level. Then, the points A and B become the intermediate level of the voltage (1/2) VCC, and
Since the output of the latch circuit 3 is switched to the H level, the current from the output terminal 5 changes to the NMOS transistors Q2 and NM
Intermediate level generation circuit 8 via OS transistor Q10
Flows from the H level to the voltage (1 /
2) Change to an intermediate level of VCC. Then, at the subsequent time t4, a new data signal is output from the internal circuit 1. In this case, the data signal line DATA switches to the L level, and the output of the output preparation period detection circuit 7 also returns to the L level. , A and B also return to the original H level and L level, respectively, so that the buffer circuit 4 performs a normal inverter operation according to the new data signal latched by the latch circuit 3, and the output terminal 5 outputs the voltage ( 1/2) VCC changes from the intermediate level to the L level.

As a result, according to this embodiment, the voltage of the output terminal 5 of the output buffer circuit changes stepwise by half of the power supply voltage VCC, requiring a relatively long output preparation period T shown in FIG. Therefore, a sudden change in the charge / discharge current of the load circuit can be greatly reduced, and power supply noise and ground noise can be reduced. Moreover, the output preparation period detection circuit 7
Detects in advance that a new data signal is to be output, and outputs an intermediate level to the output terminal 5, so that normal output is performed at time t2 or time t4, which is the time at which the output of the original data signal starts. And without sacrificing high-speed signal output. Here, a load circuit of the semiconductor memory device of the present embodiment is shown in FIG. Normally, a capacitive load such as a TTL circuit is connected to the output terminal 5 of the semiconductor memory device 10. Therefore, this load circuit can be considered as an equivalent circuit including a resistor R and a capacitor C as shown in the figure. . Then, the output terminal 5 changes from the ground potential (L level) to the power supply voltage VCC (H
Level), the electric charge q shown in Equation 1 flows into the capacitor C as a charging current,

[0036]

(Equation 1)

At this time, the voltage vA of the capacitor C is q = CvA
Is expressed by the following equation (2).

[0038]

(Equation 2)

Similarly, the voltage vB of the capacitor C when the output terminal 5 changes from the intermediate level of the voltage (1/2) VCC to the power supply voltage VCC is expressed by the following equation (3).

[0040]

(Equation 3)

The time constants of these voltages vA and vB match. FIG. 4 shows the transient characteristics of these voltages vA and vB.

The time tA until the voltage vA reaches the H-level threshold voltage VH (VH <VCC) on the load circuit side.
(Time tA when the time when the output terminal 5 switches to the H level is set to 0) First, the voltage vA (t) in Expression 2 is replaced with the threshold voltage VH and transformed to obtain the expression in Expression 4. Is done.

[0043]

(Equation 4)

The time tB required for the voltage vB to reach the threshold voltage VH is also expressed by the following equation (5).

[0045]

(Equation 5)

Comparing Equations 4 and 5, the base e of the exponential function is a value larger than 1 and the antilogarithm is 0.
From the condition that the value is between 1 and 1, it can be seen that the time tB at which this antilog number is doubled is shorter than the time tA. It can be seen that the time tB when changing from the intermediate level of the voltage (1/2) VCC to the threshold voltage VH is shorter than the time tA when changing from the ground potential to the threshold voltage VH as shown in FIG. This is apparent from FIG.

Therefore, as in the present embodiment, when the voltage change at time t2 or time t4, which is the output start time of the original data signal, is reduced to half of the conventional level, the load circuit side is required to reach the same potential level. Since the time is also shortened, the speeding up of the signal output can be further promoted.

FIGS. 5 and 6 show a second embodiment of the present invention. FIG. 5 is a circuit block diagram of an output buffer circuit, and FIG. 6 is a time chart showing the operation of the output buffer circuit. Note that components having the same functions as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, the intermediate level generating circuit 8 in the output buffer circuit of the first embodiment is
A circuit using a back-threshold effect of an FET and a P-channel MOS FET.
That is, the intermediate level generating circuit 8 includes an NMOS transistor Q composed of three N-channel MOSFETs.
PMO consisting of 11-Q13 and P-channel MOS-FET
It comprises S transistors Q14 to Q16. NMO
The S transistors Q11 to Q13 have their gate terminals connected to their respective drain terminals, and have their source and drain terminals connected in series.
It is inserted between the drain terminal of the S transistor Q9 and the VCC power supply. Also, the PMOS transistors Q14 to Q14
16, each gate terminal is connected to each drain terminal, and a source-drain terminal is connected in series,
It is inserted between the source terminal of the NMOS transistor Q10 in the output control circuit 6 and the ground.

Therefore, the intermediate level generating circuit 8 generates V
The current from the CC power supply is applied to the NMOS transistors Q11 to Q13,
NMOS transistor Q9 and PMOS transistor Q1
When the voltage flows to the output terminal 5 via the terminal, a voltage obtained by subtracting three times the threshold voltage VTH of each of the NMOS transistors Q11 to Q13 from the power supply voltage VCC is output. When the current from the output terminal 5 flows to the ground via the PMOS transistor Q2, NMOS transistor Q10 and PMOS transistors Q14 to Q16,
The output voltage is three times the threshold voltage VTH of each of the PMOS transistors Q14 to Q16.

The output terminal 5 of the output buffer circuit having the above configuration
Will be described with reference to FIG. 6 when the signal is switched from L level to H level again to L level.

In this embodiment, substantially the same operation as in the first embodiment shown in FIG. 2 is performed. However, when the input signal changes at time t11, the current from intermediate level generation circuit 8 becomes NM
The current flows out to the output terminal 5 via the OS transistor Q9 and the PMOS transistor Q1, and the output terminal 5 which has been at the L level changes to the intermediate level of the voltage VCC-3VTH due to the back-threshold effect of the three NMOS transistors Q11 to Q13. I do. Further, after the output terminal 5 is changed from the intermediate level to the H level at the subsequent time t12,
When the input signal changes again, the current from the output terminal 5 changes to the NMOS transistor Q2 and the NMOS transistor Q1.
0, and flows into the intermediate level generating circuit 8, and the output terminal 5 which has been at the H level up to that point is connected to the PMOS transistor Q
Voltage 3VT by back threshold effect of 14 ~ Q16
It changes to an intermediate level of H. Then, at time t14
, The output terminal 5 is fixed from the intermediate level to the L level.

As a result, also in the case of the present embodiment, the voltage of the output terminal 5 of the output buffer circuit requires a relatively long output preparation period T and changes stepwise through an intermediate level.
Abrupt changes in the charge / discharge current of the load circuit can be greatly reduced, and power supply noise and ground noise can be reduced. In addition, since the voltage change at time t12 or time t14, which is the time at which the output of the original data signal is started, is greatly reduced as compared with the conventional case, it is possible to contribute to an increase in signal output speed.

[0054]

As is apparent from the above description, according to the output buffer circuit of the semiconductor memory device of the present invention, by setting the output terminal to an intermediate-level voltage in advance, the voltage at which the output signal switches is obtained. Since the difference can be reduced, the noise due to the output current at this time can be reduced, and the signal output can be speeded up.

[Brief description of the drawings]

FIG. 1, showing a first embodiment of the present invention, is a circuit block diagram of an output buffer circuit.

FIG. 2 is a time chart showing the operation of the output buffer circuit according to the first embodiment of the present invention.

FIG. 3, showing the first embodiment of the present invention, is an equivalent circuit diagram of a load circuit.

FIG. 4 is a time chart showing the first embodiment of the present invention and showing a transient characteristic of a charging voltage of a load capacitance.

FIG. 5 shows a second embodiment of the present invention and is a circuit block diagram of an output buffer circuit.

FIG. 6 is a time chart showing the operation of the output buffer circuit according to the second embodiment of the present invention.

FIG. 7 shows a conventional example, and is a circuit block diagram of an output buffer circuit.

FIG. 8 shows a conventional example, and is a time chart illustrating an operation of an output buffer circuit.

[Explanation of symbols]

 5 output terminal 6 output control circuit 7 output preparation period detection circuit 8 intermediate level generation circuit

Claims (4)

(57) [Claims] An output buffer circuit of a semiconductor memory device for outputting an output signal such as storage data read from a memory cell and an internally generated control signal to an output terminal, and before output of a new output signal is started. Output preparation period detection means for detecting an output preparation period from the time point to the output start time point of the new output signal; and an intermediate level voltage between a high level and a low level in the logic amplitude of the output signal output from the output terminal. An intermediate level generating means for generating the output preparation period, and the output preparation period detected by the output preparation period detecting means,
Apply the intermediate level voltage to the terminal of the single buffer circuit
And, in a period other than the output preparation period, the end of the single buffer circuit
An output buffer circuit for a semiconductor memory device, comprising: output control means for applying the high-level voltage and the low-level voltage to the element. 2. The output buffer circuit of a semiconductor device according to claim 1, wherein said output preparation period starts when an input signal transmitted to said semiconductor memory device changes. 3. The intermediate level is half the sum of the high level and the low level at the logic amplitude.
An output buffer circuit of the semiconductor device according to claim 1. 4. The intermediate level generating means comprises a circuit using a back-threshold effect, wherein the intermediate level is a sum of threshold voltages of the transistors present in the circuit due to the back-threshold effect. 2. The output buffer circuit according to claim 1, wherein the output buffer circuit is a value or a value obtained by subtracting a total value of the threshold voltage from the high level in the logic amplitude.