JP3356660B2 - Method and system for analyzing structural warpage using finite element method, recording medium storing program for analyzing structural warpage using finite element method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a warping state analysis method for analyzing a warping state generated when a load such as heat or weight is applied to a structure such as a semiconductor device by using a finite element method analysis. About the system.

[0002]

2. Description of the Related Art A semiconductor chip is bonded to various materials and components in a manufacturing process of a semiconductor device and is affected by a change in temperature. Therefore, various warpages occur in the semiconductor chip depending on the thermal expansion coefficient and rigidity of the material to be joined and the thickness and width of the semiconductor chip itself. But,
Since a semiconductor chip in a final product state needs to be finished so as to have almost no warp, it is indispensable to know the warp state of the semiconductor chip in manufacturing a semiconductor device.

[0003] Therefore, as one of the methods for knowing the state of warpage of a semiconductor chip, there is a method of measuring the amount of warpage by applying a measuring device horizontally to the surface of the semiconductor chip.

FIG. 15 is a schematic diagram for explaining a conventional method for measuring the amount of warpage of a semiconductor chip. As shown in FIG. 15, a semiconductor chip 101 in a semiconductor device (not shown) warps due to the effect of a temperature change when joined to another material or component. In the conventional measuring method shown in FIG. 15, first, a measuring instrument 10 is placed on the surface of a semiconductor chip 101.
2 are abutted horizontally, and the height h of the semiconductor chip 101 is measured. Next, the measured height h and the semiconductor chip 101
By calculating the difference from the known thickness t, the warpage amount δ at the end portion 101a of the semiconductor chip 101 can be obtained. In the conventional measuring method, the semiconductor chip 10
It is determined that the larger the value of the amount of warpage δ is, the greater the degree of warping is.

However, even if the amount of warpage δ is the same, if the width L of the semiconductor chip is different, the stress and strain acting on the semiconductor chip 101 are different, so that the warped state of the semiconductor chip 101 is different. Similarly, even if the stress and strain acting on the semiconductor chip 101 are the same,
The amount of warpage δ of the end portion 101a of the semiconductor chip 101 differs depending on the width L of the semiconductor chip 101.

FIG. 16 is a graph showing measurement results obtained by the above-described conventional warpage amount measuring method. The measurement results shown in FIG. 16 were obtained by measuring the amount of warpage δ at the end of the semiconductor chip when a plurality of semiconductor chips having different widths L were used and the stress acting on the semiconductor chip was kept constant. Things. As can be seen from FIG. 16, the larger the width L of the semiconductor chip, the larger the warpage δ of the semiconductor chip. Therefore, even if only the warpage amount δ is measured without considering the width L of the semiconductor chip as in the above-described conventional measuring method, the warped state of the semiconductor chip cannot be known accurately.

For this reason, the radius of curvature is often used as a numerical value representing the state of warpage of a structure, not limited to the field of semiconductor devices. For example, Japanese Patent Application Laid-Open No. 4-198823 discloses a method in which the radius of curvature of a thin sheet warped by plastic working is used for measuring the residual stress of the thin sheet. In this measurement method, a thin plate is removed to a predetermined depth using a dissolving agent such as ferric chloride, and a radius of curvature of a warped surface generated in the thin plate is obtained based on residual stress. In addition,
In this publication, the method of calculating the radius of curvature of the warped surface is not specified, but the radius of curvature is calculated by measuring the distance to the warped surface of the thin plate using laser, eddy current, ultrasonic waves, or the like. In addition, Japanese Patent Application Laid-Open No. Hei 3-242531 discloses a method of measuring the amount of warpage of a sample composed of a substrate and a thin film using an interferometer or a laser displacement meter to measure the elastic modulus of the thin film.

As described above, conventionally, the radius of curvature is obtained by some method based on the measurement result of the amount of warpage of a structure,
A method of calculating the residual stress and the elastic modulus based on the radius of curvature has been adopted. Note that there is an inverse relationship between the stress acting on the structure and the radius of curvature, and the value of the radius of curvature does not depend on the width of the structure.

[0009]

However, in the above-mentioned conventional measuring method, the radius of curvature is calculated on the basis of the measurement result, so that a manufactured structure is first required. In order to design and determine the optimal dimensions and materials, it is necessary to repeat manufacturing and measurement.Especially, in semiconductor devices that use many materials and components and have a complicated structure, a great deal of time is required before product development. There was a problem that it took a lot of cost and time.

The curvature radius and the warped state are in an inverse relationship that the larger the radius of curvature is, the smaller the curvature is, and the smaller the radius of curvature is, the larger the warpage is. A sensory shift occurs. For this reason, when the radius of curvature is used as a numerical value representing the state of warpage, there is a problem that confusion often occurs at the design site.

Accordingly, the present invention provides a method of designing the dimensions and materials of a structure optimally from the beginning to reduce the cost and time of product development, and to prevent warpage occurring in the structure without causing confusion at the design site. It is an object of the present invention to provide a method and a system for analyzing a state of warpage of a structure using a finite element method, which can analyze the structure before manufacturing the structure.

[0012]

In order to achieve the above object, a method for analyzing the state of warpage of a structure according to the present invention comprises the steps of: preparing an analysis model of a structure to be analyzed; Performing a finite element method analysis of the analysis model under analysis conditions to be obtained, and detecting a displacement amount of the analysis target point due to a warp occurring in the analysis model, and a displacement of the detected analysis target point. Calculating the curvature of the warpage generated in the analysis model from the amount.

Further, a step of performing a finite element method analysis of the analysis model by changing the analysis conditions to detect a displacement amount of the analysis target point and a step of calculating a curvature of a warp generated in the analysis model are repeated. And a step of graphing the relationship between the analysis condition and the curvature.

In the method for analyzing a warped state of a semiconductor chip according to the present invention, a step of creating an analysis model of a semiconductor chip to be analyzed is performed; A finite element method analysis of the model is performed, and two points of a center part and an end part or arbitrary points are used as the analysis target points when the analysis model is warped.
Detecting the coordinates of the three points and calculating the curvature of the warpage generated in the analysis model from the detected coordinates of the analysis target point.

Further, a step of performing a finite element method analysis of the analysis model while changing the analysis conditions to detect coordinates of the analysis target point in an arbitrary coordinate system, and a step of calculating a curvature of a warp generated in the analysis model May be repeated to graph the relationship between the analysis condition and the curvature.

Further, the structure warping state analysis system of the present invention comprises an analysis model creating means for creating an analysis model of a structure to be analyzed, and a finite element method analysis of the analysis model according to given analysis conditions. Performing a finite element method analysis means for acquiring a deformation state of the analysis model under the analysis conditions, and an analysis object defined in the analysis model among the analysis models deformed as a result of performing the finite element analysis. Displacement detection means for detecting a displacement of a point or coordinates of the analysis target point in an arbitrary coordinate system, and a displacement generated in the analysis model based on the detected displacement of the analysis target point or coordinates in the arbitrary coordinate system. And a curvature calculator for calculating the curvature of the warpage.

Further, the apparatus may be provided with a graph creating means for graphing the relationship between the analysis condition and the curvature.

Further, the analysis target points may be two points defined at a center part and an end part of the analysis model, and the analysis target points may be three points arbitrarily defined in the analysis model. May be adopted.

The recording medium on which the program for analyzing the state of warpage of a structure of the present invention is recorded includes a procedure for creating an analysis model of a structure to be analyzed, an analysis target point defined in the analysis model, and an analysis target to be obtained. Performing a finite element method analysis of the analysis model under the conditions, detecting a displacement amount of the analysis target point at which the analysis model is warped and displaced under the analysis conditions, and the detected analysis target point Calculating the curvature of the warpage generated in the analysis model from the displacement amount of the computer.

Further, the recording medium on which the program for analyzing the state of warpage of a structure of the present invention is recorded includes a procedure for preparing an analysis model of the structure to be analyzed, an analysis target point defined in the analysis model, and an analysis to be obtained. Performing a finite element method analysis of the analysis model under the conditions, detecting the coordinates in the arbitrary coordinate system of the analysis target point that is displaced due to the warpage of the analysis model under the analysis conditions; and Calculating the curvature of the warpage generated in the analysis model from the coordinates of the analysis target point.

According to the present invention configured as described above, the warping state occurring in the structure is analyzed before the structure is manufactured, and the dimensions and materials of the structure are optimally designed from the beginning to reduce the cost of product development. And time can be reduced. Further, by using the curvature as a parameter of the warp state of the structure, the warp state of the structure can be known as it is from the value of the curvature value, thereby preventing confusion at the design site.

[0022]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a structure warping state analysis system (hereinafter, referred to as “analysis system”) using the finite element method of the present invention.

As shown in FIG. 1, the analysis system includes an analysis processing device 1 for analyzing a warped state of a structure using a finite element method, and an input device 2 for inputting various condition data to the analysis processing device 1. And a display device 3 for displaying an analysis result by the analysis processing device 1.

The analysis processing device 1 includes an analysis model creating means 4 for creating an analysis model as an analysis target based on the structure data input from the input device 2, and a finite deformation state of the analysis model under a certain analysis condition. A finite element method analysis means 5 for analyzing using an element method, a displacement detection means 6 for detecting a displacement amount or coordinates of an analysis target point defined in the analysis model, and a displacement amount of the analysis model detected by the displacement detection means 6 A curvature calculation means 7 for calculating the curvature of the analysis model from
It has a graph creating means 8 for graphing the relationship between the curvature of the analysis model and the analysis condition data. Analysis processing device 1
Is composed of information processing equipment such as a personal computer and a workstation. Further, the analysis model creating means 4, the finite element method breaking means 5, the displacement detecting means 6, the curvature calculating means 7, and the graph creating means 8 may have a configuration incorporated in the analysis processing device 1 in advance, or It may be realized by software installed in the analysis processing device 1. As the input device 2 for the designer to input various condition data to the analysis processing device 1, a keyboard, a mouse, or the like is used. The display device 3 displays a graph of the analysis result created by the graph creating means 7 of the analysis processing device 1, and uses a monitor, a printer, or the like.

Here, the finite element method analysis used in the present embodiment will be described.

The finite element method divides a structure (object to be analyzed) deformed by a load such as heat or load into a number of small areas (elements), and finitely determines the relationship between the force and displacement for each element. This is a method in which the solution is piecewise approximated by a function having an appropriate value and the entire deformation, strain distribution and stress distribution are obtained by numerical calculation. This finite element method analysis can determine the stress distribution, strain distribution, displacement, etc. of the structure under various conditions by changing parameters such as shape, dimensions, material constants, constraint conditions, load conditions, etc. Widely used in the field of strength design.

FIG. 2 is a flowchart showing a processing example of the analysis processing apparatus in the structural warpage state analysis system using the finite element method shown in FIG. Hereinafter, a method of analyzing a warped state of a structure using the present analysis system will be described with reference to FIGS. In this embodiment, a case where the semiconductor chip model 9 shown in FIG. 3 is used as an analysis model to be analyzed will be described as an example.

The designer activates the analysis processing device 1 when analyzing the warping state of a certain structure using the analysis system.

After the analysis processing apparatus 1 is started, the designer inputs the shape data and material constant data (thermal expansion coefficient, elastic constant, etc.) of the structure to be analyzed from the input device 2 to the analysis model creating means 4. (S1). When the structure data is input, the analysis model creation means 4 creates a semiconductor chip model 9 (see FIG. 3) as an analysis model to be analyzed based on the input structure data (S2). In addition,
The analysis model creation means 4 includes, together with the structure data, analysis condition data (displacement constraint conditions, materials and parts to be joined to the structure) when the warping state of the structure is analyzed by the finite element method analysis means 5. Temperature). The data of the semiconductor chip model 9 and the analysis condition data are transmitted from the analysis model creation means 4 to the finite element method analysis means 5.

Next, in the finite element method analysis means 5, based on the data of the semiconductor chip model 9 and the analysis condition data transmitted from the analysis model creation means 4, the warping state of the semiconductor chip model 9 is determined by the finite element method. Analysis is performed (S
3). From the result of the finite element method analysis, a deformation state of the semiconductor chip model 9 as shown in FIG. 4 is obtained. In the displacement detecting means 6, based on the deformed state of the semiconductor chip model 9, the displacement amounts δya, δx of the end 9a and the center 9b as the analysis target points defined in the semiconductor chip model 9.
a, δyo (see FIG. 4) are detected (S4) and transmitted to the curvature calculation means 7. Note that these displacement amounts δya, δxa,
Since δyo includes the amount of shrinkage of the semiconductor chip due to a change in temperature from the high temperature state at the time of joining materials and components to cooling to room temperature, the warped state of the semiconductor chip can be accurately obtained.

The curvature calculating means 7 calculates the curvature S of the deformed semiconductor chip model 9 using the following equation (1) (S5).

S = 2 (δya + δyo) / {(Lx / 2−δxa) ² + (δya + δyo) ² } (1) where δyo is the Y direction in the surface center 9 b of the semiconductor chip 9 (see FIG. 4). Δya is the semiconductor chip 9
Δxa is the displacement of the end 9a of the semiconductor chip 9 in the X direction (see FIG. 4),
Lx is the width of the semiconductor chip 9. Thus, a warped state occurring in a structure such as a semiconductor chip can be analyzed before the structure is manufactured.

The curvature S calculated by the curvature calculation means 7 is transmitted to the graph creation means 8. Each time the structure data or analysis condition data of the semiconductor chip model is changed, data input S1, analysis model creation S2, finite element analysis S
3. The displacement detection S4 and the curvature calculation S5 are repeated, and the relationship between the analysis conditions and the curvature is approximated to a multi-order function curve and graphed (S6).

The graph created by the graph creating means 8 is displayed on the display device 3. As a result, the relationship between the analysis condition parameters and the curvature can be easily obtained, and by selecting the optimal dimensions and materials of the structure such as a semiconductor chip based on the display result, the dimensions and the material of the structure can be changed from the beginning. It can be designed optimally, and the cost and time for product development can be reduced.

Next, using the displacement detecting means 6 of the warpage state analyzing apparatus shown in FIG. 1, the coordinates of the analysis target point defined on the structure in an arbitrary coordinate system are detected, and the curvature of the structure is determined from the coordinates. The case of obtaining is described.

The finite element method analysis means 5 shown in FIG. 1 can output a deformation state diagram of the semiconductor chip model 9 obtained as a result of the analysis from a printer (not shown). From the output deformation state diagram, the coordinates (Xo, Xo, end 9a) of the center 9b and the end 9a as the analysis target points on the surface of the semiconductor chip model 9 as shown in FIG.
Yo) and (Xa, Ya). Note that a digitizer or the like can be used as the displacement detection means 6 for taking in the coordinates of each part from the deformation state diagram. Further, a deformation state diagram of the semiconductor chip model 9 obtained as a result of the analysis is directly displayed on a monitor (not shown), or a deformation state diagram output from a printer is read by an image scanner and displayed on a monitor, and a mouse ( The coordinates of the end portion 9a and the center portion 9b of the semiconductor chip model 9 may be acquired by using (not shown) or the like.

The coordinates of the end 9a and the center 9b of the semiconductor chip model 9 captured by the displacement detecting means 6 are transmitted to the curvature calculating means 7, and the curvature S of the deformed semiconductor chip model 9 is calculated by the following equation (2). ).

S = 2 (Ya−Yo) / {(Xa−Xo) ² + (Ya−Yo) ² } Equation (2) where Xo is the surface central portion 9 b of the semiconductor chip model 9.
(See FIG. 5), Yo is the Y coordinate of the surface central portion 9b of the semiconductor chip model 9 (see FIG. 5), Xa is the X coordinate of the end 9a of the semiconductor chip model 9, and Ya is the semiconductor chip model 9. This is the Y coordinate of the end 9a.

In the above description, a case has been described in which the coordinates of two points at the end 9a and the center 9b on the surface of the semiconductor chip model 9 are fetched and the curvature of the deformed semiconductor chip model 9 is calculated. 3 arbitrary points (P1, P2, P3) on the surface of the semiconductor chip model 9 shown in FIG.
And the curvature S can be calculated. In this case, the curvature calculating means 6 calculates the curvature S according to the following equation (3).

[0041] S = 2 {(X1 (Y2 -Y3) + X2 (Y3-Y1) + X3 (Y1-Y2)} / [{(X1-X2) 2 + (Y1-Y2) 2} * {(X2-X3 ) ² + (Y ² −Y 3) ² ｝ * {(X 3 −X 1) ² + (Y 3 −Y 1) ² }] ^0.5 (3) where X 1 is P 1 on the surface of the semiconductor chip model 9.
X1, Y1 is the Y coordinate of the illustration P1 on the surface of the semiconductor chip model 9, X2 is the X coordinate of the illustration P2 on the surface of the semiconductor chip model 9, Y2 is the Y coordinate of the illustration P2 on the surface of the semiconductor chip model 9, X3 Is the X coordinate of P3 shown on the surface of the semiconductor chip model 9, and Y3 is the Y coordinate of P3 shown on the surface of the semiconductor chip model 9.

Next, a specific analysis example using the above-described warpage state analysis method will be described. (Analysis Example 1) In this example, as shown in FIG.
The semiconductor chip 11 using the adhesive 13 which is hardened by PWB
This is an analysis example of analyzing the optimum width Lx of the semiconductor chip 11 by focusing on the warpage of the surface of the semiconductor chip 11 for a semiconductor device formed by bonding to the mounting substrate 12.

In the analysis system of the present invention shown in FIG.
First, for each of the semiconductor chip 11, the adhesive 13, and the PWB mounting board 12, the dimensions, the coefficient of thermal expansion, the elastic modulus,
When data such as Poisson's ratio, constraint conditions, and joining temperatures of materials and components are input from the input device 2, an analysis model is created by the analysis model creation means 4.

Subsequently, a finite element method analysis was performed by the finite element method analysis means 5. As a result, it was found that the surface of the semiconductor chip 11 when it was cooled to room temperature (20 ° C.) after bonding was warped concavely. When the displacement detecting means 6 detects the displacement of the end and the center of the semiconductor chip model,
When the width Lx (see FIG. 7) of the semiconductor chip 11 is 13 mm, the Y of the central portion 11b of the surface of the semiconductor chip 11
The displacement amount δyo in the direction (see FIG. 7) is -3.8 μm,
The displacement amount δxa of the end 11a in the X direction (see FIG. 7) is -4.
5 μm, the displacement amount δya of the end 11a in the Y direction is 9.1 μm
Was analyzed.

When the width Lx of the semiconductor chip 11 and the displacement amounts δya, δxa, δyo of the respective portions of the semiconductor chip 11 are transmitted to the curvature calculating means 6, the curvature calculating means 7 uses the above equation (1). The curvature S is calculated as follows.

S = 2 (δya + δyo) / ｛(Lx / 2−δx
a) ² + (in δya ten δyo) ^2} = 0.611 varied from the width Lx of 7~22mm semiconductor chip model, repeating the process until the curvature is calculated from the analysis model generated as described above, the last Next, the relationship between the width Lx and the curvature S of the semiconductor chip 11 is graphed by the graph creating means 8.

FIG. 8 is a graph showing the relationship between the width of the semiconductor chip and the curvature in the semiconductor device shown in FIG.

The relationship between the width Lx and the curvature S of the semiconductor chip 11 graphed by the graph creating means 8 is displayed on the display device 3 as a graph of a multi-order approximation curve as shown in FIG. As can be seen from the graph shown in FIG. 8, when the width Lx of the semiconductor chip 11 is in the range of 7 mm to 13 mm,
As the width Lx increases, the curvature S increases, but when the width Lx is in the range of 15 mm to 22 mm, the curvature S hardly changes. Therefore, the width Lx of the semiconductor chip 11 is set to 7 mm
If it is desired to increase the width Lx of the semiconductor chip 11 to 22 mm, the optimum width Lx is 22 mm.

As described above, according to the warp state analysis method and system of the present invention, the warp state of a semiconductor chip can be known before a semiconductor device is manufactured, and the optimum dimensions of the semiconductor chip are selected in advance and designed. can do.

(Analysis Example 2) In this example, as shown in FIG.
The melting point of the semiconductor chip 21 and the PWB mounting substrate 22 is 19
A semiconductor device formed by connecting with a solder material 23 as an adhesive at 0 ° C., solidifying them with a mold resin 24 having a glass transition point of 140 ° C., and then cooling to room temperature (20 ° C.) Pay attention to the warpage of the surface of P
5 is an analysis example for analyzing the optimum thickness t of the WB mounting board 22.

In the analysis system of the present invention shown in FIG.
First, for each of the semiconductor chip 21, the PWB mounting board 22, the solder material 23, and the mold resin 24, the dimensions, the coefficient of thermal expansion, the elastic modulus, the Poisson's ratio, the constraint conditions, the joining temperature, and the like are input from the input device 2 to obtain an analysis model. The creating unit 4 creates an analysis model.

Subsequently, the finite element method analysis was performed by the finite element method analysis means 5 and the displacement amount at the end and the center of the semiconductor chip model was detected by the displacement detection means 6. Is 1.2 mm, the displacement amount δyo in the Y direction (see FIG. 9) of the central portion 21b of the surface of the semiconductor chip 21 is −3.8 μm, and the X direction of the end portion 21a of the semiconductor chip 21 (see FIG. 9). The displacement amount δxa of the end 21a in the Y direction is 0.7 μm.
Was analyzed to be 7.7 μm.

When the thickness t of the PWB mounting board 22 and the displacement amounts δya, δxa, δyo of each part of the semiconductor chip 21 are transmitted to the curvature calculating means 6, the curvature calculating means 6 converts the above equation (1). Is used to calculate the curvature S as described below.

S = 2 (δya + δyo) / ｛(Lx / 2−δx
a) ² + (δya ten δyo) ^2} = 0.544 PWB implementation 2.8 thickness t of the substrate model from 0.7mm
When the process from the analysis model to the calculation of the curvature is repeated in the same manner, the relationship between the thickness t of the PWB mounting board 22 and the curvature S of the semiconductor chip 21 is finally determined by the graph creation means 8. Graphed.

FIG. 10 is a graph showing the relationship between the thickness of the PWB mounting substrate and the curvature of the semiconductor chip in the semiconductor device shown in FIG.

The relationship between the thickness t of the PWB mounting substrate 22 and the curvature S of the semiconductor chip 21 graphed by the graph creating means 8 is displayed on the display device 3 as a graph of a multi-order approximate curve as shown in FIG. Is done. As can be seen from the graph shown in FIG. 10, when the thickness t of the PWB mounting board 22 is about 1.8 mm, the curvature S of the semiconductor chip 21 is maximized, indicating that the semiconductor chip 21 is most warped. Therefore, the thickness t of the PWB mounting board 22 is set to 0.7 mm.
If the thickness t is set to 1.3 mm or less or 2.5 mm or more,
It can be seen that the warpage of the semiconductor chip 21 can be suppressed.

For example, the warping state of the semiconductor chip 21 is the warping state (curvature S = 0.52) when the width Lx of the semiconductor chip 11 described in the design example 1 is 7 mm.
It can also be seen that if the thickness t of the PWB mounting board 22 is to be as large as possible or less than or equal to 2), the thickness should be about 1.1 mm.

As described above, according to the analysis method and system of the present invention using the curvature as a parameter of the warp state of the structure, the warp state of the structure can be known as it is from the magnitude of the curvature value. Confusion at the design site can be prevented.

(Analysis Example 3) In this example, as shown in FIG. 11, a semiconductor device 33 in which a semiconductor chip 31 is sealed with a sealing resin 32 as shown in FIG. This is an analysis example in which the detection unit 6 detects each coordinate of an analysis target point defined in the semiconductor device model, obtains the curvature of the semiconductor chip model from the coordinates, and analyzes the optimum width Lx of the semiconductor chip.

In the analysis system of the present invention shown in FIG.
First, when the dimensions, thermal expansion coefficient, elastic modulus, Poisson's ratio, constraint conditions, joining temperature, and the like are input from the input device 2 for each of the semiconductor chip 31 and the sealing resin 32, an analysis model is created by the analysis model creation means 4. Is done. In the case of this analysis example, since the analysis model is bilaterally symmetric, only the right half is modeled as shown in FIG. 12 for simplification.

The finite element method analysis means 5 performs a finite element method analysis based on input data such as the joining temperature of each material and part, and outputs a resulting deformation state diagram of the semiconductor device model from the printer. Is done.

In the displacement detecting means 6, this deformation state diagram is captured as an image by an image scanner and displayed on a monitor. FIG. 13 is a deformation state diagram of a semiconductor device model captured as an image by an image scanner and displayed on a monitor. That is, among the semiconductor device models 41 displayed on the monitor as shown in FIG. 13, the coordinates (Xo, Yo) of the central portion 42b and the coordinates (Xa, Ya) of the end portion 42a on the surface of the semiconductor chip model 42 are Import using a mouse or the like.

The coordinates of the end 42a and the center 42b of the semiconductor chip model 42 taken in by the displacement detecting means 6 are transmitted to the curvature calculating means 6, and the curvature S of the deformed semiconductor chip model 42 is calculated by the above equation (2). ).

When the width Lx of the semiconductor chip model is changed and the process from the creation of the folded model to the calculation of the curvature is repeated as described above, finally, the width Lx and the curvature S of the semiconductor chip 31 are calculated by the graph creation means 8. Is graphed and displayed on the display device 3.

Further, in this example, the curvature S of the warpage of the semiconductor device model 41 is obtained by the method of taking in the coordinates of three arbitrary points (P1, P2, P3) on the surface of the semiconductor device model 41 shown in FIG. Can also.

Also in this case, similarly to the above, on the surface of the semiconductor device model 41 displayed on the monitor as shown in FIG. 13, the coordinates (X1, Y1) of the point P1 and the coordinates (X2, Y2) of the point P2 are displayed.
Y2) and the coordinates (X3, Y3) of the point P3 are captured using a mouse or the like. The coordinates of each point of the semiconductor device model 41 are transmitted to the curvature calculation means 7, and the curvature S of the deformed semiconductor device model 41 is calculated by the above equation (3).

In this example, the deformation state diagram output from the printer by the finite element method analysis means 5 is captured as an image using an image scanner and displayed on a monitor, and the coordinates of each part are captured using a mouse or the like. Although the case has been described as an example, the coordinates of each unit can be captured using a digitizer. In the above description, the semiconductor chip 3
1 and the case where the warpage state of the surface of the semiconductor device 33 is analyzed, but the coordinates of an arbitrary point inside the semiconductor device model 41 or the semiconductor chip model 42 are captured in the same manner as described above, so that the semiconductor chip 31 or the semiconductor device It is possible to easily analyze the state of warpage inside 33.

As described above, according to the analysis method and system of the present invention, it is possible to know the warpage of a semiconductor chip before manufacturing a semiconductor device, and to select and design the optimum dimensions of the semiconductor chip in advance. Can be.

The embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiments, and various other modifications can be made. For example, in the analysis system of the present embodiment, an analysis is performed using a two-dimensional model. However, for a structure having a complicated structure, a system using a three-dimensional model may be used.

The analysis model creating means 4 of this embodiment
Instead of the transformation state diagram of the analysis model created in
Use a digitizer to capture the coordinates of the analysis target point from an enlarged photograph, etc. of the actual warped structure taken from the side, or capture the enlarged photograph, etc. with an image scanner, display it on a monitor, and use a mouse, etc. By capturing the coordinates of the required position, the warping state of the actual structure can be analyzed.

The finite element method analysis means 5 of the present invention
It can be used in combination with various general-purpose analysis software having an analysis solver, and further in combination with general-purpose analysis software installed on the same processing unit (machine) or another machine connected by a personal computer or a computer network. The finite element method analysis function can also be used.

Further, the present invention may be in the form of a recording medium in which a warp state analysis program for causing a computer to execute the above-described procedure is recorded.

In this case, as shown in FIG. 14, the analysis processing device 51 such as a workstation or a personal computer is caused to read the analysis program recorded on the recording medium 54, and the analysis processing device 51 is read in accordance with the warpage state analysis program. Control the operation of. This recording medium 54 may be a magnetic disk, a semiconductor memory, or another recording medium. The input device 52, the display device 53
Are the same as those shown in FIG. 1 and their description is omitted. Under the control of the warp state analysis program read from the recording medium 54, the warp state analysis device 51 executes the steps S1 to S6 described with reference to FIG.

[0074]

As described above, according to the present invention,
Since the warpage that occurs in the structure can be analyzed before the structure is manufactured, it is possible to design the dimensions and materials of the structure from the beginning and reduce the cost and time of product development. . Further, by using the curvature as a parameter of the warp state of the structure, the warp state of the structure can be known as it is from the magnitude of the curvature value, so that confusion at the design site can be prevented.

Further, since the analysis of the warped state can be easily performed, it is not necessary to train a design engineer who is skilled in general-purpose analysis software, and the human cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a system for analyzing a state of warpage of a structure using a finite element method according to the present invention.

FIG. 2 is a flowchart illustrating a processing example of an analysis processing device in the structural warpage state analysis system using the finite element method illustrated in FIG. 1;

FIG. 3 is a diagram showing a semiconductor chip model created by an analysis model creating unit.

4 is a deformation state diagram obtained as a result of performing a finite element method analysis on the semiconductor chip model shown in FIG. 3;

FIG. 5 is a deformation state diagram obtained as a result of performing a finite element method analysis on the semiconductor chip model shown in FIG. 3;

FIG. 6 is a deformation state diagram obtained as a result of performing a finite element method analysis on the semiconductor chip model shown in FIG. 3;

FIG. 7 is a configuration diagram illustrating a semiconductor device to be analyzed;

8 is a graph showing a relationship between a width and a curvature of a semiconductor chip in the semiconductor device shown in FIG. 7;

FIG. 9 is a configuration diagram illustrating a semiconductor device to be analyzed.

10 is a graph showing the relationship between the thickness of a PWB mounting board and the curvature of a semiconductor chip in the semiconductor device shown in FIG.

FIG. 11 is a configuration diagram illustrating a semiconductor device to be analyzed.

FIG. 12 is a diagram showing a semiconductor device model created based on the semiconductor device shown in FIG. 11;

13 is a deformation state diagram obtained as a result of performing a finite element method analysis on the semiconductor device model shown in FIG.

FIG. 14 is a block diagram showing another embodiment of the structure warping state analysis system using the finite element method of the present invention.

FIG. 15 is a schematic diagram for explaining a conventional method for measuring the amount of warpage of a semiconductor chip.

FIG. 16 is a graph showing measurement results obtained by a conventional method for measuring the amount of warpage of a semiconductor chip.

[Explanation of symbols]

 Reference Signs List 1,51 Analysis processing device 2,52 Input device 3,53 Display device 4 Analysis model creation means 5 Finite element method analysis means 6 Displacement detection means 7 Curvature calculation means 8 Graph creation means 9,41 Semiconductor chip model 9a, 11a, 21a End 9b, 11b, 21b Central part 11, 21, 31 Semiconductor chip 12, 22 PWB mounting board 13 Adhesive 23 Solder material 24 Mold resin 32 Sealing resin 33 Semiconductor device 42 Semiconductor device model 54 Recording medium

Claims (10)

(57) [Claims] A step of creating an analysis model of a semiconductor chip to be analyzed; defining an analysis target point in the analysis model; performing a finite element analysis of the analysis model under analysis conditions desired to be obtained; Detecting the amount of displacement of the analysis target point due to the warpage occurring, and calculating the curvature of the warpage generated in the analysis model from the detected displacement amount of the analysis target point, curvature, the semiconductor chip warped state analysis method, characterized in that calculated by the equation (1). S = 2 (δya + δyo) / ｛(Lx / 2−δxa) ² + (δya + δyo) ² ｝ (1) S: curvature δyo: displacement in the Y direction at the center of the surface of the semiconductor chip δya: end of the semiconductor chip Δxa: Displacement in the X direction at the end of the semiconductor chip Lx: Width of the semiconductor chip 2. A step of performing a finite element method analysis of the analysis model while changing the analysis conditions to detect a displacement amount of the analysis target point and a step of calculating a curvature of a warp generated in the analysis model. 2. The method according to claim 1, further comprising the step of graphing a relationship between the analysis condition and the curvature. Creating an analysis model of a semiconductor chip to be analyzed; defining an analysis target point in the analysis model; performing a finite element analysis of the analysis model under analysis conditions desired to be obtained; as the analysis target point when the warpage occurs in the, middle
Detecting the coordinates of two points or any three points of the central part and the end part, and calculating the curvature of the warpage generated in the analysis model from the detected coordinates of the analysis target point, The curvature of the semiconductor chip is calculated by the equation (2) or (3). S = 2 (Ya-Yo) / {(Xa-Xo) 2 + (Ya-Yo) 2} ... formula (2) S = 2 {( X1 (Y2-Y3) + X2 (Y3-Y1) + X3 (Y1- Y2)} / [{(X1 -X2) 2 + (Y1-Y2) 2} * {(X2-X3) 2 + (Y2-Y3) 2} * {(X3 -X1) 2 + (Y3-Y1) ² ｝] ^0.5 Expression (3) S: curvature Xo: X coordinate of the center of the surface of the semiconductor chip Yo: Y coordinate of the center of the surface of the semiconductor chip Xa: X coordinate of the end of the semiconductor chip Ya: end of the semiconductor chip Coordinates of any three points on the surface of the semiconductor chip model as P1, P
P1 (X1, Y1) P2 (X2, Y2) P3 (X3, Y3) 4. A step of performing a finite element method analysis of the analysis model by changing the analysis conditions, detecting coordinates of the analysis target point in an arbitrary coordinate system, and calculating a curvature of a warp generated in the analysis model. 4. The method for analyzing a warped state of a structural body according to claim 3, further comprising the step of repeating the above steps to graph the relationship between the analysis condition and the curvature. 5. An analysis model creating means for creating an analysis model of a semiconductor chip to be analyzed, and performing a finite element method analysis of the analysis model according to given analysis conditions;
A finite element method analysis means for obtaining a deformation state of the analysis model under the analysis conditions, and, among the analysis models deformed as a result of performing the finite element analysis, of an analysis target point defined in the analysis model Displacement detection means for detecting a displacement amount or coordinates of the analysis target point in an arbitrary coordinate system; and a displacement amount of the detected analysis target point or a warp generated in the analysis model based on the coordinates in the arbitrary coordinate system. A curvature calculating means for calculating a curvature , wherein
Is calculated by equation (1).
Analysis system for warpage of conductor chips . S = 2 (δya + δyo) / ｛(Lx / 2−δxa) ² + (δya + δyo) ² ｝ (1) S: curvature δyo: at the center of the surface of the semiconductor chip
Displacement δya in the Y direction at the end of the semiconductor chip
Displacement δxa in the Y direction at the end of the semiconductor chip
X-direction displacement Lx: width of semiconductor chip 6. The semiconductor chip warpage state analyzing system according to claim 5, further comprising a graph creating means for graphing a relationship between the analysis condition and the curvature. 7. The semiconductor chip warp state analysis system according to claim 5, wherein the analysis target points are two points defined at a center part and an end part of the analysis model. 8. A semiconductor according the analysis target points in claim 5 or 6 which is a three-point defined arbitrarily on the analysis model
Body chip warpage analysis system. 9. An object to be analyzedSemiconductor chipAnalysis model of
Procedure to create a file and specify the analysis target point in the analysis model.
Under the desired analysis conditions, the finite element method
Analyze and convert to the analysis model under the analysis conditions
Detecting the amount of displacement of the analysis target point that is displaced due to warpage
Procedure and the detected displacement amount of the analysis target point.
Calculating the curvature of the warpage occurring in the analytical model
WhenHas,The curvature of the warpage is calculated by equation (1).
Semiconductor for executing on a computer characterized by the following:
Body chipRecording medium on which the warpage state analysis program is recorded
body.S = 2 (δya + δyo) / ｛(Lx / 2−δxa) ^Two + (Δya + δyo) ^Two ｝… (1) S: curvature δyo: change in the Y direction at the center of the surface of the semiconductor chip
Order δya: displacement amount in the Y direction at the end of the semiconductor chip δxa: X-direction displacement at the end of the semiconductor chip Lx: width of semiconductor chip 10.Analysis of the semiconductor chip to be analyzed
Creating a model; Analysis target points are determined in the analysis model and analysis conditions to be obtained
Under the finite element method analysis of the analysis model below,
When the model is warped,
Detects the coordinates of two points or any three points at the center and end
Steps, and Coordinates of the detected analysis point
Calculating the curvature of the warpage generated in the analysis model.
And the curvature of the warpage is determined by the equation (2) or the equation
(3) The semiconductor chip characterized by being calculated in
A recording medium that stores a warpage state analysis program. S = 2 (Ya-Yo) / ｛(Xa-Xo) ^Two + (Ya-Yo) ^Two ｝… Equation (2)  S = 2 {(X1 (Y2-Y3) + X2 (Y3-Y1) + X3 (Y1-Y2)} / [{( X1-X2) ^Two + (Y1-Y2) ^Two ｝ * ｛(X2-X3) ^Two + (Y2-Y3) ^Two ｝ * ｛(X3 -X1) ^Two + (Y3-Y1) ^Two ｝] ^0.5 … Equation (3) S: curvature Xo: X coordinate of the center of the surface of the semiconductor chip Yo: Y coordinate of the center of the surface of the semiconductor chip Xa: X coordinate at the end of the semiconductor chip Ya: Y coordinate at the end of the semiconductor chip The arbitrary three points on the surface of the semiconductor chip model are denoted by P1, P
2, P3 P1 (X1, Y1) P2 (X2, Y2) P3 (X3, Y3)