JP3351177B2 - Method for forming wiring structure including step of forming connection hole - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a wiring structure having a step of forming a connection hole. INDUSTRIAL APPLICABILITY The present invention can be applied to various wiring structures having connection holes, and can be used, for example, when forming a wiring structure in a semiconductor device.

[0002]

2. Description of the Related Art In the manufacture of a semiconductor device, a step of forming a connection hole in a planarized interlayer insulating film is sometimes performed. In this case, if there is a step in the interlayer insulating film, a step is formed above the interlayer insulating film. A connection hole formed in a portion where the film thickness is small, and a lower portion of the step (where the thickness of the interlayer film is large).
The depth differs from that of the connection hole formed in the hole.
If such connection holes are simultaneously formed by etching, the shallow connection holes will be excessively etched,
Inconvenience may occur.

For example, this problem is found in a semiconductor device having a multilayer wiring structure. That is, in recent LSIs and the like, a multilayer wiring process such as a multilayer wiring, particularly a multilayer poly-Si wiring is used in order to improve device characteristics and cope with miniaturization. In particular, in the memory, since the use of the multi-layered poly-Si wiring is different in the cell and in the peripheral circuit, the height of the lower part of the wiring (for example, the base of the Al wiring) is different. For this reason, for example, as shown in FIG. 9, when the Al wirings 2a and 2b are formed where the height of the base 1 is different and steps are formed as shown in FIG. In addition, the thickness of the interlayer film 3 differs. That is, base 1
The thickness 3a of the interlayer film 3 on the wiring 2a on the step bottom 1a is thick, and the wiring 2b on the step
The thickness 3b of the upper interlayer film 3 is small. That is, 3a> 3b. The contact hole pattern 4 is formed using the photolithography technique as it is, and the contact hole 5 is formed.
When the holes a and 5b are opened, the following problem occurs. FIG. 9 shows the middle of the etching for opening the contact and shows a state where the shallow contact hole 5b is opened. At this time, the deep contact hole 5a is being formed. When the etching is further advanced and the holes 5a and 5b are opened as shown in FIG. 10, the shallow contact hole 5b is excessively over-etched. As a result, for example, the wiring 2b
A reaction product is generated at a shallow contact due to the reaction between the gas and the etching gas. For example, in the case of the illustrated conventional example, Ti / AlC
Although TiN films 6a and 6b are formed on u / Ti wirings 2a and 2b, TiN films 6a and 6b are formed in shallow contact holes 5b.
Ti fluoride 50 may be formed on the N film 6b. This causes a problem that the contact resistance increases. In the prior art, after the holes are opened as shown in FIG. 10, the contact holes 5a and 5b are filled with, for example, W as filling materials 7a and 7b (FIG. 11), and the upper wirings 8a and 8b (second wirings) are further formed thereon. Here, Ti / AlCu /
A TiN film) and TiN films 4a and 4b are formed thereon to form a multilayer wiring structure as shown in FIG. Reference numeral 10 in the figure
Is a poly-Si wiring.

[0004]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art and relates to the formation of a wiring structure having a step of forming a connection hole. It is another object of the present invention to provide a technique in which a problem of over-etching does not occur even when a hole is formed, and a wiring structure having good characteristics can be obtained.

[0005]

The present invention has a step.
When connecting holes are formed in the interlayer insulating film formed on the lower ground
A deep contact hole is formed in the interlayer insulating film at the bottom of the step
And a shallow connection hole is formed in the interlayer insulating film above the step
For forming a wiring structure having a step of performing simultaneously
Forming a conductive film on an insulating film having a step
Forming a material layer with a low etching rate
And the etching rate at the deep connection hole forming portion.
By removing the small material layer, the shallow connection hole shape
A material layer with a low etching rate is reserved at the bottom of the formation site.
Forming and patterning the conductive film.
Process and a process of forming an interlayer insulating film to perform interlayer planarization
And a step of forming a connection hole by etching,
In the step of forming the connection hole by etching,
Due to the presence of a material layer with a low etching rate,
The etching time for forming the connection hole is set to the above deep connection.
Make sure that the etching time for forming holes is
This is a method for forming a wiring structure having a step of forming a connection hole , which solves the above problem.

[0006]

In the present invention, after the formation of the connection hole, a step of forming a second conductive film and a step of patterning the second conductive film can be performed.

[0008]

According to the present invention, a deep connection hole is formed in the interlayer insulating film corresponding to the step bottom, and a shallow connection hole is formed in the interlayer insulating film corresponding to the step upper portion of the underlying interlayer insulating film having the step. Simultaneously, a material layer having a low etching rate is formed in advance at the bottom of the shallow connection hole forming portion, so that this etching at the bottom of the shallow connection hole forming portion is performed while the deep connection hole is etched. The material layer having a low speed is etched, and consequently the connection hole is opened at the same time, so that over-etching does not occur even in a portion where a shallow connection hole is formed.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail. However, needless to say, the present invention is not limited by the following examples.

Embodiment 1 In this embodiment, the present invention is embodied in a multilayer polysilicon wiring process in the manufacture of a miniaturized semiconductor device. Please refer to FIG. 1 to FIG.

In this embodiment, a contact hole 5 is formed in an interlayer insulating film 3 formed on a stepped base 1 (here, SiO ₂ ).
a and 5b (FIGS. 5 and 6), a deep connection hole 5a is formed in an interlayer insulating film 3 corresponding to a step bottom 1a and an interlayer insulating film corresponding to a step upper 1b. When the shallow connection holes 5b are simultaneously formed in the film, a material layer 11b having a low etching rate is formed in advance at the bottom of the portion where the shallow connection holes 5b are formed (FIGS. 3 to 5, especially FIG. 5). See) Configuration.

In this embodiment, a step of forming a conductive film (conductive film 2 for forming wirings 2a and 2b) on an insulating film (SiO ₂ film) having a step as base 1 and a material layer having a low etching rate 11 (in this case, a SiN layer) (FIG. 1) and a step of removing the material layer 11 having a low etching rate in the deep connection hole formation portion (FIG. 2).
And a step of patterning the conductive film (FIG. 3) and a step of forming an interlayer insulating film 3 and performing interlayer planarization (FIG. 4).
And a step of forming the connection holes 5a and 5b by etching (FIGS. 5 and 6).

In this embodiment, the connection holes 5a, 5b
After the formation, a step of forming a second conductive film and a step of patterning the second conductive film are performed (FIG. 8). This second
The second wirings 8a and 8b (upper wirings) shown in FIG.

Particularly, in this embodiment, a step of forming a conductive film 2 containing Al as a main component on an insulating layer (underlying layer 1) having a step and unevenness over the entire surface, and preventing reflection of lithography such as TiN and TiON. A step of forming a film 6 (here, TiN);
A step of forming (silicon nitride) on the entire surface as shown in FIG. 1; and a step of removing the material 11 (SiN) in a deep portion by using lithography to form as shown in FIG.
A step of wiring 2a, 2b are formed as shown in FIG 3 by patterning the conductive film 2 by using lithography, SiO ₂
FIG. 4 shows an interlayer planarization using an insulating layer mainly composed of
And a step of forming connection holes 5a and 5b (contact holes) using lithography (FIGS. 5 and 6), and forming a second conductive film mainly containing Al on the entire surface. And a step of patterning the second conductive film using lithography (FIG. 8) to form a multilayer wiring structure.

More specifically, in this embodiment, a multilayer poly-Si wiring is formed by the following steps.

A Ti / AlCu / Ti / TiN (100/50) is sequentially formed from a lower layer on an insulating film (here, SiO ₂ ) as a base 1 having a step of about 500 nm by a sputtering method.
0/5/20 nm) to form a laminated film (see FIG. 1). In FIG. 1, reference numeral 2 denotes Ti / AlCu / T
i denotes a conductive layer made of i
Indicates iN. Subsequently, the SiN is reduced to 1 by the P-CVD method.
It is formed to a thickness of 00 nm. This SiN forms the material layer 11 having a low etching rate. Thus, the structure shown in FIG. 1 is obtained. Note that it is also possible to form the SiN film directly on the Al-based material without using the barrier layer.

After that, the material layer 11 (SiN) having a low etching rate on the low portion, that is, on the step bottom 1a is removed by lithography (FIG. 2). Reference numeral 40 denotes a resist used as a mask at this time.

Further, the conductive film 2 is patterned using a lithography technique to form a wiring pattern (FIG. 3). The resist used as a mask at this time is denoted by reference numerals 4a and 4
Indicated by b.

Subsequently, as an interlayer insulating film 31, P-TE
After the OS is formed to a thickness of 100 nm by the P-CVD method, O ₃ TEOS is further formed to a thickness of 1000 nm as the interlayer insulating film 32, and the entire surface is planarized by etch-back. Further, P-TEOS is applied as an interlayer insulating film 33 by P-CVD.
By forming the layer to a thickness of 00 nm, the interlayer insulating film 3 is formed (FIG. 3). If the thickness of the interlayer insulating film 3 is, for example, 1000 nm in a deep portion, it is about 500 nm in a shallow portion.

After the contact pattern 4 is formed by lithography, contacts are opened by anisotropic etching to form connection holes 5a and 5b (FIGS. 5 and 6).
reference). In FIG. 5 and thereafter, the SiO ₂ film formed by three layers of TEOS is illustrated as an integrated interlayer insulating film 3.

The etching for opening the contact is performed by C
_{By using a 4} F ₈ / CO-based gas, the etching rate of SiN, which is the material layer 11 having a low etching rate, can be reduced to 1/5 or less. For this reason, the etching time is substantially equal in both the shallow contact hole 5b and the deep contact hole 5a.

As a result, over-etching is not applied to the bottom of the shallow contact hole 5b for a long time, so that generation of a reaction product between the etching gas and the wiring can be suppressed to a low level. After opening the contact, the embedded conductive material 7a,
7b, the contact holes 5a and 5b are buried by blanket (Blk) -W burying (FIG. 7).

Further, Ti / AlCu is used as an upper conductive layer.
After forming / Ti / TiN (20/500/5/200 nm) on the entire surface, patterning is performed by lithography to form upper layer wirings (second wirings) 8a and 8b (FIG. 8). In FIG. 8, reference numerals 9a and 9b denote TiN layers serving as antireflection films at this time.

According to this embodiment, by employing the present invention, the contact holes 5a and 5b (contact holes) having different depths are not excessively over-etched in the contact holes 5b having a small depth. The generation of reaction products between gas and wiring can be suppressed,
The contact characteristics are improved.

[0025]

According to the method for forming a wiring structure having a step of forming a connection hole according to the present invention, even if connection holes having different depths are formed in an interlayer insulating film formed on a stepped base, the method can be applied to the formation of a connection hole. There is an effect that a problem of etching does not occur and a wiring structure having good characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing the steps of Example 1 in order (1).

FIG. 2 is a sectional view showing the steps of the first embodiment in order (2).

FIG. 3 is a sectional view showing a step of the first embodiment in order (3).

FIG. 4 is a sectional view showing the steps of the first embodiment in order (4).

FIG. 5 is a sectional view showing the steps of the first embodiment in order (5).

FIG. 6 is a sectional view showing the steps of the first embodiment in order (6).

FIG. 7 is a sectional view showing a step of the first embodiment in order (7).

FIG. 8 is a sectional view showing the steps of the first embodiment in order (8).

FIG. 9 is a sectional view showing the steps of the conventional technique in order (1).

FIG. 10 is a sectional view showing the steps of the conventional technique in order (2).

FIG. 11 is a sectional view showing a step of a conventional technique in order (3).

FIG. 12 is a sectional view showing steps of the conventional technique in order (4).

[Explanation of symbols]

Reference Signs List 1 base (insulating film) 10 poly-Si layer 2 conductive layer (Ti / AlCu / Ti) 2a, 2b wiring (first lower wiring) 3 interlayer insulating film 31 P-TEOS 32 O ₃ TEOS 33 P-TEOS 4, 4a , 4b, 40 resist 5a deep connection hole (deep contact hole) 5b shallow connection hole (shallow contact hole) 6 antireflection film (TiN layer) 7a, 7b embedded conductive material (Blk-W) 8a, 8b second (upper layer) Wiring 11, 11a, 11b Material layer with low etching rate (SiN layer)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/768 H01L 21/027 H01L 21/28 H01L 21/3065

Claims (2)

(57) [Claims] An interlayer insulating film formed on a stepped underlayer.
When forming a connection hole in the hole, the interlayer insulation at the bottom of the step
A deep connection hole is formed in the edge film, and the interlayer insulation above the step
Step of forming shallow connection holes in the edge film simultaneously
In the method for forming a wiring structure that includes the steps of forming a conductive film on an insulating film having a step, a step of forming a material with a low layer etching rate, the smaller material layer with the etch rate in the deep contact hole forming portion By removing the above shallow connection hole formation part
A material layer with a low etching rate on the bottom of the
And it should form process, forming a step of patterning the conductive film includes a step of performing an interlayer flattening an interlayer insulating film, and forming a connection hole by etching, the contact hole by etching In the process of
Due to the presence of a material layer with a low etching rate,
The etching time for forming the connection hole is set to the above deep connection.
A method for forming a wiring structure, comprising a step of forming a connection hole, wherein the etching time is substantially equal to the etching time for forming the hole. Wherein after formation of the connection hole, forming a second conductive film, the connection hole according to claim 1, characterized in that a step of patterning the second conductive film formed A method for forming a wiring structure, comprising the steps of: