JP3351053B2 - Electronic components - Google Patents

Electronic components

Info

Publication number
JP3351053B2
JP3351053B2 JP26055093A JP26055093A JP3351053B2 JP 3351053 B2 JP3351053 B2 JP 3351053B2 JP 26055093 A JP26055093 A JP 26055093A JP 26055093 A JP26055093 A JP 26055093A JP 3351053 B2 JP3351053 B2 JP 3351053B2
Authority
JP
Japan
Prior art keywords
electronic component
adhesive
notch
wiring board
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP26055093A
Other languages
Japanese (ja)
Other versions
JPH07115100A (en
Inventor
一弘 前野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Industries Corp
Original Assignee
Toyota Industries Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Industries Corp filed Critical Toyota Industries Corp
Priority to JP26055093A priority Critical patent/JP3351053B2/en
Publication of JPH07115100A publication Critical patent/JPH07115100A/en
Application granted granted Critical
Publication of JP3351053B2 publication Critical patent/JP3351053B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83194—Lateral distribution of the layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、接着剤を用いて配線基
板上に接着される、電子部品に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component adhered on a wiring board using an adhesive.

【０００２】[0002]

【従来の技術】図８は、従来の電子部品の接着の一例を
示す図である。同図（ａ）に示す，配線基板５上には、
図示しないベアチップ、チップ抵抗、チップコンデンサ
等の部品が実装されている。さらに、前記配線基板５上
に電子部品３ｌをマウントする際には、該配線基板５上
のマウントされる位置に、例えばペ−スト状接着剤７
が、予め、図示しないディスペンサ等で塗布されてい
る。2. Description of the Related Art FIG. 8 is a diagram showing an example of conventional bonding of electronic components. On the wiring board 5 shown in FIG.
Components such as a bare chip, a chip resistor, and a chip capacitor (not shown) are mounted. Further, when the electronic component 3l is mounted on the wiring board 5, for example, a paste-like adhesive 7 is placed on the mounting position on the wiring board 5.
Is previously applied by a dispenser or the like (not shown).

【０００３】その後、同図（ｂ）に示す様に、前記電子
部品３ｌは、図示しないマウンタ等で、前記配線基板５
上の前記位置にマウント、圧着される。Thereafter, as shown in FIG. 1B, the electronic component 31 is mounted on the wiring board 5 by a mounter (not shown) or the like.
Mounted and crimped at the above position.

【０００４】[0004]

【発明が解決しようとする課題】以上の様に、従来の電
子部品３ｌの接着方法は、予め接着剤７が供給された配
線基板５上に、該電子部品３ｌをマウント、圧着する事
で行われるが、この際、余剰な接着剤７が図８（ｃ）に
示す図８（ｂ）のＢ−Ｂ’断面図の様に、電子部品３ｌ
の周囲からはみ出す。その結果、図９（ａ）に示す様
に、隣接するベアチップ８を覆ったり、図９（ｂ）に示
す様に、隣接する配線接続用ランド９を覆ったり、或い
は図９（ｃ）に示す様に、隣接する電子部品１０を覆っ
たりする。As described above, the conventional method for bonding electronic components 3l is performed by mounting and crimping the electronic components 3l on the wiring board 5 to which the adhesive 7 has been supplied in advance. However, at this time, the excess adhesive 7 is applied to the electronic component 3l as shown in the cross-sectional view taken along the line BB 'of FIG.
Protrude from around. As a result, as shown in FIG. 9A, the adjacent bare chip 8 is covered, as shown in FIG. 9B, the adjacent wiring connection land 9 is covered, or as shown in FIG. 9C. In this way, it covers the adjacent electronic component 10.

【０００５】接着剤７が、隣接するベアチップ８を覆う
と、該接着剤７中に含まれる不純物で汚染され、故障の
原因となったり、該ベアチップ８上面に設けてあるパッ
ドから外部へのワイヤボンドができなくなる問題があっ
た。又、接着剤７が、配線接続用ランド９を覆うと、電
子部品３ｌと配線基板５との配線接続ができなくなる問
題があった。さらに、接着剤７が電子部品１０を覆う
と、該接着剤７の熱応力により、該電子部品１０と配線
基板５との接続部を破壊したり、時には該電子部品１０
自体を破壊するという問題があった。When the adhesive 7 covers the adjacent bare chip 8, the adhesive 7 is contaminated with impurities contained in the adhesive 7, which may cause a failure or a wire from a pad provided on the upper surface of the bare chip 8 to the outside. There was a problem that bonding could not be performed. Further, when the adhesive 7 covers the wiring connection lands 9, there is a problem that the wiring connection between the electronic component 3l and the wiring board 5 cannot be performed. Further, when the adhesive 7 covers the electronic component 10, the connection between the electronic component 10 and the wiring board 5 may be broken due to the thermal stress of the adhesive 7, and sometimes the electronic component 10 may be damaged.
There was a problem of destroying itself.

【０００６】上記諸問題は、接着剤で接着する電子部品
の周囲に、接着剤で覆われてはまずい部品やランド等を
近接させない配置をする事で、解決できる。しかし、近
年の電子製品の小型軽量化への進展に伴い、配線基板に
ついても高集積化、及び高密度化が要求されている。従
って、配線基板の配線幅や配線間隔の狭ピッチ化は勿
論、実装部品間の間隔や、ベアチップと配線基板との接
続間隔も縮小化する必要があるが、前述の方法では、達
成できなくなる。The above-mentioned problems can be solved by arranging electronic parts to be bonded with an adhesive so that parts or lands which are not covered with the adhesive are not brought close to each other. However, with the recent progress in making electronic products smaller and lighter, higher integration and higher density of wiring boards are also required. Therefore, it is necessary to reduce not only the wiring width of the wiring board and the pitch of the wiring interval, but also the interval between the mounting components and the connection interval between the bare chip and the wiring board, but this cannot be achieved by the above-described method.

【０００７】一方、上記諸問題を解決する他の方法とし
て、接着剤の量を減らす事が挙げられる。しかし、この
方法では未充填部分が発生し易いという問題がある。未
充填部分が発生すると、接着強度が低下したり、電子部
品が発熱する場合に、放熱性が低下し、電子部品が熱破
壊する事がある。本発明はこの様な諸問題を解決するも
のであり、配線基板の高集積化、及び高密度化を達成し
た上で、信頼性の高い、接着剤による電子部品の接着を
達成する事を目的とする。On the other hand, another method for solving the above problems is to reduce the amount of the adhesive. However, this method has a problem that an unfilled portion is easily generated. When an unfilled portion occurs, the adhesive strength is reduced, and when the electronic component generates heat, the heat radiation property is reduced, and the electronic component may be thermally damaged. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and aims to achieve highly reliable and highly reliable bonding of electronic components with an adhesive after achieving high integration and high density of a wiring board. And

【０００８】[0008]

【課題を解決するための手段】上記目的を達成する為に
本発明では、切り欠きを、電子部品の接着面に、以下に
示す位置や形状で設けた。請求項１に記載の発明は、配
線基板上にペースト状接着剤により接着されると共に、
接着面と該接着面に繋がる側面とによって形成される角
部に切り欠きが設けられた電子部品において、前記切り
欠きの形状を凹型曲面にすると共に、前記切り欠きを前
記接着面の中心部から前記角部に向けて広がる形で設け
た。 In order to achieve the above-mentioned object, in the present invention, a notch is provided on the bonding surface of an electronic component in the following position and shape. According to one aspect of the present invention, distribution
Glued on the wire substrate with a paste adhesive,
The corner formed by the bonding surface and the side surface connected to the bonding surface
In an electronic component having a notch in a portion,
The shape of the notch is a concave curved surface, and the notch is
Provided in a form that spreads from the center of the adhesive surface toward the corner
Was.

【０００９】[0009]

【００１０】[0010]

【００１１】[0011]

【作用】前記構成により、電子部品が配線基板上にマウ
ント、圧着された時、余剰な接着剤を該切り欠きに逃が
す様にしたので、該電子部品の周囲にはみ出す接着剤の
量を大幅に抑えられるか、或いは無くする事が可能とな
る。又、該切り欠きから、空気が効率良く排出される
為、未充填部分の発生を大幅に抑えられるか、或いは無
くする事が可能となる。According to the above construction, when the electronic component is mounted and crimped on the wiring board, excess adhesive is allowed to escape to the notch, so that the amount of the adhesive protruding around the electronic component is greatly reduced. It can be suppressed or eliminated. Further, since the air is efficiently exhausted from the notch, it is possible to greatly suppress or eliminate the generation of the unfilled portion.

【００１２】ところで、電子部品の接着面の形状が、例
えば長方形の場合、接着面中心からの距離の最も短い、
各辺の中央部分において、はみ出す傾向があるが、この
様なはみ出し易い位置に、部分的に切り欠きを設ける請
求項２及び３に記載の方法でも同様の作用が得られる。When the shape of the bonding surface of the electronic component is, for example, a rectangle, the distance from the center of the bonding surface is the shortest.
At the central portion of each side, there is a tendency to protrude, but the same effect can be obtained by the method according to claims 2 and 3 in which a notch is partially provided at such a position where the protruding portion is easily protruded.

【００１３】[0013]

【実施例】以下、本発明の実施例について、図面を参照
しながら説明する。図１（ａ）において、電子部品３ａ
は、例えばベアチップが搭載された、長方形の接着面１
ａを有するヒートスプレッダであり、該接着面１ａと、
該接着面１ａに繋がる側面４ａとによって形成される角
部全てに、例えば凹型曲面の形状を持つ切り欠き２ａを
設けてある。Embodiments of the present invention will be described below with reference to the drawings. In FIG. 1A, the electronic component 3a
Is a rectangular bonding surface 1 on which, for example, a bare chip is mounted.
a heat spreader having an adhesive surface 1a;
All corners formed by the side surface 4a connected to the bonding surface 1a are provided with notches 2a having a concave curved surface shape, for example.

【００１４】図１（ｂ）において、配線基板５は、例え
ばＰＣＢ又はセラミック基板であり、その表面（両面基
板の場合は、裏面、多層基板の場合は、内層にも形成さ
れる）には所定の回路を構成する配線パタ−ン６が形成
されている。そして、図中には特に示さないが、前記配
線基板５上にはベアチップ、チップ抵抗、チップコンデ
ンサ等の部品が実装されている。さらに、前記配線基板
５上に前記電子部品３ａをマウントする際には、前記配
線基板５上のマウントされる位置に、例えばペースト状
接着剤７が、予め、図示しないディスペンサ等で塗布さ
れている。In FIG. 1B, the wiring substrate 5 is, for example, a PCB or a ceramic substrate, and a predetermined surface is formed on the front surface (the rear surface in the case of a double-sided substrate, and also in the inner layer in the case of a multilayer substrate). The wiring pattern 6 constituting the circuit of FIG. Although not particularly shown in the drawing, components such as a bare chip, a chip resistor, and a chip capacitor are mounted on the wiring board 5. Further, when mounting the electronic component 3a on the wiring board 5, for example, a paste adhesive 7 is applied in advance to a mounting position on the wiring board 5 by a dispenser or the like (not shown). .

【００１５】その後、図１（ｃ）に示す様に、前記電子
部品３ａは、図示しないマウンタ等で、前記配線基板５
上の前記位置にマウント、圧着される。その結果、前記
接着剤７は、該電子部品３ａと該配線基板５間を押し広
げられるが、余剰な接着剤は、該電子部品３ａに設けた
前記切り欠き２ａに逃げる為、図１（ｄ）に示す様に、
該電子部品３ａの周囲にはみ出す量は大幅に抑えられる
か、或いは無くせる。Thereafter, as shown in FIG. 1C, the electronic component 3a is mounted on the wiring board 5 by a mounter (not shown) or the like.
Mounted and crimped at the above position. As a result, the adhesive 7 spreads between the electronic component 3a and the wiring board 5, but excess adhesive escapes to the notch 2a provided in the electronic component 3a. ),
The amount protruding around the electronic component 3a can be greatly reduced or eliminated.

【００１６】又、前記切り欠き２ａは、凹型曲面となっ
ている為、前記電子部品３ａをマウントした際、該切り
欠き２ａ内の空気は速やかに排出されるので、空気が滞
留することは無く、未充填部分（ボイド）の発生は大幅
に抑えられるか、或いは無くせる。ところで、上記構成
においては、接着する電子部品側に切り欠きを設ける構
造になっているが、接着される配線基板側に切り欠きを
設けても、余剰な接着剤のはみ出し防止効果は得られ
る。しかし、電子製品に用いられる配線基板は通常、は
み出し防止効果が得られるに充分な深さの切り欠きが設
けられるほど厚みがないので、該配線基板側に切り欠き
を設けることはできない。Further, since the notch 2a has a concave curved surface, when the electronic component 3a is mounted, the air in the notch 2a is quickly discharged, so that the air does not stay. The generation of unfilled portions (voids) can be greatly suppressed or eliminated. By the way, in the above configuration, the notch is provided on the side of the electronic component to be bonded. However, even if the notch is provided on the side of the wiring board to be bonded, the effect of preventing excess adhesive from protruding can be obtained. However, a wiring board used for an electronic product is generally not thick enough to provide a notch having a sufficient depth to obtain a protrusion prevention effect, and thus a notch cannot be provided on the wiring board side.

【００１７】又、たとえ配線基板の厚みが充分あり、切
り欠きが設けられたとしても、電子部品をマウントする
と、切り欠きが全て該電子部品で覆われるので空気の逃
げ道が無くなり、接着剤の未充填部分が発生する。一
方、空気の逃げ道を設ける為に、切り欠きを電子部品の
外形寸法より大きくすると、配線基板の実装密度が低下
する。本実施例の方法であれば、これらの問題は全て解
決する。Even if the wiring board has a sufficient thickness and the notches are provided, when the electronic parts are mounted, all the notches are covered with the electronic parts, so that there is no way for air to escape, and the adhesive is not removed. A filling portion occurs. On the other hand, if the notch is made larger than the external dimensions of the electronic component in order to provide an escape path for air, the mounting density of the wiring board is reduced. According to the method of the present embodiment, all of these problems are solved.

【００１８】次に、図２、及び図３に本発明の他の実施
例における、電子部品３ｂ及び３ｃの各接着面１ｂ及び
１ｃ側の斜視図を各々示す。両図において図１と同じ構
成は同じ番号を付し、説明を省略する。図２に示す例で
は、電子部品３ｂに、なだらかな凹型曲面を持つ切り欠
き２ｂを、接着面１ｂと該接着面１ｂに繋がる側面４ｂ
とによって形成される角部のうち、各辺の中央部分にの
み設けてある。Next, FIGS. 2 and 3 are perspective views showing the bonding surfaces 1b and 1c of the electronic components 3b and 3c in another embodiment of the present invention. In both figures, the same components as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. In the example shown in FIG. 2, the electronic component 3b is provided with a notch 2b having a gentle concave curved surface, and a bonding surface 1b and a side surface 4b connected to the bonding surface 1b.
Are provided only at the center of each side.

【００１９】ところで、前記接着面１ａ或いは１ｂの様
に、接着面の形状が長方形の場合、該接着面の，中心か
らの距離の最も短い、各辺の中央部分において、接着剤
がはみ出す傾向がある。従って、切り欠き２ｂを図２に
示した様な位置に設ければ、接着剤のはみ出し易い部分
のみが、効率よく防止できる。図３に示す例では、電子
部品３ｃに、なだらかな凹型曲面を持つ切り欠き２ｃ
を、接着面１ｃの中心部から、前記角部のうちの各辺の
中央部分に向けて広がる形で設けてある。In the case where the shape of the bonding surface is rectangular, as in the case of the bonding surface 1a or 1b, the adhesive tends to protrude at the center of each side of the bonding surface, which is the shortest distance from the center. is there. Therefore, if the notch 2b is provided at the position as shown in FIG. 2, only the portion where the adhesive easily protrudes can be efficiently prevented. In the example shown in FIG. 3, a notch 2c having a gentle concave curved surface is formed in the electronic component 3c.
Are provided so as to spread from the center of the bonding surface 1c toward the center of each side of the corner.

【００２０】前記切り欠き２ｃを設けると、図２に示し
た実施例で述べた前記作用の他に、前記電子部品３ｃを
配線基板にマウント、圧着する際、該電子部品３ｃと該
配線基板間の空気が、外気へ効率良く排出されるので、
接着材層中に未充填部分（ボイド）が発生するのを、大
幅に抑えるか、或いは無くする事ができる。尚、接着面
の形状は、前記接着面１ａ、１ｂ或いは１ｃの様な長方
形に限定されず、例えば、図４に示す三角形、或いは図
５に示す台形等の、他の種々の形状の接着面に、切り欠
きを適宜設けても、同様の作用が得られる。When the notch 2c is provided, in addition to the operation described in the embodiment shown in FIG. 2, when the electronic component 3c is mounted on the wiring board and crimped, the gap between the electronic component 3c and the wiring board is reduced. Air is efficiently exhausted to the outside air,
The generation of unfilled portions (voids) in the adhesive layer can be largely suppressed or eliminated. Note that the shape of the bonding surface is not limited to a rectangle such as the bonding surfaces 1a, 1b, or 1c. For example, a bonding surface having various other shapes such as a triangle shown in FIG. 4 or a trapezoid shown in FIG. A similar effect can be obtained by appropriately providing a notch.

【００２１】即ち、図４（ａ）に示す、電子部品３ｄに
おいて、三角形の接着面１ｄと、該接着面１ｄに繋がる
側面４ｄとによって形成される角部全てに、例えば凹型
曲面の形状を持つ切り欠き２ｄを設けてあり、図１に示
した実施例と同様の作用が得られる。又、図４（ｂ）に
示す、電子部品３ｅにおいて、前記角部のうち、各辺の
中央部分にのみ、例えばなだらかな凹型曲面の形状を持
つ切り欠き２ｅを設けてあり、図２に示した実施例と同
様の作用が得られる。That is, in the electronic component 3d shown in FIG. 4A, all corners formed by the triangular adhesive surface 1d and the side surface 4d connected to the adhesive surface 1d have, for example, a concave curved shape. The notch 2d is provided, and the same operation as the embodiment shown in FIG. 1 can be obtained. Also, in the electronic component 3e shown in FIG. 4B, a cutout 2e having a gentle concave curved surface, for example, is provided only in the center of each side of the corners, as shown in FIG. The same operation as the embodiment described above can be obtained.

【００２２】さらに、図４（ｃ）に示す、電子部品３ｆ
において、三角形の接着面１ｆの中心部から、前記角部
のうち、各辺の中央部分に向けて広がる形で、例えばな
だらかな凹型曲面の形状を持つ切り欠き２ｆを設けてあ
り、図３に示した実施例と同様の作用が得られる。図５
では、電子部品３ｇ、３ｈ及び３ｉにおける、各接着面
１ｇ、１ｈ及び１ｉが台形の場合の実施例であり、図４
と同様の構成及び作用を有する。次に、図６及び図７に
は、さらに他の実施例における、電子部品３ｊ及び３ｋ
の各切り欠き２ｊ及び２ｋの、一部断面図を示す。両図
において、図１と同じ構成は、同じ番号を付し、説明を
省略する。Further, the electronic component 3f shown in FIG.
In FIG. 3, a notch 2f having a shape of, for example, a gentle concave curved surface is provided so as to extend from the center of the triangular bonding surface 1f toward the center of each side of the corners. The same operation as in the illustrated embodiment can be obtained. FIG.
FIG. 4 shows an example in which the bonding surfaces 1g, 1h and 1i of the electronic components 3g, 3h and 3i are trapezoidal.
It has the same configuration and operation as. Next, FIGS. 6 and 7 show electronic components 3j and 3k according to still another embodiment.
Is a partial cross-sectional view of each of the notches 2j and 2k. In both figures, the same components as those in FIG.

【００２３】図６では、切り欠き２ｊの断面形状をテー
パー状に、図７では、切り欠き２ｋの断面形状を段状に
形成してある。両切り欠き２ｊ、２ｋ共、図１、図２、
図３、図４或いは図５の各実施例で設けた、切り欠き２
ａ、２ｂ、２ｃ、２ｄ、２ｅ、２ｆ、２ｇ、２ｈ或いは
２ｉと同様の位置に設け、同様の作用が得られる。以
上、本発明の実施例を示したが、電子部品の形状は、菱
形や五角形又はその他複雑な形状であっても同様に適宜
切り欠きを設けても良く、又切り欠きの形状及び位置
は、同様の作用が得られるものであれば、実施例に限定
されるものではない。In FIG. 6, the cross section of the notch 2j is tapered, and in FIG. 7, the cross section of the notch 2k is stepped. Both the notches 2j and 2k are shown in FIGS.
Notch 2 provided in each embodiment of FIG. 3, FIG. 4 or FIG.
a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, or 2i, provided at the same position as that of 2i, and a similar effect is obtained. As mentioned above, although the example of the present invention was shown, the shape of the electronic component may be provided with a notch even if it is a rhombus, a pentagon or other complicated shape, and the shape and position of the notch are as follows. The present invention is not limited to the embodiment as long as the same operation can be obtained.

【００２４】[0024]

【発明の効果】以上説明した様に、本発明によれば、電
子部品の接合面に切り欠きを設け、例えば配線基板上に
マウント、圧着された時、余剰な接着剤を該切り欠きに
逃がす様にしたので、該電子部品の周囲にはみ出す量は
大幅に抑えられるか、或いは無くせる。その結果、前記
電子部品の近接した周囲に、ベアチップ、電子部品、或
いは配線接続用ランド等を配置できる様になる為、高密
度実装が可能となり、配線基板の小型、軽量化が図れ
る。As described above, according to the present invention, a notch is provided in the joint surface of an electronic component, and when the electronic component is mounted on a wiring board and pressed, for example, excess adhesive is released into the notch. As a result, the amount protruding around the electronic component can be greatly suppressed or eliminated. As a result, since a bare chip, an electronic component, a land for wiring connection, and the like can be arranged around the electronic component in close proximity, high-density mounting becomes possible, and the size and weight of the wiring board can be reduced.

【００２５】又、同時に、前記切り欠きから空気が効率
良く排出されるので、接着剤層中に未充填部分が発生す
るのを、大幅に抑えるか、或いは無くする事ができ、確
実かつ安定した高品質の接着が得られ、配線基板の信頼
性が飛躍的に向上する。At the same time, since the air is efficiently exhausted from the notch, the generation of an unfilled portion in the adhesive layer can be largely suppressed or eliminated, and a reliable and stable operation can be achieved. High-quality bonding is obtained, and the reliability of the wiring board is dramatically improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 本発明の実施例を説明する図であり、同図
（ａ）は配線基板に接着する前の電子部品３ａの接着面
１ａ側の斜視図、同図（ｂ）は電子部品を接着する前の
配線基板５の斜視図、同図（ｃ）は電子部品３ａを配線
基板５にマウント、圧着した状態の斜視図、同図（ｄ）
は同図（ｃ）のＡ−Ａ’線の一部断面図である。FIGS. 1A and 1B are diagrams illustrating an embodiment of the present invention. FIG. 1A is a perspective view of an electronic component 3a on an adhesive surface 1a side before the electronic component 3a is attached to a wiring board, and FIG. FIG. 2C is a perspective view of the wiring board 5 before bonding, and FIG. 2C is a perspective view of a state in which the electronic component 3 a is mounted and crimped on the wiring board 5, and FIG.
Is a partial cross-sectional view taken along line AA ′ of FIG.

【図２】 本発明の他の実施例における、電子部品３ｂ
の接着面１ｂ側の斜視図である。FIG. 2 shows an electronic component 3b according to another embodiment of the present invention.
FIG. 3 is a perspective view of the side of the bonding surface 1b.

【図３】 本発明のさらに他の実施例における、電子部
品３ｃの接着面１ｃ側の斜視図である。FIG. 3 is a perspective view of an electronic component 3c on an adhesive surface 1c side according to still another embodiment of the present invention.

【図４】 本発明のさらに他の実施例における、電子部
品３ｄ、３ｅ及び３ｆの各接着面１ｄ、１ｅ及び１ｆ側
の斜視図である。FIG. 4 is a perspective view of each of bonding surfaces 1d, 1e, and 1f of electronic components 3d, 3e, and 3f in still another embodiment of the present invention.

【図５】 本発明のさらに他の実施例における、電子部
品３ｇ、３ｈ及び３ｉの各接着面１ｇ、１ｈ及び１ｉ側
の斜視図である。FIG. 5 is a perspective view of the bonding surfaces 1g, 1h, and 1i of electronic components 3g, 3h, and 3i according to still another embodiment of the present invention.

【図６】 本発明のさらに他の実施例における、電子部
品３ｊの切り欠き２ｊ部分の一部断面図である。FIG. 6 is a partial sectional view of a notch 2j portion of an electronic component 3j according to still another embodiment of the present invention.

【図７】 本発明のさらに他の実施例における、電子部
品３ｋの切り欠き２ｋ部分の一部断面図である。FIG. 7 is a partial sectional view of a notch 2k portion of an electronic component 3k according to still another embodiment of the present invention.

【図８】 従来の、電子部品３ｌの接着の一例を示す図
であり、同図（ａ）は、接着する前の電子部品３ｌ、及
び配線基板５の斜視図、同図（ｂ）は、電子部品３ｌを
配線基板５にマウント、圧着した状態の斜視図、同図
（ｃ）は、同図（ｂ）のＢ−Ｂ’線の一部断面図であ
る。8A and 8B are diagrams illustrating an example of conventional bonding of electronic components 3l. FIG. 8A is a perspective view of the electronic components 3l and the wiring board 5 before bonding, and FIG. A perspective view of a state where the electronic component 3l is mounted and crimped on the wiring board 5, and FIG. 3C is a partial cross-sectional view taken along the line BB ′ of FIG.

【図９】 従来の、電子部品３ｌを接着する際に起こる
問題点の例を示す図であり、同図（ａ）は、はみ出した
接着剤７が隣接するベアチップ８を覆った状態の斜視
図、同図（ｂ）は、はみ出した接着剤７が隣接する配線
接続用ランド９を覆った状態の斜視図、同図（ｃ）は、
はみ出した接着剤７が隣接する電子部品１０を覆った状
態の斜視図である。FIG. 9 is a view showing an example of a problem that occurs when a conventional electronic component 3l is bonded, and FIG. 9 (a) is a perspective view of a state in which the protruding adhesive 7 covers an adjacent bare chip 8; FIG. 3B is a perspective view showing a state in which the protruding adhesive 7 covers the adjacent wiring connection lands 9, and FIG.
FIG. 4 is a perspective view showing a state in which the protruding adhesive 7 covers an adjacent electronic component 10.

【符合の説明】[Description of sign]

１ａ，１ｂ，１ｃ，１ｄ，１ｅ，１ｆ，１ｇ，１ｈ，１
ｉ，１ｊ，１ｋ…接着面、２ａ，２ｂ，２ｃ，２ｄ，２
ｅ，２ｆ，２ｇ，２ｈ，２ｉ，２ｊ，２ｋ…切り欠き、
３ａ，３ｂ，３ｃ，３ｄ，３ｅ，３ｆ，３ｇ，３ｈ，３
ｉ，３ｊ，３ｋ，３ｌ…電子部品、４ａ，４ｂ，４ｃ，
４ｄ，４ｅ，４ｆ，４ｇ，４ｈ，４ｉ，４ｊ，４ｋ…側
面、５…配線基板、６…配線パターン、７…接着剤、８
…ベアチップ、９…配線接続用ランド、１０…電子部品1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1
i, 1j, 1k: adhesive surface, 2a, 2b, 2c, 2d, 2
e, 2f, 2g, 2h, 2i, 2j, 2k...
3a, 3b, 3c, 3d, 3e, 3f, 3g, 3h, 3
i, 3j, 3k, 31: electronic components, 4a, 4b, 4c,
4d, 4e, 4f, 4g, 4h, 4i, 4j, 4k ... side surface, 5 ... wiring board, 6 ... wiring pattern, 7 ... adhesive, 8
... Bear chip, 9 ... Land for wiring connection, 10 ... Electronic parts

フロントページの続き (56)参考文献 特開 昭63−241937（ＪＰ，Ａ) 特開 昭57−181133（ＪＰ，Ａ) 特開 昭56−76543（ＪＰ，Ａ) 特開 昭54−150973（ＪＰ，Ａ) 特開 昭50−104864（ＪＰ，Ａ) 特開 平６−177178（ＪＰ，Ａ) 特開 平５−206178（ＪＰ，Ａ) 特開 平５−166853（ＪＰ，Ａ) 特開 平４−312932（ＪＰ，Ａ) 特開 平３−276649（ＪＰ，Ａ) 実開 昭60−101743（ＪＰ，Ｕ) 実開 平４−70738（ＪＰ，Ｕ) 実開 平２−26234（ＪＰ，Ｕ)Continuation of front page (56) References JP-A-63-241937 (JP, A) JP-A-57-181133 (JP, A) JP-A-56-76543 (JP, A) JP-A-54-150973 (JP, A) JP-A-50-104864 (JP, A) JP-A-6-177178 (JP, A) JP-A-5-206178 (JP, A) JP-A-5-168853 (JP, A) JP-A-3-276649 (JP, A) JP-A-60-101743 (JP, U) JP-A-4-70738 (JP, U) JP-A-2-26234 (JP, A) U)

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 配線基板上にペースト状接着剤により接
着されると共に、接着面と該接着面に繋がる側面とによ
って形成される角部に切り欠きが設けられた電子部品に
おいて、前記切り欠きの形状を凹型曲面にすると共に、
前記切り欠きを前記接着面の中心部から前記角部に向け
て広がる形で設けたことを特徴とする電子部品。1. An electronic component which is bonded to a wiring board with a paste-like adhesive and has a notch provided at a corner formed by an adhesive surface and a side surface connected to the adhesive surface, wherein While making the shape a concave curved surface,
Orient the notch from the center of the adhesive surface to the corner
An electronic component characterized by being provided in a spread form .
JP26055093A 1993-10-19 1993-10-19 Electronic components Expired - Fee Related JP3351053B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26055093A JP3351053B2 (en) 1993-10-19 1993-10-19 Electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26055093A JP3351053B2 (en) 1993-10-19 1993-10-19 Electronic components

Publications (2)

Publication Number Publication Date
JPH07115100A JPH07115100A (en) 1995-05-02
JP3351053B2 true JP3351053B2 (en) 2002-11-25

Family

ID=17349520

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26055093A Expired - Fee Related JP3351053B2 (en) 1993-10-19 1993-10-19 Electronic components

Country Status (1)

Country Link
JP (1) JP3351053B2 (en)

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* Cited by examiner, † Cited by third party
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JP2006120993A (en) * 2004-10-25 2006-05-11 Toppan Forms Co Ltd Ic chip, and sheet with ic chip mounted thereon
JP4721743B2 (en) * 2005-03-29 2011-07-13 京セラ株式会社 Semiconductor block holding device
EP2159580B1 (en) * 2008-08-26 2015-10-07 Lake Shore Cryotronics, Inc. Probe tip
JP5549532B2 (en) 2010-10-21 2014-07-16 富士電機株式会社 Manufacturing method of semiconductor device
JP5942212B2 (en) * 2013-05-13 2016-06-29 パナソニックＩｐマネジメント株式会社 Semiconductor device and manufacturing method thereof, semiconductor module and manufacturing method thereof, and semiconductor package
JP6268821B2 (en) * 2013-09-03 2018-01-31 ウシオ電機株式会社 Semiconductor laser device
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