JP3349777B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a chip architecture suitable for a center power pin type semiconductor memory device in which a power supply and a ground pin are arranged in the center of a chip.

[0002]

2. Description of the Related Art FIG. 9 is a diagram showing a chip architecture of a conventional corner power pin type semiconductor memory device. With reference to FIG. 9, this semiconductor memory device has a chip 1
00, a peripheral circuit 101, and a memory cell array 102. Squares arranged on the short side of the chip 100 included in the peripheral circuit 101 are pads connected to external pins Vcc, GND, etc., V is a power supply pad, G is a ground pad, and DQ is a plurality of input pads. Shows the output pad. In the corner power pin method, as shown in FIG. 9, a power supply pin Vcc and a ground pin GND are arranged at corners, a power supply pad V and a ground pad G are respectively arranged on the short side of the chip 100, and an input pad DQ is grounded. Generally, it is arranged on both sides of the pad G. RT1 to RT16 are data bus signal lines. In this figure, the number of data that can be handled simultaneously is 16. Since the case of 16 IO division is considered, the number of data buses is 16. The memory cell array 102 is divided into N blocks 1 to N, and a bit line load BT and a sense amplifier SA are arranged for each of the blocks 1 to N.

FIG. 10 is a diagram showing one of the blocks shown in FIG. 9 and its accompanying bit line load BT and sense amplifier SA. In FIG. 10, WL0
To WLi are word lines, and RD1 to RD16 are shown in FIG.
Is a data bus signal line shown in FIG. In each block, the memory cell array is further divided into some IOs, and in the example of FIG. Each of the IOs 1 to 16 is independent and can exchange data at the same time. Outputs from the sense amplifiers SA1 to SA16 of the IOs 1 to 16 are output from the respective IOs.
Data bus signal lines RD1 to RD16 corresponding to 1 to 16
It is connected to the.

FIG. 11 shows one of the IOs shown in FIG. The IO shown in FIG. 11 includes a memory cell array MA, a bit line load BT, a transfer gate TG, and a sense amplifier SA. The memory cell array MA has a word line WL
0 to WLi, bit lines BL0, / BL0 to BLj, / B
Lj, and a memory cell MC. Memory cell MC
Are provided i in the word line direction and j in the bit line direction. YD0 to YDj are column selection signals, IO, //
IO is an IO line pair, and RD is a data bus signal line RD1 to RD.
One of sixteen.

FIG. 12 shows the sense amplifier SA shown in FIG.
FIG. 5 is a diagram showing a path from the output of FIG. In the figure, a1 to aN are the outputs of the sense amplifiers SA of the blocks 1 to N, and b are the data bus signal lines RD1 to RD.
One of D16, c is an output buffer, and d is an input / output pad.

Next, the operation of the semiconductor memory device shown in FIGS. 9 to 11 will be described. Of the blocks 1 to N shown in FIG. 9, only one is activated during the read operation.
Individual. In the activated block, one of the word lines WL0 to WLi shown in FIGS. 10 and 11 is selected and the memory cell MC connected thereto is selected, and each bit line shown in FIG. Vs. BL0, / BL0
The data stored in BLj and / BLj is read. At this time, only one of the column selection signals YD0 to YDj is selected, and the corresponding bit line pair BL, / BL is set to I
Connected to O line pair IO, / IO. In this way, data of one cell of memory cell arrays MA1 to MA16 of each of IO1 to 16 is read out to IO line pair, and this data is amplified by sense amplifier SA and output to data bus signal line RD. You. In FIG. 10, the operation of each of IOs 1 to 16 in each block is independent, and the stored data is read out by each of IOs 1 to 16 and amplified by each of sense amplifiers SA1 to SA16, and the corresponding data bus The signal is transmitted to signal lines RD1 to RD16.
Note that, except for the activated block, all word lines are unselected, and data in the memory cells is not read.
In addition, since the sense amplifiers do not operate, the sense amplifier outputs of the number of blocks are connected to the data bus signal line RD, but only the sense amplifiers of the activated blocks output data. Focusing on one of the data bus lines, as shown in FIG. 12, the output signal of the sense amplifier corresponding to the activated block is transmitted to the data bus signal line, and the output signal provided near the input / output pad is provided. It reaches buffer c. The signal is further amplified by the output buffer c and output to the outside via the input / output pad d.

[0007]

Since the conventional semiconductor memory device is configured as described above, if the storage capacity increases and the chip area increases, the number of memory cells connected to one bit line increases. Therefore, there is a problem that the load capacity of the bit line increases and access is delayed. Further, an increase in the chip area leads to an increase in the length of the data bus line, resulting in an increase in the load capacity of the data bus line, and a problem that access is delayed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has been made in consideration of a center power pin type multi-I.
It is an object of the present invention to provide a semiconductor memory device capable of increasing the storage capacity and reducing the load capacity of the bit line and the data bus line in the case of the O configuration.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor memory device including four data input / output pin groups and four data input / output pin groups.
Including one mat. Four data input and output pin group includes a plurality of data input and output pins for each is input by 4 dividing the multi-bit data. In the four mats, the memory cell array is divided into two in the word line direction and two in the bit line direction. Each of the mats is connected to a data input / output pin group closest to the mat among the four data input / output pin groups, and reads / divides the multi-bit data divided into four.
Write. Semiconductor memory devices include power pads and ground pads.
And four data input / output pad groups.
Power pad, ground pad and four data input / output pads
The power supply group is located at the center of the main surface of the rectangular chip.
Pins, ground pins and four data input / output pin groups
Provided. Power pad, ground pad and four
Data input / output pads are placed above these corresponding pins.
Are connected by the wiring which is connected. Each mat is a chip
Are arranged at the center of the
The data closest to the corresponding mat in the data input / output pad group
Data bus connected to the data input / output pad group, chip length
Including word lines parallel to the sides and bit lines parallel to the short sides
Memory cell array area, memory cell array area and data
Between the bus and the memory cell array area
Amplifier that amplifies the data and gives it to the data bus
And memory cell array
Including the bit line load connected to the bit line in the region A.

A semiconductor memory device according to a second aspect of the present invention
It includes four data input / output pin groups and four mats.
The four data input / output pin groups are arranged on both sides of the power supply and ground pins, and each have a plurality of data input / output pin groups for dividing and inputting multi-bit data into four parts. In the four mats, a memory cell array having a bit line parallel to the long side of the chip and a word line parallel to the short side of the chip is divided into two in the bit line direction and two in the word line direction.
Each mat performs reading / writing of multi-bit data divided into four parts connected to the data input / output pin group closest to the mat among the four data input / output pin groups .

[0011]

According to the first aspect of the present invention, the length of the bit line is shortened by dividing the memory cell array in the bit line direction, and the number of memory cells connected to one bit line is reduced. And the access speed is improved. Further, by dividing the memory cell array into two in the word line direction, the length of the data bus is shortened, so that the load capacity of the data bus is reduced and the access speed is improved. Moreover, since the data stored in each mat is output through the data input / output pad group provided at the position closest to the mat, the access speed is also improved in this respect.

According to a second aspect of the present invention, a memory cell array having a bit line parallel to the long side of the chip and a word line parallel to the short side of the chip is divided into two in the bit line direction and two in the word line direction. I have. By doing so, claim 1
Since the load capacity of the bit line is reduced by half and the length of the data bus is reduced by half, the access speed is improved. The data bus line is shorter than the semiconductor memory device according to the first aspect, but the bit line is longer.

[0013] Each mat of claim 2 in the invention of claim 3, which is divided into two in the bit line direction. By doing so, the length of the bit line of each mat is halved, so that the load capacity of the bit line is reduced and the access speed is improved .

[0014]

Embodiment 1 An embodiment of the present invention will be described below with reference to the drawings. FIG.
Is a semiconductor memory device showing one embodiment of the present invention.
In FIG. 1, generally, the vertical direction is the short side of the chip 100, and the horizontal direction is the long side of the chip 100. The squares arranged on the long sides of the chip included in the peripheral circuit 101 are pads,
V is a power supply pad, G is a ground pad, DQ1 to DQ1
Reference numeral 6 denotes a plurality of input / output pads. The power supply pad V, the ground pad G, and the input / output pads DQ1 to DQ16 are connected to external pins provided on the long side of the chip.

As shown in FIG. 1, in the center power pin system, a power supply pin Vcc and a ground pin GND are arranged at the center, and a power supply pad V and a ground pad G are
Generally, one chip is arranged at the center of the long side of the chip 100, and the input / output pads DQ1 to DQ16 are generally arranged on both sides of these pads V and G. In this embodiment, the memory cell array 102
Is divided into two in the short side direction, and in each area,
The bit line load BT is placed at the center of the chip,
Are arranged on the outer peripheral side of the chip. The memory cell array 102 is also divided into two in the chip long-side direction, and is divided into four mats A to D in all parts. In this embodiment, the number of data that can be simultaneously input and output is 16 as in the conventional example.
Therefore, each of the mats A to D shares four IOs out of the 16 IOs. Each of the mats A to D is further divided into N blocks, and the structure of these blocks is basically the same as the block of FIG. 9, but the blocks 1 to N of FIG.
1 differs from the block of FIG. 1 in that it includes only 4 of the 16 IOs. Further, the memory cell array 102
However, since the memory cell is divided into two in the short side direction of the chip, the number of memory cells in the vertical direction is reduced by half and the number of word lines is reduced by half in the same storage area. RD1 to RD16
Is a data bus signal line, but unlike the conventional example, data bus signal lines RD1 to RD16 are RD1 to RD4, RD5
RD8, RD9 to RD12, and RD13 to RD16, which are divided into four sets and are located on the side of the sense amplifiers SA of the mats A to D which respectively handle the corresponding IOs.
Therefore, in this embodiment, four data bus lines are arranged on the sense amplifier side of each region.

FIG. 2 shows one of the data bus lines of FIG. 1 which belongs to mats A and B one by one (for example, R
D1 and RD5) and their connections. In the figure, a to N are the sense amplifier outputs of the mat A, b is one of the data bus lines corresponding to the mat A, c is the corresponding output buffer, and d is the input / output pad. Right'
Are added by the mat B. The ends of the data bus lines b and b 'are connected to input / output pads d and d' via output buffers c and c '. FIG.
Although basically the same as FIG. 12, the data bus line in FIG. 12 has almost the same length as the long side of the chip. Lines b and b 'correspond to the length of each mat, and the length is １ ／ of that of the conventional example.

FIG. 3 is a diagram showing a specific configuration of one of the mats shown in FIG. Since the configuration of each mat is the same, only the configuration of mat A is shown as a representative example.
The configuration of the IOs 1 to 4 shown in FIG.
1, and includes a bit line load (not shown), a memory cell array, a transfer gate, and a sense amplifier. In the present embodiment, the block of each mat includes four IOs as shown in FIG. 3, and the outputs of the sense amplifiers of each IO correspond to the corresponding data bus signal lines RD1 to RD4.
Connected to. Note that one set of X decoders for decoding the word lines WL0 to i is required for each mat.
FIG. 4 is a diagram showing an example of the positional relationship between the pad and the peripheral circuit 101 in FIG. 1. In this example, the pad is arranged on the outermost periphery of the chip and the peripheral circuit 101 is located inside the chip.
There is. However, this is only an example, and, for example, the peripheral circuit 101 may be arranged between the pads, and it is not always necessary to distinguish between the pad area and the peripheral circuit 101 area. FIG. 4 shows a typical example of a center power pin type pad arrangement. 4, G denotes a ground pad, V denotes a power supply pad, DQ1 to DQ4 denote input / output pads, and A0 and A1 denote address pads or control pads. The boundary of the mat is at the center of the chip, that is, between the ground pad G and the power supply pad V.

The operation of this embodiment is basically the same as the operation of the conventional example shown in FIG. However, in FIG.
Although only one of the N blocks is activated, in this embodiment, since each of the mats A to D is in charge of a separate IO, one of the N blocks is Activate one by one. That is, four blocks are activated simultaneously. However, since each block is responsible for 4 IOs, the number of IOs that are activated simultaneously is 1 as in the conventional example.
There are six. The data flow from each block to the input / output pad is the same as in the conventional example. Embodiment 2 FIG. 5 is a view showing another embodiment of the present invention, and each symbol in FIG. 1 is the same as in FIG. In this embodiment, the LOC
This is suitable for a chip having a structure (lead-on-chip), and pads V, G and DQ are present in the center of the chip. In this case, a configuration in which the sense amplifier side is directed to the center of the chip as shown in FIG. 5 is effective. Also in the case of such a configuration, the length of the bit line and the length of the data bus line are both halved as compared with the related art, and the same effect as in the first embodiment can be obtained. The operation is exactly the same as in FIG. Embodiment 3 FIG. 6 is a diagram showing another embodiment of the present invention. The semiconductor memory device shown in FIG. 6 is different from the semiconductor memory device shown in FIG. 1 in that a memory cell array having a bit line parallel to the long side of the memory chip and a word line parallel to the short side of the chip is two-dimensionally arranged in the bit line direction. That is, four mats that are divided and divided into two in the word line direction are provided, and each mat is further divided into two in the bit line direction. By doing so, the length of the bit line can be further reduced, and the load capacity of the bit line decreases. The operation is almost the same as that of FIG. 1. However, in FIG. 6, since the inside of the mat is divided into two, the number of I / Os included in each block is set to 4 as in FIG. In addition to the method of starting only one block, there is a method of starting up two blocks in the mat at the same time (block 1A and block 2A, etc.) with the number of I / Os included in each block being two.

FIGS. 7 and 8 show the structure of one mat in FIG. 6. When the number of I / Os contained in each block is four, as shown in FIG. Data is read to the data bus signal lines RD1 to RD4 by activating one of the blocks 1, 2 and the like. When the number of I / Os included in each block is set to 2, two opposite blocks such as blocks 1A and 2A or 3A and 4A are simultaneously activated as shown in FIG. , Data bus signal line RD
Data is read out from 1 to 4.

[0020]

As described above, according to the first and second aspects of the present invention, since the memory cell array is divided into two in the word line direction and two in the bit line direction, the bit lines and the data bus lines are divided. Since it can be shortened, the load capacity of the bit line and the data bus can be reduced,
This has the effect of improving access time.

According to the third aspect of the present invention, since each mat can be divided into two in the bit line direction, the load capacity of the bit line can be further reduced, and the access time can be improved accordingly .

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a diagram showing two data bus lines shown in FIG. 1 and a portion connected thereto.

FIG. 3 is a diagram showing a configuration of each mat shown in FIG. 1;

FIG. 4 is a diagram illustrating an example of a positional relationship between a peripheral circuit and a pad illustrated in FIG. 1;

FIG. 5 is a diagram showing a configuration of a semiconductor memory device according to another embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a semiconductor memory device according to another embodiment of the present invention.

FIG. 7 is a diagram showing an example of the configuration of each mat shown in FIG. 6;

8 is a diagram showing another example of the configuration of each mat shown in FIG.

FIG. 9 is a diagram showing a configuration of a conventional semiconductor memory device.

FIG. 10 is a diagram illustrating a configuration of each block illustrated in FIG. 9;

11 is a diagram showing a specific configuration of the IO shown in FIG.

12 is a diagram showing one of the data bus lines shown in FIG. 9 and a portion connected thereto.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 chip 101 peripheral circuit 102 memory cell array A to D mat G ground pad V power supply pad Vcc power supply pin RD1 to RD16 read data bus

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/10 G11C 11/41 JICST file (JOIS)

Claims (3)

(57) [Claims] And 1. A power and ground pins, a semiconductor memory device including a memory cell array for storing multi-bit data, each is for input and output is divided into four data of said multi-bit and four data output pin group having a plurality of data input and output pins, the memory cell array is divided into two in the word line direction, and a four mats are divided into two bit line direction, each of said mat, the is connected to the closest data input pin group of the four data input and output pin group, the four divided had row read / write multi-bit data, the semiconductor memory device, the rectangular chip In the main face of
The power pin, ground pin and four data inputs
Provided corresponding to the output pin group, these corresponding pins
A power supply pad connected by a wiring provided above,
Additional ground pad and four data input / output pad groups
Wherein each of the mats is arranged on the center side of the chip and parallel to the word lines.
Corresponding to one of the four data input / output pad groups.
Data connected to the data input / output pad group closest to the
Tabus, word lines parallel to the long sides of the chip and parallel to the short sides.
A memory cell array area including bit lines, and a memory cell array area provided between the memory cell array area and the data bus.
And the data stored in the memory cell array area is
Sense amplifier means for amplifying and providing to the data bus;
Is disposed on the outer peripheral side of the pre said chip, said Memoriserua
Including bit line loads connected to the bit lines in the lay region;
Semiconductor storage device. (2)Rectangular shapeChipsTwoCenter of long side
partToOne pair at a timePower and ground deployedPad pair
And the bit line parallel to the long side of the chip and the short side of the chip.
Memory having row word lines and storing multi-bit data
A semiconductor memory device comprising a cell array,Along the long side, Power and groundPad pair
Two eachAre arranged, each with multi-bit data.
Multiple data input / output that input / output in quadrantpadHave
4 data input / outputpadThe memory cell array is divided into two in the bit line direction,
And four mats divided into two in the data line direction.padSwarm
Nearest data input / outputpadConnected to the group, said 4
Reading / writing of divided multi-bit data
A semiconductor memory device characterized by the above-mentioned. 3. Each of the mats includes two regions divided in a bit line direction, each of the two regions being a memory cell array region having a rectangular shape and the memory cell array being parallel to the word line. A bit line load disposed on one side of the region, and a bit line load on the other side of the memory cell array region opposite to the one side.
Data arranged and stored in the memory cell array area
3. The semiconductor memory device according to claim 2 , further comprising: a sense amplifier for amplifying and outputting the data, and a data bus connected to said sense amplifier and arranged in parallel with said word line .