JP3348536B2 - Integrated circuit with self-heating suppression function - Google Patents
Integrated circuit with self-heating suppression functionInfo
- Publication number
- JP3348536B2 JP3348536B2 JP20925994A JP20925994A JP3348536B2 JP 3348536 B2 JP3348536 B2 JP 3348536B2 JP 20925994 A JP20925994 A JP 20925994A JP 20925994 A JP20925994 A JP 20925994A JP 3348536 B2 JP3348536 B2 JP 3348536B2
- Authority
- JP
- Japan
- Prior art keywords
- temperature
- integrated circuit
- circuit
- self
- suppression function
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
【0001】[0001]
【産業上の利用分野】この発明は、集積回路を発熱を抑
制しながら動作させるようにした自己発熱抑制機能付き
集積回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit having a self-heating suppressing function which operates an integrated circuit while suppressing heat generation.
【0002】[0002]
【従来の技術】LSI(大規模集積回路)の高集積化及
び高速クロック化に伴い、LSIの発熱を如何に抑制す
るかが問題となっている。従来、ECLを利用した大型
コンピュータでは、フロンやファンによりLSIを強制
的に冷却することが行われている。2. Description of the Related Art As the integration of LSIs (large-scale integrated circuits) and the speed of clocks increase, there is a problem of how to suppress heat generation of the LSIs. 2. Description of the Related Art Conventionally, in a large-scale computer using ECL, the LSI is forcibly cooled by a Freon or a fan.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、上述し
た従来の冷却方式では、何らかの故障によってファンが
停止したり、条件の厳しいところで設計限界を超えてし
まうと、システム全体がダウンして、動作に致命的な影
響を与えるという問題がある。この発明は、このような
問題点に鑑みなされたもので、自らが発熱を抑制しなが
ら動作する自己発熱抑制機能付き集積回路を提供するこ
とを目的とする。However, in the above-mentioned conventional cooling system, if the fan stops due to some kind of failure or exceeds the design limit in a severe condition, the whole system is down and operation is fatal. There is a problem that has a negative effect. The present invention has been made in view of such a problem, and an object of the present invention is to provide an integrated circuit with a self-heating suppressing function that operates while suppressing heat generation.
【0004】[0004]
【課題を解決するための手段】この発明に係る自己発熱
抑制機能付き集積回路は、キャッシュメモリを内蔵する
集積回路本体と、この集積回路本体の温度を検出する温
度検出手段と、この温度検出手段で検出された温度が予
め定めた設定範囲の上限値を越える場合には前記集積回
路本体に内蔵されたキャッシュメモリの機能を停止し、
温度が該設定範囲の下限値を下回ったら通常動作を実行
させる制御手段とを備えたことを特徴とする。According to the present invention, there is provided an integrated circuit having a self-heating suppressing function, an integrated circuit body having a built-in cache memory, temperature detecting means for detecting the temperature of the integrated circuit body, and the temperature detecting means. If the temperature detected in the above exceeds the upper limit of the predetermined set range, stop the function of the cache memory built in the integrated circuit body ,
Normal operation is performed when the temperature falls below the lower limit of the set range.
And control means for causing
【0005】[0005]
【作用】この発明によれば、温度検出手段が集積回路本
体の温度を検出し、この温度が予め定めた設定範囲を超
えると、制御手段が前記集積回路本体の少なくとも一部
の動作を制限するので、集積回路が自ら発熱を抑制する
ように動作し、結果的に集積回路の温度を所定の温度範
囲内に抑えることが可能になる。According to the present invention, the temperature detecting means detects the temperature of the integrated circuit main body, and when the temperature exceeds a predetermined set range, the control means restricts the operation of at least a part of the integrated circuit main body. Therefore, the integrated circuit operates to suppress heat generation by itself, and as a result, the temperature of the integrated circuit can be suppressed within a predetermined temperature range.
【0006】[0006]
【実施例】以下、図面を参照して、この発明の実施例を
説明する。図1は、この発明の一実施例に係る自己発熱
抑制機能付き集積回路の構成を示すブロック図である。
図において、1は発熱抑制対象となるCPU本体であ
り、このCPU本体1には高速動作実現のためのキャッ
シュメモリ2等が接続されている。CPU本体1と同一
集積回路内には、温度センサ3が設けられている。温度
センサ3は、チップの温度を検出し、その検出結果をク
ロック・周辺回路コントロール回路4に供給する。一
方、温度設定回路5には、チップの外部から設定された
動作温度上限値及び下限値が保持されており、この設定
値も、クロック・周辺回路コントロール回路4に供給さ
れている。なお、この設定値は、例えば外部からRA
M、不揮発性RAM、ヒューズROM、レーザトリミン
グ等で設定することができる。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an integrated circuit with a self-heating suppression function according to one embodiment of the present invention.
In the figure, reference numeral 1 denotes a CPU main body which is a target for suppressing heat generation, and a cache memory 2 and the like for realizing high-speed operation are connected to the CPU main body 1. A temperature sensor 3 is provided in the same integrated circuit as the CPU body 1. The temperature sensor 3 detects the temperature of the chip and supplies the detection result to the clock / peripheral circuit control circuit 4. On the other hand, the temperature setting circuit 5 holds an operating temperature upper limit value and a lower limit value set from outside the chip, and these set values are also supplied to the clock / peripheral circuit control circuit 4. Note that this set value is, for example,
M, nonvolatile RAM, fuse ROM, laser trimming, and the like.
【0007】クロック・周辺回路コントロール回路4
は、温度センサ3で検出された温度が温度設定回路5で
設定された上限値及び下限値の間にコントロールされる
ように、集積回路の動作を制御する。具体的には、クロ
ック・周辺回路コントロール回路4は、チップの温度が
上限値を超えた場合に、PLL(位相固定ループ)6に
クロック信号CKの周波数を下げるように指示したり、
キャッシュメモリ2の機能を停止させる。これにより、
CPU本体1の処理速度は犠牲にすることになるが、発
熱量は抑制することができる。また、クロック・周辺コ
ントロール回路4は、外部回路やOS(オペレーション
・システム)、更にはCPU本体1に、動作制限状態で
あることを示す信号を出力する。これにより、外部回路
やCPU本体1に割込等がかかり、これらの回路では動
作制限中の処理に切り換わる。また、クロック・周辺回
路コントロール回路4は、温度が下限値を下回ったら、
動作制限を解除して通常動作を実行させる。Clock / peripheral circuit control circuit 4
Controls the operation of the integrated circuit such that the temperature detected by the temperature sensor 3 is controlled between the upper limit value and the lower limit value set by the temperature setting circuit 5. More specifically, the clock / peripheral circuit control circuit 4 instructs the PLL (phase locked loop) 6 to reduce the frequency of the clock signal CK when the temperature of the chip exceeds the upper limit,
The function of the cache memory 2 is stopped. This allows
Although the processing speed of the CPU body 1 is sacrificed, the amount of heat generated can be suppressed. In addition, the clock / peripheral control circuit 4 outputs a signal indicating that the operation is in a restricted state to an external circuit, an OS (operation system), and the CPU body 1. As a result, an interrupt or the like is interrupted in the external circuit or the CPU main unit 1, and the processing is switched to the operation-restricted processing in these circuits. When the temperature falls below the lower limit, the clock / peripheral circuit control circuit 4
Release the operation restriction and execute the normal operation.
【0008】温度センサ3は、集積回路がバイポーラL
SIであれば、温度/電流特性が正の特性を持っている
ので、特定の部分の電流値を測定したり、例えば図2に
示すように、拡散層11の両端抵抗値等を測定すること
により、温度検出することができる。また、集積回路が
MOSである場合には、例えば図3に示すように、縦続
接続されたインバータゲート21,22,23からなる
発振回路24の出力をタイマ25で規定された一定時間
だけカウンタ26でカウントしたカウント値を用いるよ
うにしても良い。なお、タイマ25は、温度に関わりな
く一定周期の基準クロックCK0によって駆動される。
この場合、温度上昇に伴ってトランジスタのスイッチン
グ時間が低下して発振回路24の発振周波数が低下する
ので、カウンタ値は温度と反比例した値となる。このよ
うにチップ内に温度センサを作り込むことにより、チッ
プ内部の温度を正確に把握することができる。The temperature sensor 3 has an integrated circuit of a bipolar L
In the case of SI, since the temperature / current characteristic has a positive characteristic, it is necessary to measure the current value of a specific portion or, for example, to measure the resistance value at both ends of the diffusion layer 11 as shown in FIG. Thus, the temperature can be detected. When the integrated circuit is a MOS, for example, as shown in FIG. 3, the output of an oscillation circuit 24 composed of cascade-connected inverter gates 21, 22, 23 is output to a counter 26 for a predetermined time defined by a timer 25. May be used. Note that the timer 25 is driven by the reference clock CK0 having a constant cycle regardless of the temperature.
In this case, the switching time of the transistor decreases as the temperature rises, and the oscillation frequency of the oscillation circuit 24 decreases. Therefore, the counter value becomes a value inversely proportional to the temperature. By forming the temperature sensor in the chip as described above, the temperature inside the chip can be accurately grasped.
【0009】以上の集積回路によれば、図4に示すよう
に、チップ自らその温度を予め設定された上限値及び下
限値の間に抑えるように動作をする。従って、他の冷却
手段を用いなくても、また、他の冷却手段と併用するこ
とにより、集積回路の発熱を効果的に抑制することがで
きる。According to the above integrated circuit, as shown in FIG. 4, the chip itself operates to keep its temperature between a preset upper limit value and a preset lower limit value. Therefore, the heat generation of the integrated circuit can be effectively suppressed without using any other cooling means or by using it in combination with another cooling means.
【0010】[0010]
【発明の効果】以上述べたように、この発明によれば、
温度検出手段が集積回路本体の温度を検出し、この温度
が予め定めた設定範囲を超えると、制御手段が前記集積
回路本体の少なくとも一部の動作を制限するので、集積
回路が自ら発熱を抑制するように動作し、結果的に集積
回路の温度を所定の温度範囲内に抑えることが可能にな
る。As described above, according to the present invention,
The temperature detecting means detects the temperature of the integrated circuit main body, and if the temperature exceeds a predetermined set range, the control means restricts at least a part of the operation of the integrated circuit main body. As a result, the temperature of the integrated circuit can be suppressed within a predetermined temperature range.
【図1】 この発明の一実施例に係る自己発熱抑制機能
付き集積回路のブロック図である。FIG. 1 is a block diagram of an integrated circuit with a self-heating suppression function according to an embodiment of the present invention.
【図2】 同回路における温度センサの一例を示す図で
ある。FIG. 2 is a diagram illustrating an example of a temperature sensor in the circuit.
【図3】 同回路における温度センサの他の例を示すブ
ロック図である。FIG. 3 is a block diagram showing another example of the temperature sensor in the same circuit.
【図4】 同回路の温度の時間的変化を示すグラフであ
る。FIG. 4 is a graph showing a temporal change in temperature of the circuit.
1…CPU本体、2…キャッシュメモリ、3…温度セン
サ、4…クロック・周辺回路コントロール回路、5…温
度設定回路、6…PLL、21…動作温度測定回路、2
2…クロック選択回路、23…変化検出回路。DESCRIPTION OF SYMBOLS 1 ... CPU main body, 2 ... Cache memory, 3 ... Temperature sensor, 4 ... Clock / peripheral circuit control circuit, 5 ... Temperature setting circuit, 6 ... PLL, 21 ... Operating temperature measurement circuit, 2
2. Clock selection circuit 23: Change detection circuit
Claims (1)
体と、 この集積回路本体の温度を検出する温度検出手段と、 この温度検出手段で検出された温度が予め定めた設定範
囲の上限値を越える場合には前記集積回路本体に内蔵さ
れたキャッシュメモリの機能を停止し、温度が該設定範
囲の下限値を下回ったら通常動作を実行させる制御手段
とを備えたことを特徴とする自己発熱抑制機能付き集積
回路。An integrated circuit body having a built-in cache memory; temperature detecting means for detecting a temperature of the integrated circuit body; and a case where the temperature detected by the temperature detecting means exceeds an upper limit value of a predetermined set range. Stops the function of the cache memory built in the integrated circuit body, and the temperature falls within the set range.
A control means for executing a normal operation when the value falls below a lower limit value of the box .
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20925994A JP3348536B2 (en) | 1994-08-10 | 1994-08-10 | Integrated circuit with self-heating suppression function |
US08/508,975 US5723998A (en) | 1994-08-10 | 1995-07-28 | Electronic circuit with operation self-control function |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20925994A JP3348536B2 (en) | 1994-08-10 | 1994-08-10 | Integrated circuit with self-heating suppression function |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0855963A JPH0855963A (en) | 1996-02-27 |
JP3348536B2 true JP3348536B2 (en) | 2002-11-20 |
Family
ID=16569996
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20925994A Expired - Fee Related JP3348536B2 (en) | 1994-08-10 | 1994-08-10 | Integrated circuit with self-heating suppression function |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3348536B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3181219B2 (en) * | 1996-02-06 | 2001-07-03 | トヨタ自動車株式会社 | Electric heating type catalyst device |
JP2000269417A (en) | 1999-03-16 | 2000-09-29 | Toshiba Corp | Semiconductor device |
US8472278B2 (en) * | 2010-04-09 | 2013-06-25 | Qualcomm Incorporated | Circuits, systems and methods for adjusting clock signals based on measured performance characteristics |
JP5738141B2 (en) * | 2011-09-20 | 2015-06-17 | ルネサスエレクトロニクス株式会社 | Semiconductor device and temperature sensor system |
JP6507672B2 (en) * | 2015-01-27 | 2019-05-08 | 株式会社ソシオネクスト | Semiconductor integrated circuit device and test method of semiconductor integrated circuit device |
-
1994
- 1994-08-10 JP JP20925994A patent/JP3348536B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0855963A (en) | 1996-02-27 |
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