JP3348325B2 - Silicon-based material wiring structure and patterning method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a silicon-based material wiring used for an internal wiring of a semiconductor device and a method of patterning the same, and more particularly, to a wiring for forming on a base interlayer insulating film having a step. The present invention relates to a structure of a silicon-based material wiring capable of preventing a shape abnormality and a patterning method thereof.

[0002]

2. Description of the Related Art At the same time as the design rules of semiconductor devices such as LSIs are miniaturized from half micron to quarter micron, multi-layer wirings of several layers are employed. It is getting more severe. As an example, a problem in the case of forming a silicon-based material layer such as polycrystalline silicon on a base interlayer insulating film having a high step due to the adoption of a multilayer wiring and patterning this to form a silicon-based material wiring, This will be described below.

A technical problem in patterning a silicon-based material layer formed on a high step underlying interlayer insulating film is that the thickness of a layer to be etched substantially increases in a high step portion. In order to completely remove the layer to be etched without generating a residue at the high step portion, excessive over-etching is required, which may cause an abnormal shape of the silicon-based material wiring. Figure 2 illustrates this problem.
This will be described with reference to (a) to (c).

A gate electrode 2 and a semiconductor substrate 1 such as Si
And an interlayer insulating film 3 are formed. ⁺Polycrystalline silicon
A silicon-based material layer 5 is formed. This silicon system
The thickness of the material layer 5 in the normal direction on the surface of the semiconductor substrate 1 is a step.
The thickness B of the portion is larger than the thickness A of the flat portion, and the thickness B is
About twice as large as This state is shown in FIG. One
A resist mask 6 is formed on the substrate, and the silicon-based material layer 5 is
Anisotropic etching to put silicon-based material wiring 5P
To synchronize. At this time, the silicon-based material layer in the flat portion is
At the time of the last etching, the silicon with a thick step
Material layer is not completely etched off and has sidewalls or
Remains as a string-shaped residue 5R. This state
It is FIG.2 (b). If the residue 5R is left as it is, a wiring short circuit etc.
Must be completely removed as it may cause device failure
There is. Conventionally, residue 5R has an
It was removed by performing bar etching.

However, high integration of semiconductor devices is progressing.
In the current situation in which each constituent material layer is thinned,
The underlying interlayer insulating film during the over-etching of the strength described
It is necessary to reduce damage and film loss of 3 as much as possible. But
What is SiO_TwoAnd Si_ThreeN_FourUnderlayer insulating film consisting of
At least over-etchin
At the time of fueling, instead of F-based gas, Cl-based gas or Br-based gas
And patterning with low ion incident energy
The way to do it is common. Cl radical (Cl ^*) Or B
r radical (Br^*) Is F^*Compared to SiO
_TwoAnd Si_ThreeN_FourLow reactivity and high selectivity
Because you can wait. As an example, HBr gas was used.
High selectivity etching of polycrystalline silicon
No. 4,502,915 and JP-A-2-224.
No. 241.

In the case where a Cl-based gas or a Br-based gas is adopted and a silicon-based material layer such as polycrystalline silicon on a stepped base is patterned under a condition of high selectivity, the following problems may occur. Confirmed by the inventor. That is,
Cl ^* or Br ^* , which is the main etchant at the time of overetching, is hardly consumed on the exposed surface of the underlying insulating film made of SiO ₂ or Si ₃ N ₄ . For this reason, Cl ^* or Br ^* etches the residue 5R and, at the same time, concentrates on the side surface of the patterned silicon-based material wiring 5P, causing a shape abnormality called notching indicated by reference numeral 8. This state is shown in FIG.
It is shown in (c). Such an undercut may lead to a change in the cross-sectional shape or cross-sectional area of the electrode / wiring, resulting in a change in device characteristics. 2A to 2C illustrate the case where a plurality of silicon-based material wirings are formed on the step protrusions and the step recesses, but extend in the left-right direction of the drawing.
A similar problem occurs when forming a silicon-based material wiring that crosses the step-shaped protrusion and the step-shaped recess.

[0007]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a silicon-based material layer on an interlayer insulating film which does not cause a shape abnormality such as notching even if strong over-etching is performed. An object of the present invention is to provide a silicon-based material wiring structure and a patterning method thereof.

Another object of the present invention is to provide a structure of a silicon-based material wiring which has excellent etching selectivity with respect to an underlying interlayer insulating film, does not reduce the thickness of the interlayer insulating film or is damaged, and a method of patterning the same. It is.

It is still another object of the present invention to provide a highly reliable silicon-based wiring structure and a patterning method thereof, which are free from short circuits due to string-like residues and fluctuations in device characteristics due to abnormal wiring shapes. It is. Problems other than the above of the present invention will become apparent from the description of the present specification and the description of the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION A silicon-based material wiring structure according to the present invention has been proposed in order to solve the above-mentioned problems, and includes a silicon-based material wiring structure including a structure in which a silicon-based material wiring is formed on an interlayer insulating film. Based material wiring structure, silicon
In the region where the silicon-based material wiring is formed, a silicon oxynitride (SiO _x N _y : H) layer is formed between the interlayer insulating film and the silicon-based material wiring ,
In areas other than the area where the copper-based material wiring layer is formed, water
The silicon oxynitride (SiO _x N _y : H) layer is removed
A silicon-based wiring structure.

The thickness of the hydrogenated silicon oxynitride layer is 5 nm.
It is desirable that the thickness be at least 30 nm. This silicon oxynitride layer can be formed by plasma CVD.

[0012] silicon-based material wire for use in the present invention, polycrystalline silicon, amorphous silicon, WSi _x and MoSi _x
And the like, and Si as a constituent element or a main constituent element, such as a high melting point metal silicide and a high melting point metal polycide. Of course, impurities such as n-type and p-type may be included.

Also, the present invention provides a silicon-based material wiring pattern.
The wiring method is that silicon-based material wiring is formed on the interlayer insulating film.
Patterning method for the formed silicon-based material wiring.
hand,Silicon oxynitride (SiO 2)
_x N _y : H) forming a layer and silicon oxynitride
(SiO _x N _y : H) Forming a silicon-based material layer on the layer
Process and silicon-based material using resist mask as a mask
Just etching the material layer and just etching
Following the etching, remove the residue of the silicon-based material layer.
In the bar etching process, the hydrogenated oxynitride silicon
(SiO _x N _y : Oxygen sputtered out of the H) layer
Of the sidewall protective film at the time of patterning the silicon-based material layer.
It is patterned as a part of the constituent material,
Forming a silicon-based material wiring including a step of forming a material wiring.
It is a turning method.

At the time of over-etching, Cl-based
Etching containing either gas or Br-based gas
It is desirable to perform over-etching with gas.
No. Here, as the Cl-based gas, Cl-_Two, HCl, BC
l_Three, CCl_FourAnd SiCl _FourGas containing Cl atoms
Can be used arbitrarily. As the Br-based gas, B
r_Two, HBr BBr_Three, CBr_FourAnd SiBr_Fouretc
A gas containing Br atoms can be used arbitrarily. These gases
They may be used alone or in combination. Also as an additive gas
And H_Two, N_Two, O_TwoOr a mixture of rare gases
No.

[0015]

The point of the present invention is that SiO ₂ or Si ₃
5 nm or more and 30 nm formed by plasma CVD between an interlayer insulating film made of N ₄ or the like and a silicon-based material layer.
The point is that the following thin SiO _x N _y : H layer is formed.

SiO _x formed by plasma CVD
The N _y : H layer is generally richer in Si than the stoichiometric composition of silicon oxynitride (SiON), and therefore has low resistance to Cl-based gas or Br-based gas plasma and is easily etched. At this time, active oxygen radicals (O ^* ) are released. Therefore, at the time of over-etching, S
iO _x N _y: the H layer is exposed begins O ^* is generated at the same time, O ^* concentration on the etched substrate vicinity is high.

For this reason, the side wall portion of the silicon-based material wiring which is not subjected to ion bombardment during over-etching is oxidized, and a SiO _x -based side wall protective film is formed.

Further, a Cl-based gas may be used as an etching gas.
Or when using a Br-based gas, these etching gases
Reaction product with SiCl_xO_yOr SiBr
_xO _yA side wall protective film of the system is deposited and formed. These side walls
The protective film is made of a patterned silicon material.
Protect wiring side walls from radical attack, notching, etc.
No shape abnormality occurs. For this reason,
Perform bar etching to sufficiently remove residue at the step
It becomes possible. Also, Cl-based gas or Br-based gas is
It has low reactivity to the interlayer insulating film, and
The selection ratio of the switching is large, and the interlayer insulation
Can be prevented.

The SiO _x N _y : H used in the present invention
Since the layer only needs to function as an O ^* source during the overetching period, the layer thickness may be small and may be 5 nm.
A thickness of not less than 30 nm and usually about 10 nm is sufficient. If it is less than 5 nm, it may be etched off during over-etching and the shape abnormality may not be sufficiently avoided. If it exceeds 30 nm, it may remain on the interlayer insulating film even after over-etching. Si
O _x N _y: H layer contains a large amount of Si and H, not necessarily suitable material as a constituent material of the interlayer insulating film. However, even if it remains, it is easy to improve the film quality by annealing or to remove it by light etching with a dilute hydrofluoric acid aqueous solution or the like.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific embodiment of the present invention will be described below with reference to FIGS. In the following embodiment, as in the case of referring to the description of the prior art, when patterning n ⁺ polycrystalline silicon formed on a high step underlying interlayer insulating film, an SiO _x N _y : H layer is used as an interlayer insulating film. The structure inserted between the silicon-based material layer and the silicon-based material layer will be described as an example.

Embodiment 1 A semiconductor substrate 1 made of Si or the like having an active element (not shown) such as an impurity diffusion layer formed thereon and a thermal oxide film of 10 nm formed on the surface thereof.
A gate electrode 2 of refractory metal polycide made of n ⁺ polycrystalline silicon and refractory metal silicide is formed thereon. The thickness of the gate electrode 2 is 200 nm in total for both layers. Next, an interlayer insulating film 3 made of SiO ₂ is formed to a thickness of 300 nm under the following plasma CVD conditions. TEOS 500 sccm O ₂ 1000 sccm Gas pressure 5 Pa RF power 200 W (13.56 MH
z) Substrate temperature to be processed 40 ° C

Next, the feature of the present invention, SiO,
_{The xNy} : H layer 4 is deposited under the following plasma CVD conditions as an example. SiH ₄ 50 sccm N ₂ O 25 sccm Gas pressure 5 Pa RF power 200 W (13.56 MH)
z) Temperature of substrate to be processed: 360 ° C. SiO _x N _y obtained by formation under the present plasma CVD conditions:
The composition of the H layer 4 is Si 42.4 at. % O 31.3 at. % N 9.3 at. % H 17.0 at. % Met.

Subsequently, under the following LPCVD conditions, a silicon-based material layer 5 composed of an n ⁺
m. SiH ₄ 500 sccm PH ₃ 0.3 sccm Gas pressure 100 Pa Substrate temperature 500 ° C. The silicon-based material layer 5 has a step of about 200 nm reflecting the thickness of the gate electrode 2. Further, a resist mask 6 is formed on the silicon-based material layer 5. The resist mask 6 is formed to have a width of, for example, 0.35 nm by using a negative chemically amplified resist and KrF excimer laser lithography. FIG. 1A is a schematic cross-sectional view of the substrate to be processed formed so far.

A substrate to be processed having the structure shown in FIG. 1A is set on a substrate stage of a substrate bias applying type ECR plasma etching apparatus, and as an example, the silicon-based material layer 5 is patterned under the following conditions. Cl ₂ 75 sccm O ₂ 5 sccm Gas pressure 0.4 Pa Microwave power 850 W (2.45 GHz) RF bias power 70 W (13.56 MH)
z) Substrate temperature to be processed: 20 ° C. At the time of the just etching in the main etching step, the residue 5R of the silicon-based material layer 5 as shown in FIG.
Remains on the step portion of the interlayer insulating film 3. At the same time, the exposed surface of the SiO _x N _y : H layer 4 is exposed to plasma and starts to generate active O ^* .

Subsequently, over-etching is performed under the same etching conditions as described above. In this over-etching step, at the same time when the residue 5R is removed, SiO _x N
_y : The H layer 4 is also etched off, and an oxidized local atmosphere is formed on the surface of the substrate to be processed by the released O ^* . Thus, SiO _x or SiO _x Cl _y on the sidewalls of the silicon-based material wire 5P that is already patterned
A sidewall protection film 7 made of the same is formed to protect the side surface of the silicon-based material wiring 5P from Cl ^* attack. Therefore, no shape abnormality such as notching or side etching occurs. Further, since the interlayer insulating film 3 made of SiO ₂ is hardly etched under the above-mentioned etching conditions, an etching selectivity of the interlayer insulating film with respect to the interlayer insulating film of about 50 or more is achieved. For this reason, there is no fear that the withstand voltage deteriorates due to a decrease in the thickness of the interlayer insulating film or damage. This state is shown in FIG.

After the etching, the substrate bias application type E
The wafer is transported to an ashing device connected to the CR plasma etching device, and the resist mask 6 is ashed. Subsequently, the sidewall protective film 7 is removed by light etching using, for example, a 100: 1 diluted hydrofluoric acid aqueous solution. Since there is no damage layer on the surface of the interlayer insulating film 5, the film of the interlayer insulating film is not reduced by the accelerated etching even at this stage. This state is shown in FIG.

According to the present embodiment, the silicon-based material layer on the interlayer insulating film having a high step can be formed under a single etching condition without causing any shape abnormality or residue, and causing loss of the underlying interlayer insulating film. Therefore, patterning can be performed with good controllability.

Embodiment 2 This embodiment is an example in which the same substrate to be processed as in Embodiment 1 is patterned by two-stage etching by over-etching using a Br-based gas, which is again shown in FIGS.
This will be described with reference to FIG.

This embodiment is the same as the first embodiment up to the substrate to be processed shown in FIG. 1A and the just etching step shown in FIG.

In the subsequent over-etching step, the etching conditions are changed to the following conditions as an example, and the residue 5R
Is removed. HBr 120 sccm O ₂ 4 sccm Gas pressure 1.0 Pa Microwave power 850 W (2.45 GHz) RF bias power 70 W (2 MHz) Substrate temperature to be processed 20 ° C. The etching conditions are switched by the emission of SiCl in plasma. This was the point in time at which the intensity of the resulting 250-260 nm emission spectrum began to decay.

In this over-etching step, at the same time as the residue 5R is removed, the SiO _x N _y : H layer 4 is also etched off, and the oxidized local atmosphere is generated on the surface of the substrate to be processed by the released O ^*. It is formed. As a result, a sidewall protective film 7 made of SiO _x or SiO _x Br _y is formed on the sidewall of the silicon-based material wiring 5P that has been already patterned, and protects the side surface of the silicon-based material wiring 5P from an attack of Br ^*. . Therefore, no shape abnormality such as notching or side etching occurs. Further, since the interlayer insulating film 3 made of SiO ₂ is hardly etched under the above-mentioned etching conditions, an etching selectivity of the interlayer insulating film with respect to the interlayer insulating film of about 200 or more is achieved. For this reason, there is no fear that the withstand voltage deteriorates due to a decrease in the thickness of the interlayer insulating film or damage. This state is shown in FIG.

After completion of the etching, a substrate bias application type E
The wafer is transported to an ashing device connected to the CR plasma etching device, and the resist mask 6 is ashed. The resist mask 6 may be removed by a wet method using a resist stripper. Subsequently, the sidewall protective film 7 is removed by light etching using, for example, a 100: 1 diluted hydrofluoric acid aqueous solution. Since there is no damage layer on the surface of the interlayer insulating film 5, the film of the interlayer insulating film is not reduced by the accelerated etching even at this stage. This state is shown in FIG.

According to this embodiment, a Br-based gas having a lower reactivity than a Cl-based gas is used for over-etching.
By performing the step etching, a higher selectivity to the interlayer insulating film than in Example 1 can be obtained. For this reason,
It is possible to pattern the silicon-based material layer on the high-level interlayer insulating film with good controllability without causing shape abnormality or residue and without causing loss of the underlying interlayer insulating film.

Although the present invention has been described with reference to two embodiments, the present invention is not limited to these embodiments.

For example, while the silicon-based material wiring or silicon-based material layer is made of n ⁺ polycrystalline silicon, Si is used as a constituent element or main material such as amorphous silicon, high melting point metal silicide, and high melting point metal layer polycide. The present invention can be applied to a conductive material having various constituent elements. Each of these material layers is a material that easily causes shape abnormality due to radical attack during over-etching.

Although Cl ₂ has been described as a representative example of the Cl-based gas, and HBr has been described as the Br-based gas, an etching gas containing Cl or Br as a constituent atom can be appropriately used as described above.

In each of the above-described embodiments, the description has been given of the prevention of the abnormal shape when the silicon-based material wiring is anisotropically etched into a rectangular shape. In addition to this object, the present invention can be applied to a case where a silicon-based material wiring is patterned into a forward tapered shape. In this case, a forward tapered silicon-based material wiring can be obtained by employing a condition where deposition of the sidewall protective film is large, for example, a condition in which the mixing ratio of the O ₂ gas in the etching gas is increased in the above-described embodiment. It is possible. Also in this case, it is possible to prevent a shape abnormality such as notching occurring at the time of over-etching. Such a forward-tapered wiring is used for a lower electrode and a wiring of a CCD image pickup device or the like, and is useful for improving the step coverage of an interlayer insulating film and an upper wiring.

As the etching apparatus, a substrate bias application type ECR plasma etching apparatus was used, but a parallel plate type RIE apparatus or a magnetron RIE apparatus may be used. Helicon wave plasma etching equipment, TCP (Tr
ansformer Coupled Plasma)
Etching equipment, ICP (InductivelyCo
If a high-density plasma etching apparatus such as an (upd Plasma) etching apparatus is used, further uniformity, low damage, a high etching rate, and the like in the substrate to be etched can be expected.

[0039]

As is apparent from the above description, according to the present invention, when a layer to be etched made of a silicon-based material layer is patterned, a shape abnormality such as notching occurs even if a strong over-etching is performed. Without
It has become possible to provide a structure of a silicon-based material wiring and a patterning method thereof.

Further, according to the present invention, it is possible to provide a silicon-based material wiring structure and a method of patterning the silicon-based material wiring which are excellent in etching selectivity with respect to an underlying interlayer insulating film and are not reduced or damaged in the interlayer insulating film. It became.

Still further, according to the present invention, there is provided a highly reliable silicon-based material wiring structure which is free from a short circuit caused by a string-like residue and a change in device characteristics due to an abnormal wiring shape, and a method of patterning the same. Became possible.

With these effects, it is possible to form a silicon-based material wiring used for a semiconductor device having a high step due to the adoption of a multilayer wiring with high reliability, and the present invention can be applied to a manufacturing process of a highly integrated semiconductor device. The contribution is great.

[Brief description of the drawings]

FIGS. 1A and 1B are schematic cross-sectional views illustrating a method of patterning a silicon-based material wiring according to Examples 1 and 2 to which the present invention is applied, in the order of steps, and FIG. 1A shows SiO _x on an interlayer insulating film having a step; A state in which an N _y : H layer and an n ⁺ polycrystalline silicon layer are formed, and further a resist mask is formed;
(B) is a state in which the n ⁺ polycrystalline silicon layer is just etched, (c) is a state in which residues are removed by overetching, and (d) is a state in which the resist mask is removed.

FIGS. 2A and 2B are schematic cross-sectional views illustrating problems in a conventional method of patterning a silicon-based material wiring in the order of steps, and FIG. 2A is a diagram in which an n ⁺ polycrystalline silicon layer is formed on an interlayer insulating film having a step; Further, a state in which a resist mask is formed, (b) is a state in which the n ⁺ polycrystalline silicon layer is just etched, and (c) is a state in which a residue is removed by overetching, in which a shape abnormality has occurred in the silicon-based material wiring. It is.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 gate electrode 3 interlayer insulating film 4 SiO _x N _y : H layer 5 silicon-based material layer 5P silicon-based material wiring 5R residue 6 resist mask 7 sidewall protection film 8 notching

Claims (7)

(57) [Claims] 1. A silicon-based material wiring structure including a structure in which a silicon-based material wiring is formed on an interlayer insulating film, wherein in a region where the silicon-based material wiring is formed,
Between the interlayer insulating film and the silicon-based material wire, hydrogen, acid silicon nitride: with (SiO _x N _y H) layer is formed, other than the silicon-based material wiring layer is formed regions odor
The silicon oxynitride (SiO _x N _y : H) layer
Wherein the silicon-based wiring structure is removed . 2. The thickness of the silicon oxynitride layer is 5n.
2. The silicon-based material wiring structure according to claim 1, wherein the thickness is not less than m and not more than 30 nm. 3. The method according to claim 1, wherein the hydrogenated silicon oxynitride layer is a plasma C
2. The silicon-based material wiring structure according to claim 1, wherein the silicon-based material wiring structure is formed by VD. 4. The silicon-based material wiring is at least one selected from the group consisting of polycrystalline silicon, amorphous silicon, refractory metal silicide, and refractory metal polycide.
The silicon-based material wiring structure according to claim 1, wherein the silicon-based material wiring structure is a seed. 5. A silicon-based material wiring is formed on an interlayer insulating film.
Patterning method for the formed silicon-based material wiring.
And saidSilicon oxynitride (SiO 2)
_x N _y : H) forming a layer; The hydrogenated silicon oxynitride (SiO _x N _y : H)
Forming a recon-based material layer; Using the resist mask as a mask, the silicon-based material layer
A step of just etching Following the just etching, the silicon-based material
In the over-etching process to remove the residue of the material layer
Is the silicon oxynitride (SiO 2) _x N _y : H)
Oxygen sputtered out from the silicon-based material layer
As a part of the constituent material of the sidewall protective film at the time of patterning
Patterning to form the silicon-based material wiring
Process Of silicon-based material wiring
Patterning method. 6. The method according to claim 5, wherein overetching is performed with an etching gas containing one of a Cl-based gas and a Br-based gas. 7. The silicon-based material layer is made of polycrystalline silicon,
6. The method according to claim 5, wherein the method is at least one selected from the group consisting of amorphous silicon, refractory metal silicide, and refractory metal polycide.