JP3347059B2 - Composite semiconductor device - Google Patents

Composite semiconductor device

Info

Publication number
JP3347059B2
JP3347059B2 JP14834998A JP14834998A JP3347059B2 JP 3347059 B2 JP3347059 B2 JP 3347059B2 JP 14834998 A JP14834998 A JP 14834998A JP 14834998 A JP14834998 A JP 14834998A JP 3347059 B2 JP3347059 B2 JP 3347059B2
Authority
JP
Japan
Prior art keywords
external lead
semiconductor device
out terminal
composite semiconductor
bonding wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP14834998A
Other languages
Japanese (ja)
Other versions
JPH11330344A (en
Inventor
永吾 福田
Original Assignee
日本インター株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本インター株式会社 filed Critical 日本インター株式会社
Priority to JP14834998A priority Critical patent/JP3347059B2/en
Publication of JPH11330344A publication Critical patent/JPH11330344A/en
Application granted granted Critical
Publication of JP3347059B2 publication Critical patent/JP3347059B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、複合半導体装置に関
し、特に絶縁ケースにインサートモールドした外部導出
端子の下端先端部にボンディングワイヤが確実にボンデ
ィングできるようにした複合半導体装置に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite semiconductor device, and more particularly to a composite semiconductor device in which a bonding wire can be securely bonded to a lower end portion of an external lead terminal inserted into an insulating case.

【０００２】[0002]

【従来の技術】従来のこの種の複合半導体装置の概略構
造について、図４を参照して説明する。図４は複合半導
体装置の絶縁ケースの一部を切断した断面図であり、本
発明を示す図１のＡ−Ａ線に沿う断面図に対応してい
る。図において、１は金属放熱板であり、この放熱板１
には所定の導体パターンが形成された絶縁基板２が固着
され、この絶縁基板２の導体パターン上に半導体チップ
４等の電子部品が搭載・固着されている。2. Description of the Related Art A schematic structure of a conventional composite semiconductor device of this type will be described with reference to FIG. FIG. 4 is a cross-sectional view of a part of the insulating case of the composite semiconductor device, which corresponds to a cross-sectional view taken along line AA of FIG. 1 showing the present invention. In the figure, reference numeral 1 denotes a metal radiator plate.
Is fixed to an insulating substrate 2 on which a predetermined conductor pattern is formed, and electronic components such as a semiconductor chip 4 are mounted and fixed on the conductor pattern of the insulating substrate 2.

【０００３】また、上記放熱板１の外周には、外部導出
端子５をインサートモールドした絶縁ケース３が被せら
れている。外部導出端子５の一端５Ａは、絶縁ケース３
の上部開口端から外部に導出され、他端５Ｂは、ボンデ
ィングワイヤをボンディングするための領域として一定
の範囲に亘って絶縁ケース３の底部表面に露出させてあ
る。そして、外部導出端子５の他端５Ｂの表面部と半導
体チップ４の表面電極とはボンディングワイヤ６により
ボンディングされている。The outer periphery of the heat sink 1 is covered with an insulating case 3 in which the external lead-out terminal 5 is insert-molded. One end 5A of the external lead-out terminal 5 is
And the other end 5B is exposed to the bottom surface of the insulating case 3 over a certain range as a region for bonding a bonding wire. The surface of the other end 5B of the external lead terminal 5 and the surface electrode of the semiconductor chip 4 are bonded by bonding wires 6.

【０００４】[0004]

【発明が解決しようとする課題】従来の複合半導体装置
は、上記のように外部導出端子５の他端５Ｂの表面部と
半導体チップ４の表面電極とは、ボンディングワイヤ６
によりボンディングされるが、かかる場合、ボンディン
グ機械により超音波振動を与えながらボンディングして
いる。その際、インサートモールドされた外部導出端子
５の他端５Ｂは、絶縁ケース３の底部表面に露出してい
て絶縁ケース３への付着が不十分であるために、超音波
振動を与えるボンディング機械のアームと共に共振して
しまい、ボンディングが不十分になるおそれがあった。As described above, in the conventional composite semiconductor device, the surface portion of the other end 5B of the external lead-out terminal 5 and the surface electrode of the semiconductor chip 4 are connected to the bonding wire 6
In such a case, bonding is performed while applying ultrasonic vibration by a bonding machine. At this time, the other end 5B of the external lead-out terminal 5 that has been insert-molded is exposed on the bottom surface of the insulating case 3 and is insufficiently adhered to the insulating case 3; There is a possibility that resonance occurs with the arm and bonding becomes insufficient.

【０００５】[0005]

【発明の目的】本発明は、上記のような課題を解決する
ためのなされたもので、ボンディングワイヤが確実に外
部導出端子の下端先端部にボンディングされるようにし
た複合半導体装置を提供することを目的とするものであ
る。SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a composite semiconductor device in which a bonding wire is securely bonded to a lower end of an external lead-out terminal. It is intended for.

【０００６】[0006]

【課題を解決するための手段】本発明の複合半導体装置
は、金属放熱板の上面に導体パターンを形成した絶縁基
板を介して半導体チップ、外部導出端子等の電子部品が
搭載され、前記放熱板の外周に、その壁面内に外部導出
端子がインサートモールドされた両端開口の絶縁ケース
が被せられ、上記電子部品と上記外部導出端子とを電気
的に接続するボンディングワイヤを備える複合半導体装
置において、前記ボンディングワイヤが接続される外部
導出端子の下端先端部をＬ字状に折曲げ、該先端部が前
記絶縁ケース内に埋没するようにインサートモールドし
たことを特徴とするものである。According to the composite semiconductor device of the present invention, electronic components such as a semiconductor chip and an external lead-out terminal are mounted via an insulating substrate having a conductor pattern formed on an upper surface of a metal heat sink. In the composite semiconductor device, the outer periphery of the composite semiconductor device is provided with an insulating case having an open end at both ends in which an external lead terminal is insert-molded in a wall surface thereof, and a bonding wire for electrically connecting the electronic component and the external lead terminal. The lower end of the external lead-out terminal to which the bonding wire is connected is bent into an L-shape, and the outer end is insert-molded so as to be buried in the insulating case.

【００１０】また、本発明の複合半導体装置は、前記外
部導出端子の下端先端部に抜け止め加工を施したことを
特徴とするものである。The composite semiconductor device according to the present invention is characterized in that a tip end of a lower end of the external lead-out terminal is subjected to a retaining process.

【００１１】[0011]

【実施例】以下、本発明の複合半導体装置を図を参照し
て説明する。図１は、本発明の複合半導体装置の一部を
示す平面図である。また、図２は図１のＡ−Ａ線に沿う
断面図である。これらの図において、従来の複合半導体
装置と同一部分には同一符号を付してその説明は省略す
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A composite semiconductor device according to the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a part of the composite semiconductor device of the present invention. FIG. 2 is a sectional view taken along line AA of FIG. In these figures, the same parts as those of the conventional composite semiconductor device are denoted by the same reference numerals, and the description thereof will be omitted.

【００１２】本発明の特徴は、ボンディングワイヤ６が
接続される外部導出端子５の下端先端部５１をＬ字状に
折曲げ、該先端部５１が絶縁ケース３内に埋没するよう
にインサートモールドしたことである。なお、上記の下
端先端部５１の絶縁ケース３との固着を強固にするため
に、当該先端部５１に下方に向かって幅が広がるように
逆テーパを付したり、端面を鋸歯状にするなどの抜け止
め加工を施すようにしても良い。A feature of the present invention is that the lower end portion 51 of the external lead-out terminal 5 to which the bonding wire 6 is connected is bent into an L-shape and insert-molded so that the end portion 51 is buried in the insulating case 3. That is. In order to firmly fix the lower end portion 51 to the insulating case 3, the front end portion 51 may be reversely tapered so as to increase its width downward, or may have a serrated end face. May be applied.

【００１３】また、図３に示すように、外部導出端子５
の下端先端部５１をさらに直角に折曲げた水平部５２を
形成し、絶縁ケース３の端部から外部に突き出すように
しても良い。上記の場合には外部導出端子５をリードフ
レーム状に形成し、最終工程で不要部分を切除するよう
にする。Further, as shown in FIG.
Alternatively, a horizontal portion 52 may be formed by further bending the lower end portion 51 at a right angle so as to protrude from the end of the insulating case 3 to the outside. In the above case, the external lead-out terminal 5 is formed in a lead frame shape, and unnecessary portions are cut off in the final step.

【００１４】[0014]

【発明の効果】本発明によれば、上記のようにボンディ
ングワイヤが接続される外部導出端子の下端先端部をＬ
字状に折曲げ、該先端部が絶縁ケース内に埋没するよう
にインサートモールドしたので、下端先端部の絶縁ケー
スに対する付着力が増大する。このため、ボンディング
する際にボンディング機械によって該下端先端部に振動
を与えても下端先端部が剥がれて共振するようなことが
なく、確実にボンディングすることができ、不良品を減
少させることができる。According to the present invention, the lower end portion of the external lead-out terminal to which the bonding wire is connected as described above is set to L
Since it is bent in a letter shape and insert-molded so that the tip is buried in the insulating case, the adhesive force of the tip of the lower end to the insulating case increases. Therefore, even when vibration is applied to the lower end portion by a bonding machine during bonding, the lower end portion does not peel off and resonate, bonding can be performed reliably, and defective products can be reduced. .

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の複合半導体装置に用いる絶縁ケースの
平面図である。FIG. 1 is a plan view of an insulating case used in a composite semiconductor device of the present invention.

【図２】図１におけるＡ−Ａ線に沿う断面図である。FIG. 2 is a sectional view taken along the line AA in FIG.

【図３】本発明の他の実施例を示す断面図である。FIG. 3 is a sectional view showing another embodiment of the present invention.

【図４】従来の複合半導体装置に用いる図２と同様の断
面図である。FIG. 4 is a cross-sectional view similar to FIG. 2 used for a conventional composite semiconductor device.

【符号の説明】[Explanation of symbols]

１ 金属放熱板 ２ 絶縁基板 ３ 絶縁ケース ４ 半導体チップ ５ 外部導出端子 ６ ボンディングワイヤ ５１ 外部導出端子の下端先端部 DESCRIPTION OF SYMBOLS 1 Metal radiator plate 2 Insulating substrate 3 Insulating case 4 Semiconductor chip 5 External lead terminal 6 Bonding wire 51 Lower end tip of external lead terminal

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】金属放熱板の上面に導体パターンを形成し
た絶縁基板を介して半導体チップ、外部導出端子等の電
子部品が搭載され、 前記放熱板の外周に、その壁面内に外部導出端子がイン
サートモールドされた両端開口の絶縁ケースが被せら
れ、かつ、ボンディングワイヤをボンディングするため
の領域として一定の範囲に亘って前記絶縁ケースの底部
表面に露出している前記外部導出端子の下端を有し、 上記電子部品と上記外部導出端子の露出した下端とを電
気的に接続するボンディングワイヤを備える複合半導体
装置において、 前記ボンディングワイヤが接続される外部導出端子の下
端先端部をＬ字状に折曲げ、該先端部が前記絶縁ケース
内に埋没するようにインサートモールドしたことを特徴
とする複合半導体装置。An electronic component such as a semiconductor chip and an external lead-out terminal is mounted on an upper surface of a metal heat sink through an insulating substrate having a conductor pattern formed thereon. Insulation case with insert-molded openings at both ends is covered and for bonding wire bonding
The bottom of the insulating case over a certain range as a region of
In a composite semiconductor device having a lower end of the external lead-out terminal exposed on the surface and including a bonding wire for electrically connecting the electronic component and the exposed lower end of the external lead-out terminal, the bonding wire is connected to the electronic component. Wherein the lower end of the external lead-out terminal is bent into an L-shape, and the lower end is insert-molded so as to be buried in the insulating case. 【請求項２】前記外部導出端子の下端先端部に抜け止加
工を施したことを特徴とする請求項１の記載の複合半導
体装置。2. The composite semiconductor device according to claim 1, wherein a tip end of a lower end of said external lead-out terminal is subjected to a retaining process.
JP14834998A 1998-05-13 1998-05-13 Composite semiconductor device Expired - Lifetime JP3347059B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14834998A JP3347059B2 (en) 1998-05-13 1998-05-13 Composite semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14834998A JP3347059B2 (en) 1998-05-13 1998-05-13 Composite semiconductor device

Publications (2)

Publication Number Publication Date
JPH11330344A JPH11330344A (en) 1999-11-30
JP3347059B2 true JP3347059B2 (en) 2002-11-20

Family

ID=15450784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14834998A Expired - Lifetime JP3347059B2 (en) 1998-05-13 1998-05-13 Composite semiconductor device

Country Status (1)

Country Link
JP (1) JP3347059B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6451117B2 (en) 2014-04-01 2019-01-16 富士電機株式会社 Semiconductor device manufacturing method and semiconductor device
DE112016007473T5 (en) * 2016-11-25 2019-08-14 Mitsubishi Electric Corporation Semiconductor device

Also Published As

Publication number Publication date
JPH11330344A (en) 1999-11-30

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