JP3344628B2 - Self-running frequency stabilization circuit for PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a free-running frequency stabilizing circuit for a PLL circuit, and more particularly to a free-running frequency stabilizing circuit for a PLL circuit for extracting a synchronous clock from a received signal when receiving a digital signal on a digital transmission line. Related to a chemical circuit.

[0002]

2. Description of the Related Art There are various types of conventional free-running frequency stabilization circuits of a PLL circuit in which a device for synchronizing an input signal and an output signal in the PLL circuit is devised.

A first example is a free-running frequency stabilizing circuit of a PLL circuit which copes with a case where the bandwidth of a PLL is narrow or a time constant of a loop filter (low-pass filter) is large as shown in FIG. And an M frequency divider (÷ M) 11 that divides the input reference input signal, that is, the transmission path extraction clock signal by M, to generate an M frequency-divided clock signal, and the M frequency-divided clock signal and the VCO (Voltage Controlled Oscillator) A phase detector (PD; Phase De) that compares a phase with an N-divided clock signal obtained by dividing an output pulse signal of N by N and outputs a predetermined voltage.
Tecter) 13 and a charge pump (C) that performs a predetermined charge based on the output level of the phase detector 13.
HP) 14, a changeover switch 15 for switching between the output side of the charge pump 14 and the output side of the phase detector 13,
A loop filter (LF; low-frequency filtering circuit) 16 for filtering low-frequency components of the signal from the phase detector 13, and a VCO (Voltage Control) for controlling the oscillation frequency based on the output voltage level of the loop filter 16.
led Oscillator (voltage controlled oscillator) 12,
The output pulse signal generated by this VCO is divided by N to obtain N
An N frequency divider (÷ N) 17 generates a frequency-divided clock signal Vopd and feeds it back to the phase comparator 13.

In such a configuration, at the time of circuit initialization or output frequency switching, the changeover switch 15 is connected to the charge pump 14 in order to reduce the time required for synchronization.
By switching the current to the side and forcing a current into the loop filter 16 to forcibly approach a desired control voltage, the time required for synchronization can be reduced, and the free-running frequency can be stabilized.

A second example is a free-running frequency stabilization circuit of a PLL circuit which uses a loop filter having a small time constant to shorten the time required for synchronization, as shown in FIG. An M frequency divider 11 that divides the reference input signal, that is, the transmission path extraction clock signal, by M to generate an M frequency divided clock signal Vipd, and an M frequency divided clock signal Vipd
And N generated by dividing the output pulse signal of the VCO 12 by N
A phase detector 13 for comparing the phase with the frequency-divided clock signal Vopd and outputting a predetermined voltage; and a first and a second series-connected serial detector for passing only the low-frequency component of the signal from the phase detector 13 Loop filter (low-pass filter) 1
8, 19, a switch 20 connected in parallel to the first loop filter 18, a VCO (voltage controlled oscillator) 12 for controlling an oscillation frequency by an output voltage level of the second loop filter 19, and an output pulse signal Is divided by N to generate a N-divided clock signal Vopd, and the phase detector 13
And an N frequency divider 16 for inputting a feedback signal to the input.

In such a configuration, when the bandwidth of the PLL circuit is narrow or the time constant of the loop filter is large, when the circuit is initialized or the output frequency is switched, the switch 20 is turned on to reduce the time constant. By synchronizing with the second loop filter 19, the time required for synchronization is reduced, and the free-running frequency is stabilized.

[0007]

However, in the above-described PLL circuit of the prior art, the output of the phase detector is large, the gain of the loop filter is large, the control voltage range of the VCO is narrow, and the like. VC
If the voltage of the control signal input to O deviates, for example, beyond the range of the frequency variable control voltage of the VCO, there is a problem that the time required for synchronization of the PLL circuit cannot be reduced.

When the VCO deviates from the frequency variable control voltage range, the VCO operates until the VCO control voltage reaches a phase difference within the frequency variable control voltage range. Or it operates at the lower limit. for that reason,
It takes a very long time until the variable frequency range of the VCO becomes narrow and the comparison frequency of the phase detector remains low, the frequency deviation (phase change rate) becomes very small, and the pull-in operation by the PLL becomes possible. There is a problem that it is necessary.

Therefore, there is a problem that must be solved to shorten the time required for synchronizing the PLL circuit even when the frequency exceeds the range of the frequency variable control voltage of the VCO.

[0010]

In order to solve the above-mentioned problems, a self-running frequency stabilizing circuit for a PLL circuit according to the present invention comprises an M divider for generating an M-divided clock signal based on a reference input signal. And the N-divided clock signal composed of the M-divided clock signal and the output pulse signal generated by the VCO, and the phase difference between the inputted M-divided clock signal and the inputted N-divided clock signal is determined. A phase detector that outputs a voltage signal; a loop filter that filters low frequency components of a signal output from the phase detector; and an output pulse that controls an oscillation frequency by a voltage level output from the loop filter. And a VCO for outputting a signal. When the value of the phase difference output from the phase detector becomes equal to or greater than a predetermined value, the phase detector detects the M-divided clock signal and / or N
A divider control means for temporarily stopping the output of the divided clock signal is provided.

Further, the frequency divider control means, when the value of the phase difference output from the phase detector becomes a predetermined value or more,
Suspending the output of the M-divided clock signal; detecting when the value of the phase difference output from the phase detector becomes equal to or greater than a predetermined value, determines the phase setting value at which the free-running frequency of the VCO deviates. Setting the phase in advance and comparing the phase set value with the value of the phase difference output from the phase detector; the frequency divider control means determines that the value of the phase difference output from the phase detector is a predetermined value At this time, the phase progress status of the two M-divided clock signals and the N-divided clock signals input to the phase detector is detected, and the M-divided clock signal or the N-divided clock signal is detected. Pausing; the phase detector is a frequency divider built-in type phase detector incorporating the M frequency divider and the N frequency divider.

As described above, when the value of the phase difference output from the phase detector becomes equal to or more than a predetermined value that deviates from the free-running frequency range of the VCO, the signal on one side of the two signals input to the phase detector To temporarily generate a phase difference within the free-running frequency range of the VCO by forcibly shifting any signal input to the phase detector to one side signal by temporarily stopping the occurrence of And the time for synchronizing the PLL circuits can be shortened.

[0013]

Next, an embodiment of a free-running frequency stabilizing circuit for a PLL circuit according to the present invention will be described with reference to the drawings. The same components as those in the prior art will be described with the same reference numerals.

A self-running frequency stabilizing circuit of a PLL circuit according to a first embodiment of the present invention has a VC circuit as shown in FIG.
Even if the range of the O12 frequency variable control voltage is exceeded, the circuit configuration can shorten the time required for synchronization.
An M frequency divider (ΔM) 11 that outputs an input reference input signal, that is, an M frequency-divided clock signal Vipd generated by dividing the transmission path extracted clock signal by M, and an M frequency-divided clock signal Vipd. A phase detector that receives both an N-divided clock signal Vopd obtained by dividing the output pulse signal of a VCO (voltage controlled oscillator) 12 by N, compares the phases thereof, and outputs a predetermined voltage corresponding to the phase difference ( PD; Phase De
Tecter) 13, a loop filter (LF; low-frequency filtering circuit) 16 for filtering low-frequency components of the signal from the phase detector 13, and a VCO (Oscillator) that controls the oscillation frequency based on the output voltage level of the loop filter 16. Volt
An Age Controlled Oscillator (VCO) 12 and an N frequency divider (÷) that divides the output pulse signal generated by the VCO by N to generate a N-divided clock signal Vopd and feeds it back to the phase detector 13. N) 17, an M-divided clock signal Vipd output from the M-divider 11 based on the phase difference signal LD output from the phase detector 13 and provided between the M-divider 11 and the phase detector 13 Frequency divider control means for temporarily suspending the output of
That is, the frequency divider control circuit (Divider Control)
1) 30.

The loop filter 16 is a low-pass filter that removes unnecessary harmonic components and noise contained in the signal output from the phase detector 13 and
It has a function to determine the response and synchronization characteristics of the PLL based on the amplitude / phase characteristics.

The VCO 12 is an oscillator whose oscillation frequency is determined by the output voltage of the loop filter 16, and its output is applied to the phase detector 13 to form a PLL feedback loop.

The frequency divider control circuit 30 has a configuration in which a phase set value which is a value deviating from the free-running frequency of the VCO 12 can be set in advance. This phase setting value is compared with the value of the phase difference from the phase detector 13, that is, the phase difference signal LD. If the phase difference signal LD is larger than the phase setting value, the frequency divider control signal DC becomes high. Output a signal.
When the frequency divider control signal DC becomes high level, the M frequency-divided clock signal Vipd output from the M frequency divider 11 is temporarily stopped during the high level time.

The operation of the free-running frequency stabilizing circuit of the PLL circuit having such a configuration will be described with reference to a timing chart shown in FIG.

In the cases (1), (2), and (3), (4), in which the M-divided clock signal Vipd is temporarily stopped, the phase setting value 3 provided in the frequency divider control circuit 30 is provided.
When the phase difference signal LD output from the phase detector 13, that is, the phase difference signal LD between the M-divided clock signal Vipd and the N-divided clock signal Vopd is greater than 1, When it is determined that the frequency deviates from the running frequency range, the frequency divider control signal DC is generated at a high level for a predetermined period (state (1)). This frequency divider control signal D
When C goes high, the generation of the M-divided clock signal Vipd output from the M divider 11 is temporarily stopped. Therefore, the generation of the M frequency-divided clock signal Vipd is delayed only during the period in which the frequency divider control signal DC is at the high level, and the phase on the reference signal side is forcibly shifted (state (2)).

Next, the delayed M frequency-divided clock signal Vipd
Occurs, the delayed M-divided clock signal Vipd
And the N-divided clock signal Vopd are input to the phase detector 13 to generate the phase difference signal LD. If the phase difference signal LD is larger than the phase set value 31, V
It is determined that the frequency deviates from the free-running frequency range allowed by the CO 12, and the frequency divider control signal DC generates a high-level signal for a predetermined period (state (3)). When the frequency divider control signal DC goes high, the generation of the M-divided clock signal Vipd is temporarily stopped, so that the generation of the M-divided clock signal Vipd is delayed, and the phase on the reference signal side is further forced. (The state of (4)).

The delayed M frequency-divided clock signal V
When the ipd occurs, the phase detector 13 detects the delayed M
Divided clock signal Vipd and N-divided clock signal Vop
A phase difference signal LD from the signal d is generated. This phase difference signal LD
Is VCO when the value is smaller than the phase set value 31.
12 can be determined to be within the range of the free-running frequency allowed, it can be determined that the pull-in operation in the PLL circuit operates normally (state (5)). Therefore, the frequency divider control signal DC does not go to the high level, and the operation of the M frequency-divided clock signal Vipd occurs normally without a pause. Then, the PLL circuit performs a pull-in operation and controls the N-divided clock signal Vopd (output pulse signal side) so as to synchronously follow the M-divided clock signal Vipd (reference input signal side) (state (6)). . In this way, the phase on the reference input signal side is forcibly shifted, and PL
The input reference signal and the output pulse signal can be brought into a synchronized state (state (7)) by shortening the time for driving the L circuit to a state where the L circuit can follow the synchronization.

Here, the phase amount to be shifted by temporarily stopping the M frequency-divided clock signal Vipd (reference input signal side) of the M frequency divider 11 is compared with a signal (N frequency division) of the phase detector 13 to be compared. If the phase amount is set to be larger than the phase amount that changes in the time of one cycle of the clock signal Vopd), the PL
The time required for the L circuit to follow the synchronization (delivery time) can be reduced. In the extreme case, the divider control signal D
If the phase difference signal LD is used instead of C,
In a time period of about several cycles of the signal on the side to be compared, a state in which the PLL circuit can follow the synchronization can be obtained. However, when starting these phase shift controls, the phase comparison must be performed one or more times.
It is necessary to provide a start function for stopping frequency divider control for an appropriate time.

Next, a free-running frequency stabilizing circuit of a PLL circuit according to a second embodiment will be described with reference to FIG.

The self-running frequency stabilizing circuit of the PLL circuit according to the second embodiment includes a reference-side signal (M-divided clock signal Vipd) and a comparison-side signal (N-divided clock signal Vop).
d), the phase shift control is performed, and the M reference clock signal Vi is generated by dividing the input reference input signal, that is, the transmission path extraction clock signal by M.
An M frequency divider 11 that outputs pd, an M frequency-divided clock signal Vipd, and an N frequency-divided clock signal Vod obtained by dividing the output pulse signal of a VCO (voltage controlled oscillator) 12 by N are both input. A phase detector 13 for comparing phases and outputting a predetermined voltage; a loop filter (low frequency filtering circuit) 16 for filtering low frequency components of a signal from the phase detector 13; A VCO 12 for controlling an oscillation frequency by a voltage level, and an M frequency divider 1
1 and the phase detector 13, the M-divided clock signal Vipd output from the M-divider 11 based on the phase difference signal LD output from the phase detector 13 and the N-divider 17.
And a frequency-divider control circuit 30a for controlling the output of the N-frequency-divided clock signal Vopd.

The frequency divider control circuit 30a has a phase set value within the free-running frequency of the PLL circuit, compares this phase set value with the phase difference signal LD from the phase detector 13,
If the phase difference signal LD is larger than the phase set value, the frequency divider control signal DC outputs a high level signal. The M-divided clock signal Vipd output from the M-divider 11 is stopped only during the period of the high-level signal of the divider control signal DC (see the flowchart of FIG. 2).

On the other hand, the frequency divider control circuit 30a has a function of receiving a phase delay signal (θR) for detecting a phase progress state from the phase detector 13. Input reference side (M-divided clock signal Vi
When the phase of pd) is advanced, it becomes high level,
When the phase of the comparison side (N-divided clock signal Vopd) is advanced, it becomes a low level signal.

In a circuit having such a function, V
When the frequency deviates from the range of the frequency permitted by the CO 12, that is, when the phase difference signal DC becomes larger than a preset phase set value, the phase progress of the two signals input to the phase detector 13 is performed. Detect state. That is, if the phase on the reference side is ahead of the phase delay signal θR, the frequency divider control signal DCi is set to the high level, and the output of the M frequency-divided clock signal Vipd, which is the output of the M frequency divider 11, is temporarily stopped. To control. If the phase on the comparison side is advanced, the frequency divider control signal DCo is set to the high level, and the N frequency divider 17
Is controlled so as to temporarily stop the output of the N-divided clock signal Vopd, which is the output of.

In this manner, the reference side (M-divided clock signal Vipd) and the comparison side (N
It is possible to forcibly shift either of the phases of the frequency-divided clock signal Vopd) to drive the phase into the synchronous tracking state by the PLL circuit. The operation of the PLL circuit to drive to the synchronous follow-up state is the same as that described in the first embodiment with reference to the timing chart of FIG.

Next, a free-running frequency stabilizing circuit of a PLL circuit according to a third embodiment will be described with reference to FIG.

The self-running frequency stabilizing circuit of the PLL circuit in the third embodiment is an integrated circuit (IC) having at least a M frequency divider, an N frequency divider, and a phase comparator.
rcuit (integrated circuit).
A reference input signal to be input to C is input through a gate circuit 31 formed of NOR or the like, and the VCO
12 between the N frequency divider 17 which feeds back the output pulse signal of No. 12 and generates the N frequency-divided clock signal Vopd.
And the like. A frequency divider control circuit 30a is provided between the phase detector 13 and the gate circuit 31, and controls the reference M frequency divider 11 and the comparison N frequency divider 17 via the gate circuits 31 and 32. Thus, a forced phase shift is performed. Here, the frequency divider control circuit 30
a, the phase progress state detected by the phase detector 13 is detected in the same manner as in the second embodiment, and the reference side (M-divided clock signal Vi) is detected.
pd) or the signal on the comparison side (N-divided clock signal Vopd) is temporarily stopped.

When the gate circuits 31 and 32 are used as described above, it is not possible to directly control the M frequency divider 11 and the N frequency divider 17 in the IC including the M frequency divider 11 and the N frequency divider 17. Even in the case of the structure, by turning off the gate circuits 31 and 32, the M frequency divider 11 and N
The input signal to the frequency divider 17 is stopped, and the M frequency-divided clock signal Vipd and the N frequency-divided clock signal Vop output from the frequency divider 17 are stopped.
d can be paused. In the embodiment, the gate circuits 31 and 32 have a function of simply controlling the disconnection state and the connection state. However, the present invention is not limited to this. Is also good.

In such a configuration, when the frequency deviates from the range of the frequency permitted by the VCO 12, that is, when the phase difference signal DC becomes larger than a preset phase set value, the input to the phase detector 13 is made. The phase progress state of the two signals being detected is detected. If the phase of the reference side (M frequency-divided clock signal Vipd) is ahead of the phase delay signal θR, the frequency divider control signal DCi is set to the high level, the gate circuit 31 is turned off, and the M frequency divider is turned off. The input of the reference input signal to be input to 11 is blocked. If the phase of the comparison side (N-divided clock signal Vopd) is advanced, the divider control signal DCo is set to the high level, the gate circuit 32 is turned off, and the output pulse signal input to the N-divider 17 is output. Block.

In this way, the signal input to the M frequency divider 11 or the N frequency divider 17 is turned off, and the phase detector 13
Of the reference side (divided-by-M clock signal Vipd) and the comparison side (divided-by-N clock signal Vopd) are forcibly shifted, so that the phase can be driven to the synchronization following state by the PLL circuit. is there. The operation of the PLL circuit to drive to the synchronous follow-up state is the same as that described in the first embodiment with reference to the timing chart of FIG.

As described above, as disclosed in the above-described first to third embodiments, when the frequency deviates from the allowable frequency of the VCO 12, the two signals input to the phase detector 13 By suspending the generation of the reference side signal or the comparison side signal and forcibly shifting the phase, the time for synchronizing at the lower limit or the upper limit of the free running frequency can be reduced to stabilize the free running frequency. It becomes possible.

[0035]

As described above, the PL according to the present invention is
The free-running frequency stabilization circuit of the L circuit forcibly shifts the reference side or comparison side signal input to the phase detector when the phase detector deviates from the allowable frequency of the VCO, and forcibly performs the phase shift. By doing so,
There is an effect that the time required for synchronization in the PLL circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram schematically showing a free-running frequency stabilization circuit of a PLL circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the circuit in FIG.

FIG. 3 is a circuit diagram schematically showing a free-running frequency stabilization circuit of a PLL circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram schematically showing a free-running frequency stabilization circuit of a PLL circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram schematically showing a free-running frequency stabilization circuit of a PLL circuit according to the related art.

FIG. 6 is a circuit diagram schematically illustrating a free-running frequency stabilization circuit of a PLL circuit according to another example of the related art.

[Explanation of symbols]

11; M divider, 12; VCO, 13; phase detector, 1
6; loop filter, 30; frequency divider control circuit, 30a;
Divider control circuit, 31; gate circuit, 32; gate circuit

Claims (1)

(57) [Claims] 1. An M frequency divider for generating an M frequency-divided clock signal based on a reference input signal, and an N frequency-divided clock signal based on an output pulse signal.
Type a N divider that, the M-divided clock signal and with said N divided clock signal, a phase detector for outputting a signal having a voltage corresponding to the phase difference is output from the phase detector a loop filter for filtering the low frequency components of the signal, VC for outputting the output pulse signal by controlling the oscillation frequency by a voltage level output from the loop filter
In the free-running frequency stabilization circuit of the PLL circuit consisting of O
Te, the value of the phase difference output from the phase detector is greater than a predetermined value
The two phase detectors input to the phase detector
Phases of the M-divided clock signal and the N-divided clock signal
Detecting the progress state, the M divided clock signal or the previous
A free-running frequency stabilizing circuit for a PLL circuit, comprising a frequency divider control means for temporarily stopping the N- divided clock signal .