JP3340174B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chamber technology, and more particularly to a technology effective when applied to a wafer processing step in a semiconductor device manufacturing process.

[0002]

2. Description of the Related Art A multi-chamber device has been proposed and manufactured by semiconductor device manufacturers in Japan and overseas since the latter half of the 1980's as one of future developments of semiconductor manufacturing devices for the following reasons.

(1) The multi-chamber system uses a vacuum,
Alternatively, since the wafer can be integratedly processed in an inert gas atmosphere, contamination from the outside can be prevented when forming each layer, quality can be improved, and further stabilization can be achieved. .

(2) Since it is an integrated process in a multi-chamber system, the time required for wafer transfer can be reduced, and the overall process can be shortened.

(3) In the multi-chamber, in order to cope with a new process, only one process chamber constituting the multi-chamber is newly manufactured, and the wafer transfer robot section, the load lock chamber, etc. Since the products can be used as they are, it is possible to reduce the investment amount due to the technical progress of semiconductor manufacturing.

Next, the prior art of the multi-chamber apparatus will be summarized.

(1) The multi-chamber apparatus manufactured so far has a plurality of different processing apparatuses connected to a wafer transfer section, and is intended for a part of the processing.

(2) The basic configuration of a conventional multi-chamber is a wafer transfer apparatus serving as a main body, and a process chamber and a load lock chamber connected to the periphery thereof. The docking chamber required for connecting a plurality of multi-chambers is little utilized.

(3) By using a conventional multi-chamber apparatus, for example, if a thin film is to be formed, a pretreatment
It is possible to execute a continuous process of forming a thin film.

[0010]

The above prior art has the following problems.

(1) In the conventional multi-chamber apparatus, since the number of process chambers that can be connected to the main wafer transfer chamber is several, when performing a series of process processing, one process chamber of the same type is connected. It was the limit to do. In other words, two process chambers of the same type
There was no room to connect the units. Since there is only one process chamber with the same function,
The capacity of the process chamber with the lowest throughput capacity determines the processing capacity of the multi-chamber device,
There is a problem that a process chamber having a sufficient processing capacity is not effectively used.

(2) In a multi-chamber apparatus, when there is only one process chamber, when one process chamber is stopped due to failure or maintenance, the whole series of processing is interrupted. And the operation rate of the multi-chamber apparatus is reduced.

(3) Even when a multi-chamber system is realized by connecting multi-chamber devices,
If there is only one process chamber having the same function, the problems (1) and (2) still occur.

An object of the present invention is to provide a method of manufacturing a semiconductor device using a multi-chamber technique, which can improve the utilization efficiency of a plurality of process chambers.

Another object of the present invention is to use a multi-chamber technique capable of increasing the number of objects to be processed per unit time in an integrated processing step performed by sequentially combining a plurality of types of processing . Semiconductor device manufacturing method
Is to provide a law .

Still another object of the present invention is to use a multi-chamber technology capable of improving the operation rate by avoiding the stop of the entire apparatus due to maintenance management work or failure of an individual process chamber . An object of the present invention is to provide a method for manufacturing a semiconductor device .

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0018]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones will be briefly described as follows.

That is, in the method of manufacturing a semiconductor device according to the present invention, a plurality of process chambers each independently performing a desired process on a semiconductor wafer, and the plurality of process chambers are isolated from an external environment. connected to each other in a closed space
Te, a transfer chamber for transferring operation of the semiconductor wafer between a plurality of said process chamber, said semiconductor
A method of manufacturing a semiconductor device using a multi-chamber apparatus including a load lock chamber for taking in and out of a wafer , wherein a plurality of the multi-chamber apparatuses are connected to the processor.
Chamber or the load lock chamber
To the semiconductor wafer via a docking chamber.
C through the docking chamber,
A plurality of types of processing are performed by transporting the inside of the chamber .

[0020]

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

The above-described multi-chamber apparatus of the present invention is used.
According to the method for manufacturing a semiconductor device , for example, in a plurality of process chambers performing different processes, when there is a difference in required time in each process for a specific workpiece,
By providing multiple process chambers for performing a process with a longer required time and allocating an object to be processed to a plurality of multiple process chambers and operating them in parallel, a process chamber for performing other processes before and after the process is performed. Waiting time is eliminated, and the number of objects to be processed per unit time can be increased in an integrated processing step performed by sequentially combining a plurality of types of processing, and effective use of each process chamber is realized. can do.

Further, for example, when there is a difference in the time required for maintenance and the failure rate among a plurality of process chambers performing different processes, the time required for maintenance is reduced. By providing multiple process chambers that perform long processing or process chambers with higher failure rates, it is possible to perform maintenance management and target processing simultaneously, or to continue operation by switching to an alternative process chamber in the event of a failure. . That is, it is possible to avoid the stop of the integrated processing step for the object to be processed, and it is possible to reliably improve the operation rates of the apparatus and the integrated processing step.

Further, by providing a plurality of process chambers for performing different processes in a multiplex manner, the number of processed objects per unit time can be increased by the multiplicity during the entire normal operation. At the same time, when a specific process chamber fails, switching to an alternative process chamber and performing a degenerate operation to reduce the supply of workpieces can avoid the stoppage of the entire integrated processing process and improve fault tolerance. Can be.

[0030]

Embodiment 1 Hereinafter, a multi-chamber apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a conceptual diagram showing an example of the configuration of the multi-chamber apparatus of the present embodiment.

In the multi-chamber apparatus of this embodiment, as an example, a case will be described where an integrated processing step of continuously performing different processes A, B, and C on a semiconductor wafer (hereinafter simply referred to as a wafer) is performed. I do.

In the multi-chamber apparatus of this embodiment, the process chamber 1, the process chamber 2, and the process chamber 3 are provided in a multiplexed manner so that the same process A can be executed equivalently, and the process chamber 4 that can execute the process B is provided. , A process chamber 5 that can execute the process C, a load lock chamber 6 that performs loading and unloading of a wafer, and a wafer transfer chamber 7 around which the respective chambers are connected. Although not shown, a gate valve mechanism is disposed at a connection portion between the wafer transfer chamber 7 and each chamber, and various conditions such as a temperature, a gas atmosphere, and a degree of vacuum in each chamber are independently controlled to a desired state. At the same time, a wafer (not shown) is taken in and out through the gate valve mechanism.

Inside the wafer transfer chamber 7, there is provided a transfer arm 7a which can rotate and expand and contract freely.
A transfer table 7b, which is provided at the tip end of a and on which a wafer (not shown) is placed, is provided, and the operation of moving the wafer between the chambers is performed.

Further, as a control system, the multi-chamber apparatus of this embodiment is under the control of an overall control CPU (central processing unit) 8, and includes process chambers 1 to 3, and process chambers 4, 5, and The load lock chamber 6 and the wafer transfer chamber 7 are respectively
The process chamber CPUs 1c to 3c, the process chamber CPUs 4c and 5c, the load lock chamber CPU 6c, and the wafer transfer chamber CPU 7
c.

The process chamber CPUs 1c to 5c and the load lock chamber CPU 6c are respectively
A process A specific digital output 1a-3a for identifying a process in each chamber, a process B specific digital output 4a, a process C specific digital output 5a, and a load lock chamber specific digital output 6a;
It has process chamber use status digital outputs 1b to 3b, process chamber use status digital output 4b, process chamber use status digital output 5b, and load lock chamber use status digital output 6b indicating the operation status of each chamber. To the CPU 8 for use.

The overall control CPU 8 includes a wafer progress management file 9 and a throughput optimization algorithm 10.
And the individual process chambers 1 to
3, and a multitasking function capable of simultaneously managing and operating each of the process chambers 4 and 5, the load lock chamber 6, and the wafer transfer chamber 7 in parallel.

FIG. 2 is a flowchart showing an example of a procedure of an integrated processing process performed in the multi-chamber apparatus of the present embodiment. This integrated processing includes a process A (processing time; 3 hours unit), a process B (processing time; 1 hour unit), and a process C (processing time; 1 hour unit). Here, it is assumed that a plurality of wafers in the load lock undergo wafer processing in the integrated processing procedure shown in FIG.

First, a description will be given of a method of executing the integrated processing procedure of FIG. 2 in the multi-chamber apparatus of the present embodiment of FIG. The wafer progress management file 9 corresponds to the integrated processing procedure of FIG. 2 corresponding to the process chamber. The process chamber is in an operable state, and a wafer as a processing object (not shown) is loaded in the load lock chamber 6.
It is assumed that there are a plurality of sheets.

Along with the execution start command shown in FIG. 2, the overall control CPU 8 refers to the wafer progress management file 9 and the throughput optimization algorithm 10 and causes the wafer transfer chamber CPU 7c to transfer the wafer from the load lock chamber 6 to the process chamber 1. Command.

When the wafer of the number N1 is transferred to the process chamber 1, the process chamber CPU 1c starts the process A. Then, when the time has passed for 3 hours,
The process chamber CPU 1c transmits end information to the overall control CPU 8.

Thereafter, the overall control CPU 8 executes the wafer progress management file 9 and the throughput optimization algorithm 1
0, a wafer transfer command is transmitted to the CPU 7c for the wafer transfer chamber. CPU 7c for wafer transfer chamber
Transports the wafer of the number N1 from the process chamber 1 to the process chamber 4, and after the completion of the transport, the CPU for overall control
8 to the end information.

Thereafter, the overall control CPU 8 transmits a process processing command to the process chamber CPU 4c.
The process chamber CPU 4c executes the process B for one hour, and thereafter transmits end information to the overall control CPU 8.

Next, the overall control CPU 8 includes the wafer progress management file 9 and the throughput optimization algorithm 1
0, a wafer transfer command is transmitted to the wafer transfer chamber CPU 7c. After that, the wafer transfer chamber CPU 7c transfers the wafer of the number N1 from the process chamber 4 to the process chamber 5, and transmits end information to the overall control CPU 8.

Thereafter, the overall control CPU 8 issues a process processing instruction to the process chamber CPU 5c. As a result, the process chamber CPU 5c
Is executed in units of one hour, and after completion, the end information is transmitted to the CPU 8 for overall control.

The overall control CPU 8 refers to the wafer progress management file 9 and the throughput optimization algorithm 10 and transmits a wafer transfer command to the wafer transfer chamber CPU 7c. The wafer transfer chamber CPU 7c transfers the number N from the process chamber 5 to the load lock chamber 6.
One wafer is conveyed, and an end command is transmitted to the overall control CPU 8.

The overall control CPU 8 refers to the wafer progress management file 9 and confirms that the integrated processing procedure of FIG. 2 has been completed for the wafer of the number N1.

FIG. 3 is a wafer processing diagram in the multi-chamber apparatus of this embodiment.

The above-mentioned series of operations show the processing status of the wafer processing of the number N1 in FIG. 3 up to the unit of 5 hours.

Since the overall control CPU 8 is capable of multitask processing, in the wafer processing of the number N1 in FIG. Reference is made to 9 and the throughput optimization algorithm 10 (e.g., having the function of examining the availability of process chambers and specifying which process chambers can be processed) to find the next feasible job. Then, it is found that the wafer of the number N2 needs to be processed in the process A, and the process chamber capable of executing the process A is the overall control CP.
U8 refers to the process A specific digital outputs 1a, 2a, 3a of the process chamber CPU, and it is understood that the corresponding ones are the process chamber 1, the process chamber 2, and the process chamber 3. Further, digital output 1b, 2 of process chamber usage status
b, 3b, 4b, 5b, and the load lock chamber usage digital output 6b, the process chamber 2, the process chamber 3, the process chamber 4,
It can be seen that the process chamber 5 is in an unused state.

When the overall control CPU 8 selects a subordinate usable CPU (process chamber), if there are a plurality of process chambers satisfying the conditions,
It is assumed that there is a rule that the number Nn is used from the younger one. It is understood that the process chamber 2 satisfies the above requirements. Therefore, the overall control CPU 8
Transmits a wafer transfer command to the wafer transfer chamber CPU 7c.

In this case, the overall control CPU 8 simulates the use status of the entire process chamber, and
The wafer transfer command is issued within a time unit. The wafer transfer chamber CPU 7c transfers the wafer of the number N2 from the load lock chamber 6 to the process chamber 2, and thereafter transmits end information to the overall control CPU 8. The overall control CPU 8 refers to the wafer progress management file 9 and
A process command is transmitted to the process chamber 2. Hereinafter, the integrated processing procedure of FIG. 2 is executed for the wafer of the number N2 similarly to the wafer of the number N1. This state is
FIG. 4 is a processing diagram for the wafer with the number N2 in FIG. 3.

The same processing is performed on wafers with numbers N3 and lower. FIG. 3 summarizes the above.

FIG. 4 shows the lapse of time and the occupation state of the process chamber in the multi-chamber apparatus of this embodiment. FIG. 6 summarizes the device occupation state up to the time lapse state of the 5-hour unit for each hour unit. 5
After the time unit, the occupation state of the process chamber is equivalent to that of the 5-hour unit (however, the situation is different near the end of processing a plurality of wafers). As can be seen from the figure, it can be seen that a plurality of process chambers are effectively used.

Next, the effect of the multi-chamber apparatus of this embodiment will be described in comparison with the wafer processing capacity of the conventional multi-chamber apparatus shown in FIG.

FIG. 7 shows a conventional multi-chamber apparatus. In the conventional multi-chamber apparatus, there is only one process chamber having each function. That is, the conventional multi-chamber apparatus includes a process chamber 11 capable of executing the process A, a process chamber 12 capable of executing the process B, a process chamber 13 capable of executing the process C, a load lock chamber 14 capable of loading and unloading the wafer, and a wafer and the like. It comprises a transfer chamber 15.

In terms of the system, this multi-chamber apparatus is under the control of the overall control CPU 16, and each chamber is controlled by the process chamber CPUs 11c to 11c.
CPU 13c for process chamber, CPU 14c for load lock chamber, CPU 15c for wafer transfer chamber
have.

The wafer transfer chamber 15 is provided with a transfer arm 15a and a distal end of the transfer arm 15a.
A transfer table 15b on which a wafer (not shown) is placed is provided, and the wafer is moved between the chambers.

Further, the process chamber CPU 11c
Each of the process chamber CPU 13c and the load lock chamber CPU 14c includes a process A specific digital output 11a, a process B specific digital output 12a,
It has a process C specific digital output 13a, a load lock chamber specific digital output 14a, a process chamber use digital output 11b to a process chamber use digital output 13b, and a load lock chamber use digital output 14b.

The overall control CPU 16 has a wafer progress management file 17.

FIG. 8 is a wafer processing diagram of a conventional multi-chamber apparatus. The process processing content is the integrated processing procedure shown in FIG. The number N1 in FIG.
During the process A, the wafer of the number N2 cannot be processed by the conventional multi-chamber apparatus, and the wafer of the number N1 is moved to the process chamber 12 where the process B is performed. The N2 wafer undergoes process A.

For example, at the lapse of the six-hour unit in FIG.
The process chamber 12 for executing the process B and the process chamber 13 for executing the process C are not used. In this case, it can be seen that the process chamber 11 that performs the process A, which requires three hours, controls the entire process.

FIG. 9 shows the lapse of time and the occupation state of the process chamber in the conventional multi-chamber apparatus. Comparing FIG. 9 with FIG. 4 of the multi-chamber apparatus of this embodiment, it can be seen that the process chamber of FIG. 9 is not effectively utilized.

Next, it is assumed that one process chamber for processing the process A cannot be used due to a failure. FIG.
In the multi-chamber apparatus of the present embodiment, it is assumed that the process chamber 1 is out of order. In this case, what can process the process A is the process chamber 2 and the process chamber 3
As one of them is used,
(1), and the fault tolerance is surely improved.

On the other hand, in the conventional multi-chamber apparatus shown in FIG. 7, when the process chamber 11 capable of processing the process A cannot be used due to a failure, there is no process chamber capable of processing the process A. Processing becomes impossible.

[0066]

Embodiment 2 FIG. 5 is a conceptual diagram showing an example of the configuration of a multi-chamber apparatus according to another embodiment of the present invention. In the case of the second embodiment, an example is shown in which a cluster tool system is constructed by combining a plurality of multi-chamber apparatuses.

That is, in the cluster tool system of the present embodiment, the process chamber 5 is removed from the multi-chamber apparatus shown in FIG. And another multi-chamber apparatus is connected.

Around the wafer transfer chamber 19, a process chamber 20, a process chamber 21 capable of executing the process B, a process chamber 22, a process chamber 23, and a process chamber 24 capable of executing the process C are connected. In this case, the number of process chambers capable of executing process A is three, the number of process chambers capable of executing process B is three, and the number of process chambers capable of executing process C is three. Since the processing can be performed more flexibly than in the case of the above-described first embodiment, for example, the processing steps are executed simultaneously in two lines, an improvement in throughput can be expected and a fault tolerance can be improved.

As described above, even when a plurality of multi-chamber apparatuses are gathered to form a cluster tool system, the overall throughput can be increased by applying the algorithm of the same method as described above.

Further, in the cluster tool system of the present embodiment shown in FIG. 5, even if any two process chambers are unavailable due to a failure, a process required for the integrated processing procedure shown in FIG. 2 can be performed. Since there is one or more chambers, integrated processing can be performed without stopping operation, and fault tolerance is reliably improved.

[0071]

Embodiment 3 FIG. 6 is a conceptual diagram showing an example of the configuration of a multi-chamber apparatus according to still another embodiment of the present invention.
The multi-chamber apparatus of the present embodiment is used for an integrated processing step of continuously performing the same three processes A, B, and C as in the first embodiment.

The multi-chamber apparatus of the third embodiment has a straight tunnel-like chamber 37 and a plurality of process chambers 31, 32, and 3 connected in parallel to side surfaces of the tunnel-like chamber 37.
3, and process chamber 34, process chamber 3
5.

Gate valve mechanisms 31g to 35g are interposed at the connection portions of the process chambers 31 to 35 to the linear tunnel-shaped chamber 37, and various kinds of temperature, atmosphere, vacuum degree, etc. in each chamber are provided. The conditions can be independently controlled to a desired state, and the gate valve mechanism 31g-
A wafer (not shown) is taken in and out through each of the 35 g.

The load lock chamber 36 and the load lock chamber 3 are provided at both ends of the tunnel-shaped chamber 37.
8 are arranged, and the load lock chamber 36,
Transmission and reception with the outside of the wafer (not shown) are performed via 38.

In the inside of the tunnel-shaped chamber 37, a transport path 41 arranged along the longitudinal direction,
There is provided a transfer arm 39 and a transfer table 40 that move on the table.

In this case, the three process chambers 31 to 31
In the process chamber 33, the process A is performed, the process chamber 34 performs the process B, and the process chamber 35 performs the process C. Thus, for the process A having the longest processing time, the use of a vacant one of the process chambers 31 to 33 can improve the throughput as in the case of the first embodiment. .

Further, since the plurality of process chambers 31 to 35 are connected in parallel to the side surface of the linear tunnel-shaped chamber 37, the space between the process chambers can be made relatively large, and maintenance and management can be performed. There is an advantage that work can be performed more easily.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and may be variously modified without departing from the gist thereof. Needless to say.

For example, a cluster tool system may be constructed by combining the configuration of the first embodiment and the configuration of the third embodiment.

[0080]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

[0081] Sunawa Chi, it is possible to improve the utilization efficiency of the process chamber of multiple effect is obtained that.

[0082] Also, it is possible to increase the quantity of the object to be processed per unit time in the integrated process to be performed sequentially combining multiple several treatment effect is obtained that.

[0083] Further, to avoid stopping of the whole device due like failure of maintenance management tasks and individual process chambers, it is possible to improve the operating rate.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram illustrating an example of a configuration of a multi-chamber apparatus that is Embodiment 1 of the present invention.

FIG. 2 is a flowchart illustrating an integrated process performed in the multi-chamber apparatus according to the first embodiment of the present invention.

FIG. 3 is a wafer processing diagram in the multi-chamber apparatus according to the first embodiment of the present invention.

FIG. 4 is a conceptual diagram illustrating an example of an operation of the multi-chamber apparatus according to the first embodiment of the present invention.

FIG. 5 is a conceptual diagram illustrating an example of a configuration of a multi-chamber apparatus that is Embodiment 2 of the present invention.

FIG. 6 is a conceptual diagram illustrating an example of a configuration of a multi-chamber apparatus that is Embodiment 3 of the present invention.

FIG. 7 is a conceptual diagram showing an example of a conventional multi-chamber apparatus.

FIG. 8 is a wafer processing diagram of a conventional multi-chamber apparatus.

FIG. 9 is a conceptual diagram showing an example of the operation of a conventional multi-chamber apparatus.

[Explanation of symbols]

Reference Signs List 1 Process chamber (for process A) 1a Process A specific digital output 1b Process chamber use status digital output 1c Process chamber CPU (first control means) 2 Process chamber (for process A) 2a Process A specific digital output 2b Process chamber Usage status digital output 2c Process chamber CPU (first control means) 3 Process chamber (for process A) 3a Process A specific digital output 3b Process chamber usage status digital output 3c Process chamber CPU (first control means) 4 Process chamber (for process B) 4a Process B specific digital output 4b Process chamber use status digital output 4c Process chamber CPU (first control means) 5 Process chamber (process) 5a Digital output for process C specification 5b Digital output of process chamber use status 5c CPU for process chamber (first control means) 6 Load lock chamber 6a Digital output of load lock chamber specific 6b Load lock chamber use digital output 6c Load lock CPU for chamber (first control means) 7 Wafer transfer chamber (connection means) 7a Transfer arm 7b Transfer table 7c CPU for wafer transfer chamber (first control means) 8 CPU for overall control (second control means) 9 Wafer progress management file 10 Throughput optimization algorithm 11 Process chamber 11a Process A specific digital output 11b Process chamber use status digital output 11c Process chamber CPU 12 Process chamber 12a Process B specific digital output 12b Process chamber usage digital output 12c Process chamber CPU 13 Process chamber 13a Process C specific digital output 13b Process chamber usage digital output 13c Process chamber CPU 14 Load lock chamber 14a Load lock chamber specific digital output 14b Load lock chamber usage digital output 14c Load lock chamber CPU 15 Wafer transfer chamber 15a Transfer arm 15b Transfer table 15c Wafer transfer chamber CPU 16 CPU for overall control 17 Wafer progress management file 18 Docking chamber (connection means) 19 Wafer transfer chamber (Connecting means) 20 Process chamber (for process B) 21 Process chamber (for process B) B) 22 Process chamber (for process C) 23 Process chamber (for process C) 24 Process chamber (for process C) 31 Process chamber (for process A) 31 g Gate valve mechanism 32 Process chamber (for process A) 32 g Gate valve Mechanism 33 Process chamber (for process A) 33 g Gate valve mechanism 34 Process chamber (for process B) 34 g Gate valve mechanism 35 Process chamber (for process C) 35 g Gate valve mechanism 36 Load lock chamber 37 Tunnel-shaped chamber (connection means) 38 Load lock chamber 39 Transfer arm 40 Transfer table 41 Transfer path

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/02 H01L 21/20

Claims (2)

(57) [Claims] A plurality of process chambers each independently performing a desired process on a semiconductor wafer; and a plurality of said process chambers interconnected by a closed space isolated from an external environment. A transfer for performing a transfer operation of the semiconductor wafer between chambers
A chamber and a load lock chamber for loading and unloading the semiconductor wafer
Of a semiconductor device using a multi-chamber apparatus having
A granulation method, a plurality of the multi-chamber apparatus, said process tea
Or a load lock chamber instead of the load lock chamber.
Connecting via a king chamber, the semiconductor wafer via the docking chamber,
By transporting through the plurality of multi-chamber devices,
A method for manufacturing a semiconductor device, comprising performing a process. 2. The system according to claim 2, wherein said docking chamber is connected to said docking chamber.
The plurality of multi-chamber devices held by
A function to perform the same kind of processing as a process chamber
A plurality of process chambers provided
The semiconductor device according to claim 1, wherein:
Production method.