JP3337700B2 - Image processing apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and an image processing method.

[0002]

2. Description of the Related Art With the recent increase in image quality and color of copiers, there has been a risk of counterfeiting of particular documents such as gift certificates and securities. On the other hand, as a method of recognizing a specific original in a copying machine, a method of detecting a distribution of color data of an input image and comparing both distributions of the input image and color data of the specific original image, and a method of detecting both an input image and a specific original image Is converted into a common color space, and in the common color space, an input image and a specific document image are compared in pixel units. In the case where the document is determined to be a specific document by the above method or the like, a technique of adding a dot pattern or the like which is hardly visible to human eyes to an output image is generally proposed by the present applicant.

[0003]

However, in recent years, an image processing apparatus for forming an image after temporarily storing an input image in a memory for storing image data has been used. In this image processing apparatus, image data remains in the memory simply by prohibiting image formation, and forgery may be possible by instructing image formation again. Further, an image processing apparatus which inputs image data from an input device having a memory for storing the image data and processes the image data to form an image has been used. In this image processing apparatus, similarly to the above-described image processing apparatus, simply prohibiting image formation leaves image data in the memory of the input device, and instructs another image processing apparatus to form an image. In some cases, forgery is possible.

[0004] The present invention addresses the above problems individually or
It is intended to be a collective solution and aims to effectively prevent counterfeiting.

[0005]

The present invention has the following configuration as one means for achieving the above object. An image processing apparatus according to the present invention includes a storage unit that holds input image data, an image processing unit that processes the input image data, and a similarity between an image represented by the input image data and a predetermined specific image. And control means for erasing the image data held in the storage means when the value is high. Input means for inputting image data stored in the memory from an input device having a memory; image processing means for processing the input image data; an image represented by the input image data and a predetermined specific image; Output means for outputting, to the input device, an instruction to delete the image data stored in the memory of the input device when the similarity with the input device is high.

According to the image processing method of the present invention, input image data is stored in a memory, and when processing the input image data, the similarity between an image represented by the input image data and a predetermined specific image is determined. When the value is higher, the image data held in the memory is erased. Also,
When inputting image data stored in the memory from an input device having a memory and processing the input image data, when the degree of similarity between the image represented by the input image data and a predetermined specific image is high. Preferably, an instruction to delete the image data stored in the memory of the input device is output to the input device.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below in detail with reference to the drawings. In the following embodiments, a copying machine is shown as an application example of the present invention, but the present invention is not limited to this, and other devices such as a printer and a printer interface may be used without departing from the spirit of the present invention. It is also possible to apply the present invention to an apparatus. In addition, the specific manuscript includes not only those whose copying is prohibited by law, such as banknotes and securities, but also everything up to specific uses such as confidential documents.

[0008]

FIG. 1 is a block diagram showing a configuration example of the present embodiment. In FIG. 1, reference numerals 122 and 123 denote a scanner a and a scanner b, respectively, which optically read an image of a document and convert it into RGB signals. Reference numeral 102 denotes an image processing unit (hereinafter referred to as “IPU”).
It receives the GB signal, converts the luminance signal into a density signal, and outputs a YMCK signal. The IPU 102 has a memory for storing at least one screen of image data.
Reference numeral 103 denotes a host computer, and a scanner 123
It receives the RGB signals, converts the luminance signal into a color system, and outputs an L ^* a ^* b ^* signal.

Reference numeral 104 denotes a still video camera (hereinafter, referred to as "SV"), and reference numeral 105 denotes a video tape recorder (hereinafter, referred to as "VTR"). A signal processing unit 100 is connected to the IPU 102, the host computer 103, the SV 104, the VTR 105, and other input devices, receives an image signal from each input device in the form of a color space handled by each input device, and converts the image signal into a print signal. Convert.

Reference numeral 112 denotes an image output device such as a printer. Next, in the signal processing unit 100, 106 is an arithmetic circuit having a memory, 107 is a conversion circuit, 108 is a color processing circuit, 109 is a specific original identification circuit, 110 is an image output control circuit, 113 is a display unit, Reference numeral 404 denotes an identification signal INH of the specific document identification circuit 109.

Next, an operation example of the signal processing unit 100 will be described. The image of the color original is read by the scanner a 122 and the scanner b 123 and becomes a digital signal separated into three colors of RGB, each of which has an image processing function.
It is sent to U102 and the host computer 103. IP
In U102 and the host computer 103, logarithmic conversion,
The masking calculation, the UCR and the calculation processing performed by the image processing unit of the ordinary digital color copying apparatus convert the input RGB signal into the YMCK signal, or input the RGB signal input to the IPU 102 or the host computer 103. Is converted to an XYZ color system XYZ signal, or the image signal converted to the XYZ color system is
^The input RGB signals are converted into various color spaces, such as being converted into L ^* a ^* b ^* signals of the ^* a ^* b ^* color system.

From RGB signals to tristimulus values XYZ in the XYZ color system,
Further, when the tristimulus values XYZ are converted into L * a * b *, the conversion formulas when the RGB signal conforms to the NTSC system are expressed by formulas (1) and (2). L * = 166 (Y / Yo) ¹ /3-16 a * = 504.3 {(X / Xo) ¹ /3-(Y / Yo) ^1/3 } b * = 201.7 {(Y / Yo) ^1/3 -(Z / Zo) ^1/3 }… (2) where Xo, Yo, and Zo are constant

As described above, image signals converted into signals in various color spaces by the IPU 102, the host computer 103, and the like are input to the signal processing unit 100. Also, SV104 and VT
An RGB signal is input to the signal processing unit 100 from a device such as R105. IPU102, host computer 103, SV104 and
When an image signal output from an input device such as the VTR 105 is a frame-sequential YMCK signal, the signal is divided into two systems, one to the image output control circuit 110 and the other to the arithmetic circuit 106.
Is input to Further, when the input to the signal processing unit 100 is a signal other than the YMCK in the frame sequence, the signal is output to the arithmetic circuit 106
Is input to

The arithmetic circuit 106 has a memory. When the input signal is a dot-sequential image signal, the signal is passed. When the input signal is a frame-sequential signal, the signal is temporarily stored in the memory. The signal is converted into a point-sequential signal. From the arithmetic circuit 106, RGB, YMCK, L ^* a ^* b ^* , XYZ
Various signals are output, and the signals are sent to the conversion circuit 107.

The conversion circuit 107 converts the input image signal into an image signal in a certain common color space (RGB signal in this embodiment). The image signal of the common color space output from the conversion circuit 107 is divided into two and sent to the color processing circuit 108 and the specific original identification circuit 109. FIG. 2 is a block diagram illustrating a configuration example of the conversion circuit 107 according to the present embodiment, and FIG. 3 is a diagram illustrating an example of a relationship between various color spaces and a common color space according to the present embodiment. The following shows the YMCK signal as RGB
An example of conversion into a signal will be described.

In FIG. 2, reference numerals 201, 202, and 203 denote adders c, m, and y, respectively.
The signal and the K signal, the M signal and the K signal, and the Y signal and the K signal are added. 204, 207 and 210 are multipliers, respectively, which add predetermined constants a11, a21 and a31 to the result of the adder c201.
Multiply. Numerals 205, 208, and 211 are multipliers which add predetermined constants a12, a22,
Multiply by a32. Reference numerals 206, 209, and 212 denote multipliers, each of which outputs a predetermined constant a13,
Multiply a23 and a33.

Reference numerals 213, 214, and 215 denote adders r, g, and b, which are multipliers 204, 205, and 2, respectively.
06, the outputs of multipliers 207, 208 and 209, and the outputs of multipliers 210, 211 and 212 are added. The adder r213 outputs the R signal, the adder g214 outputs the G signal, and the adder b215 outputs the B signal. The operation of the conversion circuit 107 is as follows. The C signal, M signal, and Y signal output from the arithmetic circuit 106 are input to an adder c201, an adder m202, and an adder y203, respectively. The K signal is divided into three, and is separately input to the adder c201, the adder m202, and the adder y203. Adder c
201, an adder m202, and an adder y203 calculate C '= C + K, M' = M + K, and Y '= Y + K, respectively, and output C', M ', and Y' to the multipliers 204 to 212. .

The signals multiplied by the predetermined values in the multipliers 204 to 212 are input to an adder r213, an adder g214, and an adder b215. Adder r213, adder g2
14, and the adder b215 outputs an R signal, a G signal, and a B signal, respectively. The above relationship is expressed as in equation (3).

[0019] Here, the coefficient matrix A in the expression (3) is an inverse matrix of the coefficient matrix of the masking process.

That is, as shown in FIG. 3, image signals in different color spaces are converted into image signals in a predetermined common color space by signal conversion or normalization. Even if the image signal is in the same color space, even if the axis is distorted due to the influence of the spectral characteristics when reading the original, the common color space determined in advance by signal conversion and normalization can be used. Convert to image signal.

The color processing circuit 108 receives the RGB signals from the conversion circuit 107, and performs logarithmic conversion, masking, UCR
And outputs a frame sequential YMCK signal.
On the other hand, the signal sent to the specific document identification circuit 109 determines whether or not the specific document image exists in the input image signal by a method described later. If the specific document identification circuit 109 determines that the specific document image exists in the input image signal, the INH 404 sent from the specific document identification circuit 109 to the image output control circuit 110 becomes “1”. The image output control circuit 110 stops outputting the input image signal while the INH 404 is “1”, prevents the image determined as the specific document image from being output from the image output device 112, and displays the image. Sends a signal to the unit 113,
Display image output disabled.

Conversely, if no specific original exists in the input image signal, INH 404 remains at "0". When the INH 404 is “0”, the image output control circuit 110 allows the input image signal to pass, and
12 is output. Next, an operation example of the specific document identification circuit 109 will be described. FIG. 4 shows a specific original identification circuit 1
FIG. 10 is a block diagram showing a configuration example of the embodiment 09.

In FIG. 4, reference numeral 515 denotes a CPU which controls the whole of the specific document identification circuit 109. 516 is ROM
Stores an operation program of the CPU 515 and the like. A RAM 517 is used as a work area for various programs. The CPU 515 mainly includes a counter a5
The data of the counter h528 and the SRAM 512 are read, and the existence of the specific document image in the input document image is checked.

Reference numerals 513 and 514 denote latches for latching a total of 15 bits of data of 5 bits each for RGB. Reference numeral 501 denotes a determination ROM, which stores image data of a specific document in an RGB space as indicated by hatching in FIGS. 5A and 5B. The determination ROM 501 of this embodiment is constituted by a ROM having a data width of 8 bits and an address width of 15 bits. In the determination ROM 501, bit 0 of the data at an arbitrary address represented by a total of 15 bits of 5 bits each for RGB indicates the presence or absence of image data of the first specific document, and bit 1 indicates image data of the second specific document. ..., Bit 7
Indicates the presence or absence of image data of the eighth specific document, and stores eight types of image data of the specific document.
As shown in FIG. 6, when the bit is "1", it means that the image data of the specific document corresponding to the bit exists, and when the bit is "0", the bit corresponds to the bit. This means that the image data of the specific document does not exist.

For example, when the image data of the third specific document exists at the address represented by the input RGB signals 313 to 315, bit 2 of the output of the determination ROM 501 is "1" and the other bits are "1". When it becomes "0" and the image data of the fourth specific document and the seventh specific document exist, the bits 3 and 6 of the output of the judgment ROM 501 are "1" and the other bits are "0". . When the image data of the specific document does not exist immediately, all the bits of the output of the determination ROM 501 become "0".

It should be noted that the data stored in the determination ROM 501 is not limited to the image data of a specific document, and it goes without saying that any specific image data may be stored.
The judgment result output from the judgment ROM 501 is the latch circuit 5
02 are input to the integrators a5011-h5018. FIG. 7 shows integrators a5011-h501.
8 is a diagram showing an example of the relationship between the input x _j and the output y _j of the E.8. When '1' is input to the integrator, the output y _j increases toward 255, and conversely, '0' Is input, the output y
_j decreases toward zero.

FIG. 8 shows integrators a5011-h50.
FIG. 18 is a diagram illustrating an example of a detailed configuration of FIG. In FIG. 8, 6
01 and 602 are multipliers, 603 is an adder, and 604 is a latch. 7 and 8, the input is x _j and the output is y _j
Then, the operation of Expression (4) is performed.

[0028] In Expression (4), β is a constant for controlling the integration effect of the integrator. The integration effect increases as β increases, and the integration effect decreases as β decreases. That is, the curve of the output y _j shown in FIG. 7 (a), beta is gradually changed closer to 1, beta changes rapidly closer to 0.

For example, assuming that a specific document is a document of the size of a bill, a value of about β = 31/32 is appropriate, and a size of a stamp or the like is about β = 7/8. . The value of β may be set arbitrarily by a scanning unit (not shown) according to the specific document. The comparison calculators a5001 to h5008 are respectively provided with inputs from the integrators a5011 to h5018,
It compares the input (constant) from the registers 5021 to 5028 and outputs comparison signals C1 to C8, respectively. When the input from the integrator is Ai and the input from the register is Bi, the comparison signal Ci is expressed by equation (5).

[0030] That is, the input image signal and the image data of the specific document continuously match, and the output A of the integrators a5011-h5028 is output.
While i exceeds the comparison constant Bi of the registers 5021 to 5028, the comparison operation units a5001 to h5
The output Ci of 008 is “1”. Conversely, when Ai is equal to or less than Bi, Ci is “0”.

The counters a521 to h528 are:
From the comparison operation units a5001 to h5008 to Ci
Is input, and when each input is “1”, clock C
Count up in synchronization with LK. That is, the counter a
The count values of 521 to h528 are as shown in FIG.
When the specific original image (hatched portion in the figure) is included in the original image shown in FIG. 9, the number of pixels in the recognized area (hatched portion in the drawing) is represented as the specific original image shown in FIG. 9B.

The OR write circuit 511 has a comparator a5
001 to output C1 to C8 of the comparator h5008
OR-write to AM512. The SRAM 512
Is a RAM having a data width of 8 bits and an address width of 15 bits as in the determination ROM 501. FIG. 10 is a block diagram showing a detailed configuration example of the OR write circuit 511 and the SRAM 512.

The address bus A0 of the SRAM 512
A14 receives RGB signals of 5 bits each, and D0 to D7 of the data bus include data 5 after OR operation described later.
120 to 5127 are input. Reference numeral 5112 denotes a timing signal generation circuit which generates a timing signal whose example is shown in FIG. The OR write circuit 511 outputs the clock CLK '.
During the period when the read signal OE synchronized with the address bus is “0”, the data of the address specified by the address buses A0 to A14
The data is read from the data buses D0 to D7 of the AM 512 and latched by a latch circuit connected to the data bus. Subsequently, the input signals 5120 to 5127 and the previously latched data are logically ORed by an OR circuit, and when the signal Rio becomes "0", an OR operation result is output from the buffer. At this time, since the write signal WE is "0" at the same time, the OR operation result is written to the address of the SRAM 512 specified by the address buses A0 to A14. The input signals 5120 to 5127 are respectively output from the comparison arithmetic unit a5.
001 to the output of the comparator h5008.

Thus, for example, the input signal 512
0, if the comparison result C1 of the comparison operation unit a5001 becomes "1" even once, it corresponds to an arbitrary address in the color space specified by each of the 5 bits of RGB.
Bit 0 of the address of the SRAM 512 becomes "1".
Similarly, if the other input signals 5121 to 5127 become "1" at least once, each of the bits 1 to 5 of the SRAM 512 address corresponding to an arbitrary address in the color space specified by each of the five RGB bits. '1' is recorded in bit 7.

The data recorded in the SRAM 512 in this manner represents the volume Tjd in the RGB space of the observable image data indicated by the oblique lines in FIG. 12 that matches the image data of the specific original image. For example, the total number of “1” s of bit 0 of the SRAM 512 is the volume of the observed image data in the RGB space that matches the image data of the first specific document image. Hereinafter, similarly, bits 1 to 7 of the SRAM 512 are the volumes of the observed image data that match the image data of the second to eighth specific original images.

FIG. 13 is a flowchart illustrating the control of the specific document recognizing circuit 109 by the CPU 515. In FIG. 13, when the CPU 515 detects the information of the document reading start, first, the INH 404 is set to “0” (S1201). Subsequently, reading of the document image is started (S1202), and 1 is set to a variable n (S120).
3). The variable n represents the number of the counter that stores the counter value in the RAM 517. At this time, since n = 1, the count value of the first counter a521 shown in FIG. 4 is represented by the variable area on the RAM 517. (S1204).

Subsequently, the total number of "1" s of bit n-1 of the SRAM 512 is stored in a variable vol on the RAM 517 (S1205). Here, the variable vol
Represents the volume Tjd of the observation image data shown in FIG. Subsequently, it is determined whether or not the value of the variable area exceeds a predetermined constant k (S1206). The value of the variable area is shown in FIG.
(B) corresponds to the number of pixels in the recognition area indicated by oblique lines. Accordingly, by comparing the value of the variable area with the constant k, it is determined whether or not there is a possibility that the document is a bill document, for example.
That is, when area ≧ k is YES, for example, it is determined that there is a possibility that the document is a bill document, and the process proceeds to the determination of the similarity R. Conversely, if area ≧ k is NO, for example, it is determined that the document is not a bill document, and the determination of the similarity R is passed.

Subsequently, the volume Tjd of the observation image data of the variable vol is compared with the volume Torg of the specific original image data previously registered and indicated by hatching in FIG. Calculated and compared with a constant β (S120
7). Here, the similarity R is represented by Expression (6). The closer the value of the similarity R is to 1, the higher the similarity between the observed image data and the specific document image data.

Therefore, in S1207, Vol = Tjd
Thus, the comparison of the expression (7) is performed. vol / Torg <β (7) In equation (7), the constant β is an experimentally determined value.
Indicates a matching ratio in a color space, for example, β = 0.
A value such as 7 is set. If the result of S1207 is YES, it is determined that the observed image data is a specific document image. Accordingly, INH404 is set to "1" in order not to output image data including the specific document image (S12).
08).

If the result of S1207 is NO, since n = 1 at this time, it is determined that the first specific document image is not included. Accordingly, in order to determine whether or not the next specific document image is included, the variable n is incremented (S1209), and the variable n exceeds 8 or S
Until the result of step 1207 becomes YES, S1204 to S1
Repeat 210.

Although the above description and FIGS. 1 to 13 have been described using RGB signals of 5 bits each, the present embodiment is not limited to this, and the determination ROM 51
Needless to say, the address width of the SRAM 2 or the SRAM 512 may be increased or decreased, and RGB signals of other bit numbers may be used. Also, the determination ROM 511 and the SRAM
The data width of 512 or the like is set to 8 bits, and the number of image data of a specific document that can be registered beforehand is set to 8. However, the present embodiment is not limited to this.
Increase or decrease the data width of the RAM 512,
It goes without saying that other data widths may be used to increase or decrease the number of image data of a specific document that can be registered beforehand.

As described above, according to this embodiment,
The image data of a plurality of specific documents, such as bills, gift certificates, securities, etc., registered previously and the image data of the input document are simultaneously compared in a predetermined color space. If it is determined that the input document image data includes at least one of the plurality of specific documents, the output of the input document image data is disabled, and information indicating that output is disabled is displayed on the display unit 113. Can be done. Therefore, it is possible to realize an image processing apparatus capable of simultaneously preventing various types of specific originals from being forged.

[0043]

Second Embodiment Hereinafter, a second embodiment according to the present invention will be described. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and detailed description is omitted. FIG.
FIG. 9 is a block diagram showing a configuration example of a second embodiment according to the present invention.

If the image data determined to be specific document image data is output from the IPU 102,
The image output control circuit 110 disables the output of the image data, displays information indicating that the image data cannot be displayed on the display unit 113, and sends a clear signal 124. Clear signal 1
By 24, the image data including the specific image data in the memory inside the IPU 102 is deleted.

In the above description and FIG.
Although an example in which the U102 is used as an input device has been described, the present embodiment is not limited to this, and it goes without saying that any input device having a memory for storing image data therein may be used. As described above, according to the present embodiment, the same effect as that of the first embodiment can be obtained, and in addition, the image data including the specific original image in the memory in the input device that has sent the input image data is deleted. It is possible to prevent forgery of a specific manuscript.

[0046]

Third Embodiment Hereinafter, a third embodiment according to the present invention will be described. If the image data including the specific document image is data transmitted from the host computer 103, a communication protocol is set between the signal processing unit 100 and the host computer 103, and the output output by the image output control unit 110 is output. The impossible information is sent to the host computer 103 according to the communication protocol, and the host computer 103
And output a message that cannot be output on a CRT or the like.

Further, in addition to the message that cannot be output, for example, "Because an input document contains a bill image ...
The reason that output is not possible, such as ".", Can be included in the message. In the above description, an example was described in which the host computer 103 was used as an input device.
The present embodiment is not limited to this, and it goes without saying that any input device having a display unit such as a CRT may be used.

As described above, according to the present embodiment,
In addition to obtaining the same effects as those of the first embodiment, a message that cannot be output can be output to the display unit of the input device. Can convey information. The present invention may be applied to a system including a plurality of devices or to an apparatus including one device. Needless to say, the present invention can also be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus.

[0049]

Fourth Embodiment Hereinafter, a fourth embodiment according to the present invention will be described. [Appearance of Apparatus] FIG. 15 shows an example of an appearance of an apparatus according to a fourth embodiment of the present invention. In FIG. 15, reference numeral 2201 denotes an image scanner which reads an original and performs digital signal processing. Reference numeral 2202 denotes a printer which prints out an image corresponding to the original image read by the image scanner 2201 on a sheet in full color.

In the image scanner 2201, 22
Reference numeral 00 denotes a mirror pressure plate, and the original 22 on the original platen glass 2203 is displayed.
04 is illuminated by a lamp 2205,
The light is led to 2208, forms an image on a three-line sensor 2210 by a lens 2209, and is decomposed into full-color information, red (R), green (G), and blue (B) components, and the light intensity of each component Signal processing unit 2
Sent to 211. The lamp 2205 and the mirror 22
06 is the speed v, and the mirrors 2207 and 2208 are the speed v /
2, electrical scanning (main scanning) of the three-line sensor 2210
By mechanical movement perpendicular to the direction,
The entire surface of the document is scanned (sub-scanning), and the read document image is sent to the signal processing unit 2211.

In the signal processing section 2211, the read image signal is temporarily stored in an image memory and then electrically processed, so that magenta (M), cyan (C), yellow (Y), black (K) ) And is sent to the printer 2202. In addition, image scanner 220
1, four reading operations are performed on the image data read by one original scanning, and one component among M, C, Y, and K is generated by image processing, respectively.
The data is sent to the printer 2202, and one printout is completed by a total of four readings and processes.

The M, C, Y, K image signals sent from the image scanner 2201 are transmitted to the laser driver 22.
12 is sent. The laser driver 2212 modulates and drives the semiconductor laser 2213 according to the sent image signal. The laser beam passes through a polygon mirror 2214, an f-θ lens 2215, and a mirror 2216,
17 is scanned.

Reference numeral 2218 denotes a rotary developing unit which includes a magenta developing unit 2219, a cyan developing unit 2220, and a yellow developing unit 22.
21; a black developing section 2222; the four developing sections alternately contact the photosensitive drum 2217 to develop the electrostatic latent image formed on the photosensitive drum with toner; Reference numeral 2223 denotes a transfer drum which winds a sheet supplied from a sheet cassette 2224 or 2225 and transfers an image developed on the photosensitive drum 2217 to the sheet.

After the four colors of M, C, Y, and K are sequentially transferred in this manner, the sheet passes through the fixing unit 2226, and is discharged after the toner is fixed on the sheet. [Image Scanner] FIG.
It is a block diagram which shows an example of the flow of the signal of No. 01.

In the figure, reference numerals 1210-1 to 3 denote CCD sensors (solid-state image sensors) having R, G, and B spectral sensitivity characteristics, respectively.
And A / D converted respectively, for example, 8
Outputs a bit signal. Therefore, each of R, G, B colors is
It is classified into 0 to 255 stages according to each light intensity.

Since the sensors 1210-1 to 1210-3 of this embodiment are arranged at a fixed distance, the delay element 1
Using 401 and 1402, the spatial shift is corrected. Reference numeral 1412 denotes an image memory, which is a sensor 1210-1.
The image data read by .about.3 is temporarily stored.

Reference numerals 1403 to 1405 denote logarithmic converters.
It is configured as a look-up table using M or RAM, and converts image data read from the image memory 1412 from a luminance signal to a density signal. Reference numeral 1406 denotes a well-known masking / UCR (under color removal) circuit. Although not described in detail, M, C, Y, and K signals for output are output at each read operation by three input signals. Then, a predetermined bit length such as 8 bits is output in a frame sequential manner.

Here, the signal CNO separately input to the masking / UCR circuit is a 2-bit field sequential signal, an example of which is shown in Table 1, controls the order of the four transfer operations, Switch operating conditions.

[0059]

[Table 1] A known spatial filter circuit 1407 corrects the spatial frequency of the output signal. Reference numeral 1408 denotes a density conversion circuit which corrects the density characteristics of the printer 2202, and is configured by the same ROM or RAM as the logarithmic converters 1403 to 1405.

On the other hand, reference numeral 1409 denotes a specific document image determining circuit which determines whether at least one of a plurality of specific document images exists in the input image, and outputs a determination signal H. That is, when it is determined that at least one of the plurality of specific document images is present in the input image, the determination signal H = 1 is determined.
H = 0 is output. Receiving H, the CPU 1411 outputs a copy prohibition signal NG. That is, when H = 1,
NG = 1 is output, and when H = 0, NG = 0 is output.

The signal SNO is a selection signal of a specific document image to be determined, which is output from the CPU 1411 and is sequentially switched from 0 to 7 to determine a plurality of specific documents. Reference numeral 1410 denotes an OR gate.
08, and a logical sum V ′ of the copy inhibition signal NG from the CPU 1411 is output.

As a result, when the determination signal H = 1, that is, when it is determined that the specific original image exists in the input image, regardless of the value of the signal V, for example, the output V ′ = FF (255) ), All the toners of M, C, Y, and K are developed / transferred over the entire surface, and the output image is painted black. Conversely, when H = 0, that is, when it is determined that the specific document image does not exist in the input image,
The signal V is output as it is as the output V '.

[Judging Means] FIGS. 17 and 18 show the judging circuit 1.
FIG. 409 is a block diagram illustrating a configuration example of a 409. Reference numeral 1301 denotes a thinning circuit, an example of which is shown in FIG. 19A. The thinning circuit 1301 outputs image data in which some data of the input image is thinned in order to reduce the processing load of the determination circuit 1409.

Reference numeral 1310 denotes a color matching circuit, which is a RAM 1302 for a color matching look-up table;
It is composed of tristate gates 1311 to 1313, an inverter 1314, a control circuit 1315, and a battery 1316 for retaining the stored contents of the RAM 1302 regardless of the power ON / OFF state of the apparatus main body.

The RAM 1302 checks the color distribution of 64 types of specific documents in advance so as to match the colors with a plurality of types of specific documents, and stores the color of the input image and the color of the specific document image. Are stored as information for determining whether or not they match. The determination information stored in the RAM 1302 is retained by the battery 1316 even when the power of the apparatus main body is turned off.

The control circuit 1315 outputs WE as a control signal.
And MSEL, and read / write control of the RAM 1302,
In addition, the control of the tri-state gates 1311 to 1313 is performed. Control of the control circuit 1315 has the following two modes. (1) Normal control mode in which the RAM 1302 operates as a look-up table (2) RAM rewrite mode in which the RAM 1302 is rewritten In the normal control mode, the control circuit 1315 fixes the MSEL to “1”, thereby causing the tristate gate 131 to operate.
1 through which the signal passes and the tri-state gate 1312
And 1313 to prevent the signal from passing, and RA
The terminal OE of M1302 is set to “0”. Further, the signal WE
Is fixed at “1”. Therefore, the RAM 1302 is in the data output enable state and functions as a look-up table.

The upper three address terminals of the RAM 1302
The selection signal SNO from the CPU 1411 is
The lower 5 bits receive the upper 5 bits of the thinned RGB image signal. The value of the SNO is sequentially switched from 0 to 7, and it is determined whether or not the color of the pixel of the input image matches the color of the eight specific original images.
Output is simultaneously made in correspondence with 8-bit data, and a total of 64 types of specific originals are determined in a total of eight determination operations when the SNO value is 0 to 7.

That is, a feature of the present invention is that various kinds of specific originals can be determined with simple hardware by sequentially switching the selection signal SNO and repeatedly determining. Further, even when the type of the specific document to be determined is increased from, for example, 64 to 128, the number of repetitions of the determination based on the selection signal SNO may be increased, so that the hardware load is not greatly increased.

Reference numerals 1303-1 to 130-8 denote color judgment circuits each constituted by the same hardware.
It comprises a register 1307 and a comparator 1308, each of which determines whether or not a specific document image exists in the input image. The output of the tint determination circuits 1303-1 to 1303-1 is "1" when it is determined that the specific original image to be processed is present in the input image, and is "0" when it is determined that the specific original image is not present. Become.

Reference numeral 1309 denotes an OR gate.
If at least one of the outputs of 303-1 to 30-8 becomes "1",
The determination signal H = 1 is output, and when all the outputs of the tint determination circuits 1303-1 to 130-3 are “0”, H = 0 is output. On the other hand, in the RAM rewrite mode, the control circuit 1315
The RAM 1302 is rewritten based on data transferred from the outside. That is, by fixing the signal MSEL to “0”, the signal is prevented from passing through the tri-state gate 1311 and the tri-state gates 1312 and 13
The signal is passed to 313, and the terminal OE of the RAM 1302 is set to “1”. Further, the signal WE is fixed to “0”. Therefore, the RAM 1302 is in the data write enable state, and the RAM 1302 indicated by the address signal A1.
Is rewritten to the data signal D1. Further, once updated contents of the RAM 1302 are retained by the battery 1316 independently of the power supply of the apparatus main body, and are retained until the next update even when the power supply of the apparatus main body is turned off. .

[Timing Chart] FIG. 20 is an example of a main scanning timing chart in the normal control mode of this embodiment. HSYNC is a main scanning synchronization signal that synchronizes the start of main scanning. CLK is an image transfer clock, which is a basic clock for various image processing in this embodiment.

On the other hand, CLK 'is obtained by dividing CLK by 4 and is a basic clock in the decision circuit 1409.
The signal SEL is a timing signal used in the thinning circuit 1301 described above. CLK 'and SEL are shown in FIG.
This is generated by a frequency dividing circuit 1310 shown in FIG. That is, an inverter 1451, a 2-bit counter 1452, an inverter 1453, and an AND gate 1454.
And the 2-bit counter 1452 has the HSYN
After being cleared (initialized) by C, CLK is counted and the count value is output in two bits. The upper bit D1 is output as CLK 'and the lower bit D0 is output.
Is the logical product of the inverted signal and the upper bit D1.
Output as L.

FIG. 19A shows a thinning circuit 1 having a configuration example.
Reference numeral 301 denotes a flip-flop (hereinafter, referred to as "F / F") 1455 to 1457 and 1 for holding data with CLK.
461 to 1463, selectors 1458 to 1460, CL
F / Fs 1464 to 1466 holding data at K ′, as shown in FIG. 20, an example of R (or G, B) signals transferred at CLK at a rate of 1/4
An R ′ (or G ′, B ′) signal synchronized with CLK ′ can be obtained.

[Integrator] FIG. 21 is a block diagram showing a configuration example of the integrator 1306. Reference numerals 1501 and 1505 denote F / Fs, which hold data at the rise of CLK '. 1
A multiplier 502 receives two 8-bit signals (A, B) and outputs an 8-bit signal (A × B / 255) as a multiplication result. A multiplier 1503 is also a 1-bit signal (A).
And an 8-bit signal (B) are input, and an 8-bit signal (A × B) is output as a multiplication result.

An adder 1504 receives two 8-bit signals (A and B) and outputs an 8-bit signal (A) as an addition result.
+ B) is output. As a result, the integrator 1306, 2
The relationship between the value input signal x _i and the 8-bit output signal y _i is expressed by the following equation. y _i = (α / 255) y _{i -1} + β x _{i -1} (8) In the above equation, α and β are constants set in advance, and are integrated according to the magnitudes of these values. The characteristics of the vessel 1306 are determined.

For example, FIG. 22 shows an example of input and output of the integrator 1306 when α = 247 and β = 8. That is, with respect to the input x _i as shown in FIG. 22 (a), FIG. 2
An output _yi as shown in FIG. 2 (b) is output. In FIG. 22, an input x such as 701 and 702, which is almost “0” before and after “1”, is almost “0”.
Inputs x _i such as _i and 703 that are “0” despite being almost “1” before and after are considered to be noise. The input x _i is integrated by the integrator 1306, and the comparator 1308 binarizes y _i by an appropriate threshold value set in the register 1307, as shown as an example in 704 of FIG. , The above-described noise can be removed.

The CPU 1411 shown in FIG.
The quantified signal is input as the determination signal H. If it is determined that a specific document image exists in the input image, H
= 1, but the CPU 1411 receives this and sets the copy prohibition signal NG = 1. If it is determined that the specific document image does not exist in the input image, H = 0 remains, and the CPU 1411 receives this and keeps NG = 0.

[Flowchart] FIG. 23 is a flowchart showing an example of the processing procedure of this embodiment. First, at step 801, an original image is read and the image memory 1412 is read.
Accumulates the image read. Next, in step 802,
A specific document image determination is performed on the input image of the image memory 1412.

Next, in step 803, when it is determined that the specific original image exists in the input image, step 8
In step 04, the CPU 1411 sets the copy prohibition signal NG to "1". If it is determined that the signal does not exist, the process proceeds to step 805, in which the CPU 1411 sets NG to "0". Further, in step 806, the image memory 14
12 is read out, a magenta signal is generated and output.

Next, steps 807, 808, 809
Then, the image data in the image memory 1412 is sequentially read, and cyan, yellow, and black signals are generated and output.

[0081]

Fifth Embodiment In the fourth embodiment, when it is determined that a specific document image exists in an input image, the output image is painted black, but the present invention is not limited to this.
Hereinafter, a fifth embodiment according to the present invention will be described. The fifth
In the embodiment, the same components as those of the fourth embodiment are denoted by the same reference numerals, and the detailed description is omitted.

FIG. 24 is a flowchart showing an example of the processing flow of this embodiment. First, in step 901, an original image is read, and the read image is stored in the image memory 1412. Next, in step 902, the image memory 1412
The specific original image determination is performed on the input image in the inside.

Next, in step 903, if it is determined that the specific original image exists in the input image, the image output is prohibited, the process is terminated, and if it is determined that there is no specific original image, the next step is performed. And output the image. That is, the process proceeds to step 904, where the image data in the image memory 1412 is read, and a magenta signal is generated and output.

Next, steps 905, 906, and 907
Then, the image data in the image memory 1412 is sequentially read, and cyan, yellow, and black signals are generated and output.

[0085]

Sixth Embodiment Further, as a sixth embodiment according to the present invention, a color copying machine which encodes a read image, stores it in a memory, and outputs it will be described. [Description of Apparatus Outline] FIG. 25 shows an example of an external view of the apparatus according to the sixth embodiment.

Reference numeral 1201 denotes a document table glass on which a document 1202 to be read is placed. The manuscript 1202 has the illumination 12
The image is formed on the CCD 1208 by the optical system 1207 through the mirrors 1204 to 1206. Further, a mirror unit 121 including a mirror 1204 and an illumination 1203 is mechanically driven by a motor 1209.
0 is the speed v, the second mirror unit 1211 including the mirrors 1205 and 1206 is driven at the speed v / 2, and
The entire surface of 202 is scanned.

Reference numeral 1212 denotes an image processing unit which processes the read image as an electric signal and outputs it as a print signal. Reference numerals 1213 to 1216 denote semiconductor lasers, which are driven by a print signal output from the image processing unit 1212, and laser light emitted by each of the semiconductor lasers is
Latent images are formed on the photosensitive drums 1225 to 1228 by the polygon mirrors 1217 to 1220. 1221
Reference numeral 1224 denotes a developing device for developing a latent image by using K, Y, C, and M toners. The developed toners of each color are transferred to a sheet, and a full-color print output is performed.

The paper fed from any of the paper cassettes 1229-1231 and the manual feed tray 1232
After being transferred to the transfer belt 1234 via the registration roller 1233, the sheet is conveyed. The toner of each color is developed in advance on the photosensitive drums 1228 to 1225 in synchronization with the sheet feeding timing, and the toner is transferred to the sheet as the sheet is transported.

The paper on which the toner of each color is transferred is separated and conveyed from the transfer belt 1234, the toner is fixed on the paper by the fixing device 1235, and the paper is discharged to the paper discharge tray 1236. [Flow of Image Signal] FIGS. 26 and 27 show the image processing unit 121.
FIG. 4 is a block diagram showing an example of a signal flow of No. 2;

Reference numerals 1101 to 1103 denote R, G, and B, respectively.
The outputs of the sensors 1101 to 1103 are amplified by analog amplifiers 1104 to 1106.
The signals are converted into digital signals by the / D converters 1107 to 1109, respectively. Reference numerals 1110 to 1111 denote delay elements for correcting a spatial displacement between the sensors 1101 to 1103.

Reference numerals 1151 to 1156 denote tristate gates, which pass respective input signals when the signals OE1 to OE6 sent from the CPU (not shown) are "0" according to the contents of the scaling process. Table 2 shows the scaling content and signal O
An example of the relationship between E1 and OE6 is shown.

[0092]

[Table 2] Reference numerals 1157 to 1160 denote scaling circuits for scaling an image signal in the main scanning direction.

A color space converter 1112 converts an RGB signal into a lightness signal L ^* and chromaticity signals a ^* and b ^* . Here, the L ^* a ^* b ^* signal is represented by L ^* a ^* b ^{* in} CIE ^.
It is a signal representing a chromaticity component of a color space defined as a space. The L ^* a ^* b ^* signal is represented by the following equation. Where αij, X0, Y0, Z0 are constants of X, Y, Z
Is a signal generated by calculating an RGB signal, and is represented by the following equation.

[0094] Where βij is a constant 1113 is an encoder a for the brightness signal,
The signal L ^* is coded in units of 4 × 4 pixel blocks, and a coded signal L-code is output. Reference numeral 1114 denotes a chromaticity signal encoder b which encodes the signals a ^* and b ^* in units of 4 × 4 pixel blocks and outputs a code signal ab-code.

On the other hand, reference numeral 1115 denotes a feature extraction circuit for detecting the presence or absence of two types of features for the pixel. A first feature is a black pixel, and a black pixel detection circuit 1115-1 generates a determination signal K1 'as to whether or not the pixel is a black pixel. Further, the signal K1 ′ is output to the 4 × 4 area processing circuit 1115-3.
And a determination signal K1 for determining whether or not a 4 × 4 pixel block is a black pixel area.

The second feature is a character pixel, and a character area detection circuit 1115-2 generates a determination signal K2 'as to whether or not the pixel is a character pixel. Further, the signal K2 ′ is 4 ×
A determination signal K2 which is input to the four area processing circuit 1115-4 and determines whether or not a 4 × 4 pixel block is a character area.
Becomes Reference numeral 1116 denotes an image memory, which is a brightness code signal Lc.
mode, a chromaticity code signal ab-code, and determination signals K1 and K2 as a result of feature extraction.

Reference numerals 1141 to 1144 denote M, C,
Density signal generators for Y and K.
The configuration is as follows. Reference numeral 1117 denotes a brightness information decoder,
The signal L from the L-code read from the memory 1116
^*1118 is a chromaticity information decoder, and
Signal a from ab-code read from^*
And b^*Is decrypted. Reference numeral 1119 denotes a color space converter, which
Signal L^*, A^*, B ^*With M, which is the toner development color,
Conversion into each of C, Y, and K color components. 1120 is density conversion
With a look-up table of ROM or RAM.
Is done. Reference numeral 1121 denotes a spatial filter, which is a space of an output image.
Perform frequency correction.

On the other hand, reference numeral 1161 denotes a decoding circuit similar to 1117 for decoding the brightness signal L ^* . 1162 is 111
8, the chromaticity signals a ^* and b ^* are decoded.
Reference numeral 1163 denotes a color space converter.
The inverse conversion of equation (0) is performed to convert the L ^* a ^* b ^* signals into RGB signals. Reference numeral 1164 denotes a specific document image determination circuit similar to 1409 in FIG. 16, and determines the presence or absence of the specific document image in the input image in the same manner as in the fourth embodiment.

[Flowchart] FIG. 28 is a flowchart showing an example of the processing flow of this embodiment. First, at step 711, an original image is read and the image memory 111 is read.
Then, the read image is stored in step S6. Next, step 712
Then, the specific original image determination is performed on the input image in the image memory 1116.

Next, in step 713, if it is determined that the specific original image exists in the input image, the image output is prohibited, the processing is terminated, and if it is determined that the specific original image does not exist, the next step is performed. The flow shifts to 714, where an image is output and the process ends. As described above, according to the fourth aspect of the present invention,
According to the sixth to sixth embodiments, an image processing apparatus that determines whether at least one specific document image among a plurality of specific documents exists in an input image, temporarily stores the image in a memory. In the image processing device that outputs after, the presence or absence of a specific document image for the image data in the memory,
Further, by sequentially switching the type of the specific document image to be determined and repeatedly determining the type, there is an effect that even if the number of specific documents to be determined is increased, the load on the hardware does not increase significantly.

[0101]

Seventh Embodiment Hereinafter, a seventh embodiment according to the present invention will be described. In the seventh embodiment, the same components as those in the sixth embodiment are denoted by the same reference numerals, and detailed description is omitted. [Explanation of Apparatus Outline] An example of the appearance of the apparatus in this embodiment is the same as the example of the appearance of the apparatus in the sixth embodiment shown in FIG.

[Image Forming Timing Chart] FIG. 29 is an example of a timing chart relating to image forming in this embodiment. In FIG. 29, a signal START is a signal indicating the start of a document reading operation. The signal WPE indicates a section in which the image scanner reads a document image, performs an encoding process, and writes data in a memory. The signal ITOP is a signal indicating the start of the printing operation, and the signals MPE, CPE, YPE, KPE
Is a magenta semiconductor laser 1216, a cyan semiconductor laser 1215, and a yellow semiconductor laser 12 shown in FIG.
14. Section signals for driving the black semiconductor laser 1213, respectively.

As shown in FIG. 29, CPE, YPE, K
The PE sets the time t1, t2, t with respect to the MPE, respectively.
3 which is equivalent to the distance d1, shown in FIG.
d2 and d3 are controlled according to the following equation. t1 = d1 / v, t2 = d2 / v, t3 = d3 / v (11) where v is a paper feed speed signal HSYNC is a main scanning synchronization signal, and signal CLK is a pixel synchronization signal. The signal YPHS is a 2-bit count value of the main scanning counter, and is a signal of the inverter 100 shown in FIG.
It is generated by a circuit composed of 1 and 2 bit counters 1002 and 1003.

The signal BLK is a synchronization signal in units of 4 × 4 pixels, and is processed in units of 4 × 4 blocks at the timing indicated by BDATA. [Flow of Image Signal] FIGS. 31 and 32 show the image processing unit 121.
FIG. 4 is a block diagram showing an example of a signal flow of No. 2;

Reference numeral 1171 denotes a specific document image determination circuit which determines the presence or absence of a specific document image in an input image in the same manner as in the fourth embodiment. 1170 is a CPU for controlling the present embodiment.
Then, the judgment result signal H from the judgment circuit 1171 is input. [In the case of enlargement processing] In the first mode for performing enlargement processing,
The scaling process is performed before the encoding (compression) process. Therefore, as shown in Table 2 above, OE1, OE3, OE6
Are "0" in the three signals, OE2, OE4,
"1" is set for each of the three signals of OE5,
Of the 3-state gates, 1151, 1153, 1
156 passes the input signal, 1152, 1154, 1
156 does not pass the input signal.

As a result, the RGB image signals synchronized by the delay elements 1110 and 1111 first pass through the tri-state gate 1151, and are scaled by the scaling circuits 1157 to 1111.
Enlargement processing is performed at 59. Here, the detailed operation of the scaling processing circuit is described in, for example, Japanese Patent Application No. 1-199344. Next, the RGB image signal that has been subjected to the enlargement processing passes through a tri-state gate 1153 and passes through a color space converter 1112.
And sent to the feature extraction circuit 1115. Encoder 11
13, 1114, the image coded signal L
-Code, ab-code, and feature extraction circuit 1115
Are extracted from the image memory 1
It is sent to 116 and held.

The codes read from the image memory 1116 are the density signal generation units 114 for M, C, Y, and K, respectively.
At 1 to 1144, the image data is decoded (expanded) into a density image signal.
It is sent to the Y and K laser drivers. [In the case of reduction processing] In the second mode for performing reduction processing,
The scaling process is performed before the encoding (compression) process. Therefore, as shown in Table 2 above, OE2, OE4, OE5
OE1, OE3, OE3
"1" is set to each of the three signals of OE6,
Of the 3-state gates, 1152, 1154, 1
155 becomes valid, and 1151, 1153, and 1156 become invalid.

As a result, the RGB image signals synchronized by the delay elements 1110 and 1111 are first sent to the color space converter 1112 and the feature extraction circuit 1115 via the tri-state gate 1152. Encoder 111
3,1114, the image code signal Lc
mode, ab-code and the characteristic signals K1 and K2 extracted by the characteristic extraction circuit 1115 are stored in the image memory 111.
6 and held there.

The codes read from the image memory 1116 are the density signal generators 114 for M, C, Y, and K, respectively.
At 1 to 1144, the image data is decoded (expanded) into a density image signal, passes through a tri-state gate 1155, and is scaled.
The reduction processing is performed at ~ 1160. The reduced image signal is sent to the M, C, Y, and K laser drivers via the tri-state gate 1154.

[Area Processing] FIG. 33 is a block diagram showing a configuration example of the 4 × 4 area processing circuit 1115-4. In FIG. 33, CLK is a pixel synchronization signal, and HSYNC is a main scanning synchronization signal. Reference numerals 901 to 903 denote line memories that provide a delay of one line. Each of the signals X1, X2, and X3 corresponds to one signal in the sub-scanning direction with respect to the input signal X.
There is a delay of two lines, two lines, and three lines. 904 and 909 are adders, and 905 to 908 are F / Fs. As a result, X and X corresponding to four pixels in the sub-scanning direction of the binary signal X are obtained.
Among 1, 1, and X3, the number of "1" is counted.

Reference numeral 910 denotes a two-input one-output selector.
Is a NOR gate, 912 is an F / F, and the number of pixels C1 where X = 1 is calculated in units of 4 × 4 blocks in synchronization with the signal BLK generated from the XPHS bit 0 and the XPHS bit 1 Then, the output Y is compared with a comparison value C2 preset in the register 913. When C1> C2, the output Y becomes "1", and when C1≤C2, the output Y becomes "0", as shown in BDATA of FIG. Y is output at the same timing.

Here, the characteristic feature is that the code signals L-code and ab-code obtained by encoding and the characteristic signals K1 and K2 extracted by the characteristic extraction circuit are shown in FIG. (4 × 4) blocks correspond to one-to-one. That is, the image code and the characteristic signal are extracted in units of 4 × 4 pixel blocks, stored at the same address in the memory, or at an address calculated from the same address, and read out correspondingly. be able to.

That is, by storing the image information and the characteristic (attribute) information in the same address in the memory or at the address calculated from the same address, for example,
Memory write and read control circuits can be shared and simplified, and editing processing such as scaling / rotation can be performed with simple processing on the memory, thus optimizing the system. It can be performed.

FIG. 35 shows a specific example of area processing relating to character pixel detection. For example, FIG. 35A shows a result of determining whether or not each pixel is a character pixel by the character area detection circuit 1115-2 for a part 1201-1 of the image of the original 1201 as shown in FIG. b). The pixel indicated by the mark “の” in FIG.
Among the pixels detected at 115-2, the output corresponding to the same pixel is K2 ′ = 1, and the outputs corresponding to the other pixels are K2 ′ = 0.

The result of this determination is sent to the area processing circuit 1115.
-4, the register 913 shown in FIG.
By setting 4 and performing area processing, if there are five or more pixels determined to be character pixels in each 4 × 4 block, the pixel is determined to be a block of a character area and is determined to be a character pixel. If is less than four, it is determined that the block is not a block of a character area.

The output of the area processing circuit 1115-4 is a signal K2 with reduced noise as shown in FIG. Similarly, the black pixel detection circuit 1115-1
Area processing circuit 11
By processing in step 15-3, a signal K1 corresponding to 4 × 4 blocks can be obtained.

[Color Space Converter] FIG. 36 shows a color space converter 1.
FIG. 119 is a block diagram showing an example of the configuration of the embodiment 119. 2501 is L
A color space converter that converts ^* a ^* b ^* signals to RGB signals.
Conversion is performed by the following equation. Note that βij ′ (i, j = 1,2,3) in equation (12) is the inverse matrix of βij (i, j = 1,2,3) in equation (10). Also, αi in equation (14)
j ′ (i, j = 1,2,3,4) is the inverse matrix of αij (i, j = 1,2,3,4) in equation (9).

Reference numerals 2502 to 2504 denote logarithmic converters for performing the following conversion. Reference numeral 2514 denotes a black extraction circuit which generates a black signal K1 according to the following equation.

K1 = min (M1, C1, Y1) (16) 2505 to 2508 are multipliers, respectively.
A predetermined coefficient a1, a2, a3 is added to each signal of Y1 and K1.
After multiplication by a4, the sum is added in the adder 2515. Equation (17) represents the output M from the adder 2515. M = a1 · M1 + a2 · C1 + a3 · Y1 + a4 · K1 (17) Reference numerals 2509 to 2513 denote registers, and the density signal generation unit m1
In the same register 141, a11, a21, a31, a41, 0
However, in the same register of the density signal generation unit c1142, a1
2, a22, a32, a42, 0 are the density signal generation units y114
In the same register of No. 3, a13, a23, a33, a43, 0
The same register of the density signal generation unit k1144 stores a14, a
24, a34, a44 and a14 'are set.

2531 to 2533 are AND gates, 25
Reference numeral 30 denotes a two-input one-output selector, and reference numeral 2520 denotes a NAND gate. As a result, it is checked from the logical product of the signals K1 and K2 whether the pixel is included in a black character area. , A2, a3, and a4 are selected. Further, when the pixel is not included in the black character area, the processing of the following equation (18) is performed. When the pixel is included in the black character area, the processing of the following equation (19) is performed.

[0121]

[Table 3] That is, in the black character area, as shown in Expression (19),
By outputting in K single color, an output without color shift can be obtained. On the other hand, in the region other than the black character region, as shown in Expression (18), output is performed in four colors of MCYK.
By the calculation of the equation (18), the M1, C1, Y1, and K1 signals based on the RGB signals read by the CCD sensor are
The MCYK signal based on the spectral distribution characteristics of the toner is corrected and output.

[Spatial Filter] FIG. 37 shows a spatial filter 1
FIG. 2 is a block diagram showing an example of the configuration of FIG. In FIG. 37, reference numerals 801 and 802 denote line memories that provide a delay of one line, and 803 to 809 denote F / Fs, which provide a delay of one pixel. 810 and 811 are adders, and 812 to 814 are multipliers, respectively, which are multiplied by coefficients b1, b0 and b2, respectively, and then added in an adder 815.

On the other hand, reference numerals 816 to 821 denote registers, respectively. The values of b11, b12, b01, b02, b21, and b22 are held in the respective registers in advance, and
22 to 824, the values are set to b1, b0 and b2 in accordance with the signal K2 indicating that the pixel is included in the character area. Table 4 below shows the relationship between K2 and the values of b0, b1, and b2. For example, b01 = 4/8, b11 = 1 /
8, b21 = 1/8, b02 = 12/8, b12 = -1 / 8,
The value of b22 = -1 / 8 is previously stored in the registers 816 to 821.
, K2 = 0 as shown in Table 4.
(Ie, non-character area pixels), a smoothing filter is formed to remove high frequency component noise in the image. On the other hand, when K2 = 1 (that is, a character area pixel), an edge enhancement filter is formed to emphasize the edge portion of the character.

[0124]

[Table 4] [Pixel Correction Means] FIG. 38 is a block diagram showing a configuration example of a pixel correction circuit.

In FIG. 38, CLK is a pixel synchronization signal, and HSYNC is a horizontal synchronization signal. 401, 402
Is a line memory which gives a delay of one line. 403
411 are F / Fs, each of which gives a delay of one pixel. As a result, as shown in FIG.
22 and 7 pixels X11, X12 and X1 around X22
A total of eight pixels of 3, X21, X23, X31, X32, and X33 are output.

Reference numerals 411 to 414 denote pixel edge detection circuits.
As shown in FIG. 39B, a value of | A−2B + C | / 2 is output for three inputs of A, B, and C. The target pixel X22 is input to all input terminals B of the four pixel edge detection circuits. X12 and X32 are input to the input terminals A and C of the edge detection circuit 411, respectively. As a result, a = | X12−2 · X22 + X32 | / 2 is output. It becomes the absolute value of the secondary differential amount in the sub-scanning direction shown by θ1, and represents the edge strength in the θ1 (sub-scanning) direction.

X11 and X33 are input to the input terminals A and C of the edge detection circuit 412, respectively.
| X11-2 · X22 + X33 | / 2 is output, where b is
The absolute value of the second derivative in the diagonally lower right direction, shown as θ2 in FIG. 39 (c), is the absolute value of the edge in the θ2 (diagonally lower right) direction. The input terminals A and C of the edge detection circuit 413
X21 and X23 are input, and as a result, c = | X
21−2 · X22 + X23 | / 2 are output.
The absolute value of the secondary differential amount in the main scanning direction indicated by θ3 in FIG. 9C is shown, and represents the edge strength in the θ3 (main scanning) direction.

X31 and X13 are input to the input terminals A and C of the edge detection circuit 414, respectively.
| X31-2.X22 + X13 | / 2 is output, where d is
The absolute value of the second-order differential amount in the obliquely rightward upper direction, shown as θ4 in FIG. 39C, represents the edge strength in the θ4 (diagonally upper rightward) direction. 415 shown in FIG. 38 is a maximum value detection circuit.
For four inputs b, c, and d, which input is the largest is determined, and a 2-bit determination result y is output.

FIG. 40 is a block diagram showing a detailed configuration example of the maximum value detection circuit 415. In FIG. 40, 421
Is a comparator which compares the input a with the input b and outputs "1" when a> b, and outputs "0" when a≤b. 422 is 2
In the selector of one input, inputs a and b are input to input terminals A and B, respectively, and a comparison result of the comparator 421 is input to a select terminal S. As a result, the maximum value max of a or b is obtained.
(A, b) is output.

Similarly, the input c from the comparator 423
The selector 424 outputs a comparison result of the input d and the maximum value max (c, d) of c or d. Further, the maximum value max (a, b) and the maximum value max (c,
d) is compared by the comparator 425 to output a signal y1. As a result, of the inputs a, b, c, d,
When a or b is maximum, y1 = 1, and when c or d is maximum, y1 = 0.

428 is an inverter, 426, 427, 4
Reference numeral 29 denotes a two-input NAND gate. As a result, when a or c is the maximum among the inputs a, b, c, and d, y0 = 1, and when b or d is the maximum, y0 = 0.
Becomes That is, the maximum value max of a, b, c or d
According to (a, b, c, d), a 2-bit output y1y0 is output according to the following relationship.

When max (a, b, c, d) = a, y1y0 = 1
When 1 max (a, b, c, d) = b y1y0 = 1
When 0 max (a, b, c, d) = c y1y0 = 0
When 1 max (a, b, c, d) = d y1y0 = 0
0 416 to 419 shown in FIG. 38 are smoothing circuits, respectively.
As shown in FIG. 39A, a value of (A + 2B + C) / 4 is output for three inputs A, B, and C. The target pixel X22 is input to all input terminals B of the four smoothing circuits 416 to 419.

The input terminals A and C of the smoothing circuit 416
X12 and X32 are input, and as a result, a '=
(X12 + 2.X22 + X32) / 4 is output, but a '
Is an output subjected to smoothing processing in the sub-scanning direction indicated by θ1 in FIG. 39 (c). X11 and X33 are input to the input terminals A and C of the smoothing circuit 417, respectively. As a result, b '= (X11 + 2.X22 + X33) / 4 is output. This is an output obtained by performing a smoothing process in a diagonally lower right direction indicated by θ2.

The input terminals A and C of the smoothing circuit 418
X21 and X23 are input respectively, and as a result, c ′ =
(X21 + 2.X22 + X23) / 4 is output, but c '
Is an output obtained by performing a smoothing process in the main scanning direction indicated by θ3 in FIG. X31 and X13 are input to the input terminals A and C of the smoothing circuit 419, and as a result, d '= (X31 + 2.X22 + X13) / 4 is output. This is an output obtained by performing a smoothing process in an obliquely rightward upward direction indicated by θ4.

Reference numeral 420 denotes a 4-input / 1-output selector.
A signal is output in the following relationship by four inputs a ', b', c ', d' and a 2-bit select signal y1y0. When y1y0 = 00, b 'is output. When y1y0 = 01, a' is output. When y1y0 = 10, d 'is output. When y1y0 = 11, c' is output. Accordingly, the output of the pixel correction circuit is as follows. .

When the edge amount in the θ1 direction is the maximum The smoothed output in the θ3 direction When the edge amount in the θ2 direction is the maximum The smoothed output in the θ4 direction When the edge amount in the θ3 direction is the maximum The smoothed output in the θ1 direction The θ4 direction When the edge amount is the maximum, the smoothed output in the θ2 direction [Result of Pixel Correction] FIG. 41 is a diagram showing an example of the image correction result.

When an image having a density pattern as shown in FIG. 41A is subjected to an encoding / decoding process by block encoding, as shown in FIG. In some cases, roughness may appear in 4 × 4 units. Thus, by performing the above-described smoothing process on FIG. 2B, an image with reduced roughness can be obtained as shown in FIG. 2C. For example, FIG.
The pixel indicated by A in FIG. 7A is roughened because it has been decoded to a higher density than the pixel corresponding to A in FIG. In the case of the A pixel in FIG.
Since the edge (density gradient) amount in the θ4 direction shown in (c) is larger than the edge amount in the other directions, the edge is smoothed in the θ2 direction orthogonal to θ4 and corrected to a lower density. Similar corrections are made for the other pixels, and as a whole, the roughness is reduced as shown in FIG.

Since the smoothing process is performed in the direction orthogonal to the density gradient, the sharpness of the character portion is not lost. [Judging Means] FIGS. 42 and 43 are block diagrams showing examples of the structure of the judging circuit 1171 shown in FIGS. 31 and 32.

The determination circuit 1171 of this embodiment is substantially the same as the determination circuit 1409 of the fourth embodiment, and the same components are denoted by the same reference numerals and the detailed description thereof will not be repeated. The judgment circuit 1171 of the present embodiment and the judgment circuit 1409 of the fourth embodiment
The difference between the first and second embodiments is in the width of the address bus of the RAM 1302.
8 bits.

That is, in the fourth embodiment, the RAM 130
The upper three bits of the address bus 2 have the CPU 141
An RGB signal is input to the lower 15 bits of the pattern selection signal SNO from 1 to form a total of 18 bits. On the other hand, in the present embodiment, the RAM 13
The address bus 02 is configured to receive 15 bits of RGB signals.

[Timing Chart of Judging Means] The main scanning timing chart in the judging means of this embodiment is the same as the timing chart example shown in FIG. 20 of the fourth embodiment, and a detailed description thereof will be omitted. [Integrator] The integrator 1306 of this embodiment is the same as the configuration example of the integrator shown in FIG. 21 of the fourth embodiment, and a detailed description thereof will be omitted.

A binarized determination signal H is input to the CPU 1170 shown in FIGS. When it is determined that a specific document image is present in the input image, the determination signal H becomes "1", but the CPU 1170 receives this and performs a copy prohibition process. If it is determined that the specific document image does not exist in the input image, the determination signal H remains “0”, and the CPU 1170 receives this signal,
Take measures to allow copying.

[Flowchart] FIG. 45 is an example of a flowchart showing the procedure of the processing in this embodiment. First, in step 1801, a document image is read and an image memory 1116 is read.
Accumulates the image read. Next, step 1802
Then, the specific original image determination is performed on the input image in the image memory 1116.

Next, in step 1803, when it is determined that the specific original image exists in the input image, step 1
In step 804, the CPU 1170 deletes the input image data stored in the image memory 1116 to prevent the read image from being output. If it is determined that the specific original image does not exist in the input image, the process proceeds to step 1805.

Next, in step 1805, the image memory 1
The input image data in 116 is read, and the image is copied and output. At this time, when it is determined that the specific original image does not exist in the input image, normal copy output is performed. When it is determined that the specific original image exists, the image memory 1116 has already been output.
Since the input image data in the image has been erased, the entire white or black image is copied and output.

In the above description, if a specific original image exists in the input image, the CPU 1170 deletes the input image data in the image memory 1116 to prohibit copy output. The present invention is not limited to this. If it is determined that a specific document image is present, the CPU 1170 processes the input image data in the image memory 1116 and, for example, copies and outputs an image different in color from the document image. By doing so, forgery can be prevented.

Further, when copying the specific original 1901 shown in FIG. 46 and determining that the specific original image exists in the input image, the CPU 1170 processes the input image data in the image memory 1116, For example, as shown in FIG. 46, a similar effect can be obtained by forming a copy output in which the character “INVALID” (invalid) is overlaid on the entire surface of the copy output 1902.

Similarly, for example, as shown in FIG. 47, on the entire surface of the copy output 1903, a symbol or number (FIG.
In the case of 7, for example, "123") is overlaid and copied and output. Specifically, a number unique to the apparatus or a manufacturing lot number of the apparatus is periodically and repeatedly output on the entire copy output. Thus, if the copied output is abused, the information of the copying apparatus that has output the copied output can be obtained as a clue for the search by checking the overlapped symbol or number.

By setting the cycle Lx and Ly of the repeated output, such as a superimposed symbol or number, smaller than either the vertical or horizontal width of the specific document to be processed, the corresponding portion of the specific document can be copied from the copy output. Even if a cut-out is abused, it is possible to reliably add a superimposed symbol or number to the cut-out portion of the copy output. As described above, according to this embodiment, in an image processing apparatus that temporarily stores an input image in a memory and then outputs the image, it is determined whether or not a specific document image exists in the input image, and it is determined that the specific document image exists. In this case, forgery of a specific document can be prevented by processing the image data stored in the memory.

The present invention may be applied to a system composed of a plurality of devices or to an apparatus composed of one device. Needless to say, the present invention can be applied to a case where the present invention is achieved by supplying a program to a system or an apparatus.

[0151]

As described above, according to the present invention,
Counterfeiting can be effectively prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of an embodiment according to the present invention.

FIG. 2 is a block diagram illustrating a detailed configuration example of a conversion circuit according to the present embodiment.

FIG. 3 is a diagram illustrating an example of a relationship between various color spaces and a common color space according to the present embodiment.

FIG. 4 is a block diagram showing a detailed configuration example of a specific document identification circuit according to the embodiment;

FIG. 5 is a diagram illustrating an example of a relationship between a specific document image and a color space.

FIG. 6 is a diagram illustrating an example of a relationship between color space data of a specific document image according to the present embodiment and data in a determination ROM.

FIG. 7 is a diagram illustrating an example of a state of integration of the integrator according to the embodiment.

FIG. 8 is a block diagram showing a detailed configuration example of the integrator of the present embodiment.

FIG. 9 is a diagram illustrating an example of a positional relationship between a specific document and a recognition area according to the embodiment;

FIG. 10 is a block diagram showing a detailed configuration example of an OR write circuit and an SRAM of the present embodiment.

FIG. 11 is an example of a timing chart of the timing generation circuit of the present embodiment.

FIG. 12 is a diagram illustrating an example of comparison and determination of a specific document image according to the present embodiment.

FIG. 13 is a flowchart illustrating an operation example of a CPU according to the present embodiment.

FIG. 14 is a block diagram showing a configuration example of a second embodiment according to the present invention.

FIG. 15 is an example of an external view of an apparatus according to a fourth embodiment of the present invention.

FIG. 16 is a block diagram illustrating an example of a signal flow of an image scanner according to the present embodiment.

FIG.

FIG. 18 is a block diagram illustrating a configuration example of a determination circuit according to the present embodiment.

FIG. 19 is a block diagram illustrating a configuration example of a thinning circuit and a frequency dividing circuit according to the present embodiment.

FIG. 20 is an example of a main scanning timing chart in the normal control mode of the present embodiment.

FIG. 21 is a block diagram illustrating a configuration example of an integrator of the present embodiment.

FIG. 22 is a diagram illustrating an example of a relationship between input and output of the integrator according to the present embodiment.

FIG. 23 is a flowchart illustrating an example of a processing flow according to the present embodiment.

FIG. 24 is a diagram showing an example of a processing flow of the fifth embodiment according to the present invention.

FIG. 25 is an example of an outline view of an apparatus according to a sixth embodiment of the present invention.

FIG. 26,

FIG. 27 is a block diagram illustrating an example of a signal flow according to the present embodiment.

FIG. 28 is a flowchart illustrating an example of a processing flow according to the present embodiment.

FIG. 29 is an example of an image forming timing chart according to the seventh embodiment of the present invention.

FIG. 30 is a block diagram showing a configuration example of a circuit for generating a timing signal according to the present embodiment.

FIG.

FIG. 32 is a block diagram illustrating an example of a signal flow according to the present embodiment.

FIG. 33 is a block diagram showing a configuration example of a 4 × 4 area processing circuit of the present embodiment.

FIG. 34 is a schematic diagram of a 4 × 4 area according to the present embodiment.

FIG. 35 is a diagram illustrating an example of an area process according to the embodiment;

FIG. 36 is a block diagram illustrating a configuration example of a color space converter according to the present embodiment.

FIG. 37 is a block diagram illustrating a configuration example of a spatial filter according to the present embodiment.

FIG. 38 is a block diagram illustrating a configuration example of a pixel correction circuit according to the present embodiment.

FIG. 39 is a diagram illustrating an operation example of the pixel configuration circuit according to the present embodiment.

FIG. 40 is a block diagram illustrating a configuration example of a maximum value detection circuit according to the present embodiment.

FIG. 41 is a diagram illustrating an example of an image correction result according to the present embodiment.

FIG. 42,

FIG. 43 is a block diagram illustrating a configuration example of a determination circuit according to the present embodiment.

FIG. 44 is a block diagram illustrating a configuration example of an encoding circuit according to the present embodiment.

FIG. 45 is an example of a flowchart showing the procedure of processing in this embodiment.

FIG. 46,

FIG. 47 is a diagram illustrating an example of a copy output according to the present embodiment.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Signal processing unit 102 Image processing unit (IPU) 103 Host computer 104 Still video (SV) 105 Video tape recorder (VTR) 106 Operation circuit 107 Conversion circuit 108 Color processing circuit 109 Specific document identification circuit 110 Image output control circuit 112 Image output Device 113 Display unit 122, 123 Scanner a, Scanner b 124 Clear signal 404 Identification signal INH 501 Judgment ROM 511 OR writing circuit 512 SRAM 515 CPU 1112 Color space converter 1113, 1114 Encoder 1115 Feature extraction circuit 1116 Image memory 1141 1144 density signal generator 1157 to 1160 scaling circuit 1161, 1162 decoder 1163 color space converter 1164 determination circuit 1170 CPU 1171 determination circuit 140 ～1405 logarithmic converter 1406 masking / UCR circuit 1407 spatial filter 1408 density conversion circuit 1409 decision circuit 1411 CPU 1412 image memory 2201 Sukiyana 2202 printer 2210 three-line sensor

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Yutaka Udagawa 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Kenichi Ota 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon (72) Inventor Eiji Ota 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Yoichi Takagi 3-30-2, Shimomaruko 3-chome, Ota-ku, Tokyo Canon Inc. (56) References JP-A-1-316783 (JP, A) JP-A-4-294682 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 1 / 387,1 / 40 H04N 1/64

Claims (7)

(57) [Claims] And 1. A storage means for storing input image data, image processing means for processing the input image data, wherein when similarity between the image and the predetermined specific image represented by the input image data is high An image processing apparatus comprising: a control unit for erasing the image data stored in the storage unit. 2. An input device for inputting image data stored in the memory from an input device having a memory; an image processing device for processing the input image data; Output means for outputting, to the input device, an instruction to delete the image data stored in the memory of the input device when the similarity with the specific image is high. . 3. An image reading means for optically reading an original to obtain a full-color input image signal obtained by color separation, and an image output means for printing and outputting the processed image signal. The image processing device according to 1. 4. The image processing apparatus according to claim 3 , wherein said image output means transfers images formed on a plurality of photoconductors to a transfer medium and outputs the images. 5. The image processing apparatus according to claim 1, wherein the input image is stored in the storage unit after being encoded. 6. holds input image data into the memory, when processing the input image data, the similarity between the image and the predetermined specific image represented by the input image data is
An image processing method, wherein the image data stored in the memory is deleted when the value is higher . 7. Image data stored in a memory is input from an input device having a memory, and when processing the input image data, an image represented by the input image data and a predetermined specific image are processed. the degree of similarity is
An image processing method comprising: outputting, to the input device, an instruction to delete the image data stored in a memory of the input device when the value is high .