JP3337047B2 - Pulse divider circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a TDMA (Time
Division Multiple Access:
The present invention relates to a pulse dividing circuit for generating a frame pulse or the like used in a communication device for time division multiple access, etc., and particularly to a pulse dividing circuit which realizes low power consumption by switching a reference frequency signal and has little deterioration in accuracy.

[0002]

2. Description of the Related Art In a TDMA communication system or the like in which communication is performed using time slots divided in time, a frame pulse is used as a time reference for determining a time slot of the own station. The pulse dividing circuit for generating a frame pulse must operate continuously during communication and accurately maintain its own frame timing. Normally, the frame pulse is obtained by dividing the frequency of a reference signal having a frequency equal to or higher than the bit rate in order to ensure the resolution of 1-bit accuracy.

On the other hand, for example, PHS (Personal Handy phon) specified in RCR-STD28
In the case where reception is performed at a period much longer than the frame period at the time of waiting for an incoming call as in the e System) method, the standby section generates a frame pulse using a reference signal having a frequency lower than the bit rate, and The average power consumption of the frequency dividing circuit and the oscillating circuit can be reduced by the reference frequency switching type pulse frequency dividing circuit that generates a high-resolution frame pulse only in the section.

FIG. 4 is a block diagram showing an embodiment of a conventional reference frequency switching type pulse dividing circuit. Here, 19.2 MHz is used as the first reference frequency, 32.768 kHz is used as the second reference frequency, and a frame pulse having a period of 5 ms (200 Hz) is obtained as an output. When the logic of the reference frequency switching signal a is “L” (low), 19.2 MHz is used as the reference frequency,
In the case of H "(high), 32.768 kHz is used as the reference frequency.

The reference frequency switching signal a is input to the latch circuit 1 and becomes an internal switching signal b synchronized with the frame pulse. The 19.2 MHz reference signal c is a 50-digit counter 11
, The frequency is divided by 1920 by the 1920-decimal counter 12, and the first frequency-divided pulse p of 200 Hz
1 is obtained. The reference signal d of 32.768 kHz is 16
Divided by 164 by the quaternary counter 26, 199.8H
A second frequency-divided pulse p2 of z is obtained. Internal switching signal b
Is "L", the selector 2 outputs the first frequency-divided pulse p1 as the frame pulse pf, and the hex counter 26 of the second frequency-divider circuit 20 stops its operation. , And the count value is initialized to 0.
On the other hand, when the logic of the internal switching signal b is “H”, the selector 2 generates the second frequency-divided pulse p2 by the frame pulse pf
Is output, and the first frequency dividing circuit 10 including the 50-decimal counter 11 and the 1920-decimal counter 12 stops operating, and the 1920-decimal counter 12 is initialized to a count value of 0. With the above-described configuration, the 19.2 MHz oscillation circuit and the first frequency-dividing circuit 10 with large power consumption can be operated only when necessary, so that low power consumption is achieved.

[0006]

However, the circuit shown in FIG. 4 has a second reference frequency of 32.768 k.
Hz is not an integral multiple of 200 Hz, which is the desired output frequency.
z cannot be obtained. For this reason, as shown in FIG. 5, the error of the second frequency-divided pulse p2 from the original pulse position gradually increases, and accurate frame synchronization cannot be maintained in the long term (however, in FIG. 5, The error is greatly emphasized). If the second reference frequency is selected so as to be an integral multiple of the desired output frequency, the above-mentioned problem does not occur, but an oscillator having such a frequency is not always on the market as a general-purpose product. From the viewpoint of cost reduction of the apparatus, it is desirable to use an inexpensive general-purpose product as the second reference frequency source, but in the conventional circuit shown in FIG. 4, it is necessary to sacrifice the pulse time accuracy. . SUMMARY OF THE INVENTION It is an object of the present invention to solve these problems and to provide a pulse frequency dividing circuit which is highly accurate, has excellent flexibility in selecting a reference frequency, and has low power consumption.

[0007]

According to the first aspect of the present invention,
A first reference frequency signal having a frequency of F1 [Hz];
<F1, and a second reference frequency signal of a frequency F2 [Hz] that is F2Ｆ (F1 / N) × i (N and i are integers) is input, and a frequency-divided pulse of a frequency F1 / N [Hz] is input. A pulse divider circuit for holding a switching signal input from the outside in synchronization with the frequency-divided pulse; and dividing the first reference frequency signal by N to generate a first frequency-divided pulse. And a first pulse dividing circuit constituted by an N-ary counter which outputs the second reference frequency signal as M [M is F2 / (F1 / N) <M <F2 / ｛(F1
/ N) +1}, an M-ary counter that divides the second reference frequency signal by L (L = F2 / F3, F3
Is a common divisor of F2 and F1 / N), means for initializing the M-ary counter by an output pulse of the L-ary counter, output pulses of the M-ary counter and outputs of the L-ary counter A second pulse dividing circuit constituted by means for taking a logical sum of the pulses and outputting as a second divided pulse; and outputting a correction value to an N-ary counter in the first pulse dividing circuit. Correction value output means, a switching means for switching between the first frequency-divided pulse and the second frequency-divided pulse according to the output of the latch means, and an output signal of the latch means, When the switching means selects the second frequency-divided pulse, the first stop signal for stopping the first pulse frequency dividing circuit and the output signal of the latch means allow the switching means to perform First A second stop signal for stopping said second pulse dividing circuit of if you select the peripheral pulses,
When the switching means switches from the second frequency-divided pulse side to the first frequency-divided pulse side according to the output signal of the latch means, an N-ary counter in the first pulse frequency dividing circuit is controlled by the correction value. When the switching means switches from the first frequency-divided pulse side to the second frequency-divided pulse side according to a first initialization signal to be initialized and an output signal of the latch means, the second pulse frequency division is performed. Control means for outputting a second initialization signal for initializing all counters in the circuit.

According to a second aspect of the present invention, in the pulse frequency dividing circuit of the first aspect, the correction value output means is configured to output the correction value to the M-ary during a period in which the second pulse frequency dividing circuit is selected. It is characterized by comprising a K-ary counter {K = (F1 / N) / F3} for counting the number of output pulses of the counter, and arithmetic means for multiplying the count result of the K-ary counter by an integer.

According to a third aspect of the present invention, in the pulse frequency dividing circuit of the first aspect, the first reference frequency signal operates simultaneously with the first pulse frequency dividing circuit.
Divided by a binary counter (J is an integer) and input to the first pulse divider circuit, and the first pulse divider circuit has an N / J binary counter instead of the N-ary counter. Features.

[0010]

According to the first aspect of the invention, even if the value of the second reference frequency is arbitrarily selected, the output pulse closest to the desired frequency (F1 / N) on the lower frequency side can be obtained from the M-ary counter. As a result, an output pulse having a frequency that is exactly a fraction of the desired frequency can be obtained from the L-ary counter. Therefore, as shown in FIG. 2, if the M-ary counter is periodically initialized by the output pulse of the L-ary counter, the output of the M-ary counter and L
The logical sum of the outputs of the binary counter is always a pulse having a frequency near the desired frequency and, on average, equal to the desired frequency. If this pulse is the output of the second pulse divider,
There is no problem that the time accuracy of the second frequency-divided pulse is deteriorated in a long term. Further, a periodic error occurs in the second divided pulse cycle. In order to correct this error, a correction value output means is provided. That is, the correction value output means corrects the N-ary counter of the first pulse divider with the correction value when switching from the second pulse divider to the first pulse divider. Thus, no error propagates to the first pulse divider.

The second aspect of the present invention utilizes the fact that an error generated in the second frequency-divided pulse is proportional to the number of output pulses from the M-ary counter, and calculates the correction value to the first pulse frequency-divided circuit. A means is provided for autonomously generating the signal within the second pulse divider circuit. Therefore, there is no need to input a correction value from the outside, and the interface with a control device or the like for controlling the pulse frequency dividing circuit according to the present invention is simplified.

According to the third aspect of the present invention, by providing the J frequency divider preceding the first pulse frequency divider, the frequency division ratio of the first pulse frequency divider is reduced and the circuit is simplified. At the same time, it is possible to respond to a high-speed reference frequency signal.

[0013]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this embodiment, the first reference frequency is 19.2 MHz, and the second reference frequency is 32.
Using 768kHz, 5ms period (200Hz) for output
Is obtained to obtain the frame pulse pf of the above. 19.2 MH when the logic of the reference frequency switching signal a is “L”
z is used as a reference frequency, and 3 when “H”
2.768 kHz is used as the reference frequency. The reference frequency switching signal a is input to the latch circuit 1 and becomes an internal switching signal b synchronized with the frame pulse pf. The 19.2 MHz reference signal c is a 50-digit counter 11
The first frequency-divided pulse of 200 Hz is obtained by dividing the frequency by 50 with the J-ary counter (corresponding to claim 3) and then dividing the frequency by 1920 with the 1920-decimal counter 12 (corresponding to N / J counter of claim 3). p1 is obtained.

The reference signal d of 32.768 kHz is 164.
It is input to clock terminals of a binary counter 21 (corresponding to the M-ary counter of claim 1) and a 4096-ary counter 22 (corresponding to the L-ary counter of claim 1). The frequency-divided pulse p4 from the 4096-base counter 22 is input to the reset terminal of the 1664-base counter 21 to initialize the 1664-base counter 21 to 0, and to one input terminal of the OR circuit 23. The other input terminal of the OR circuit 23 has 16
The frequency-divided pulse p3 from the quaternary counter 21 is input.

The output of the OR circuit 23 is input to the selector 2 as a second frequency-divided pulse p2, and the clock of the 25-ary counter 24 (corresponding to the K-ary counter of claim 2) in the correction value output circuit 30. Input to terminal. The count output of the 25-ary counter 24 is converted into 2
After being doubled, the 1920-decimal counter 12 is used as the correction value i.
Output to

In such a configuration, the internal switching signal b
Is "L", the first frequency dividing circuit 10 composed of the 50-digit counter 11 and the 1920 decimal counter 12 operates, and the selector 2 selects the first frequency-divided pulse p.
1 is selected and output as the frame pulse pf.
At this time, the hex base counter 21 and the 4096 base counter 2
The second frequency dividing circuit 20 composed of the binary 25-bit counter 24 and the OR circuit 23 stops its operation by the second stop signal g output from the control circuit 40, and stops each counter by the second initialization signal h. The count values of 21, 22, 24 are initialized to zero.

On the other hand, when the logic of the internal switching signal b is "H", the second frequency dividing circuit 20 operates, and the second frequency dividing pulse p2 is selected by the selector 2, and is set as the frame pulse pf. Is output. At this time, the first frequency dividing circuit 1
0 stops the operation by the first stop signal e output from the control circuit 40. The logic of the internal switching signal b is "
In the case of "H", the frequency of the output pulse p3 of the 1664-base counter 21 is 199.8048 Hz, which is slightly lower than the desired frequency of 200 Hz. On the other hand, the frequency of the output pulse p4 of the 4096-base counter 22 is Is 8 Hz, which is synchronized with the desired frequency of 200 Hz. Since the hexadecimal counter 21 is reset by the pulse p4 synchronized with the desired frequency, when the error (period error) of the pulse p3 with respect to the desired frequency signal becomes a constant value. The error is forcibly set to 0 (see times t1 to t3 in FIG. 2), and the pulse p3 for the desired frequency signal is output.
Does not exceed a certain value.

Here, 4096/164 = 24.98. That is, the hexadecimal counter 21 outputs the pulse p3
Is output for 24 pulses, and is reset immediately before outputting the next 25th pulse. That is, in this circuit, the integration error is cleared when the error of the pulse p3 with respect to the desired frequency signal is integrated by 24 pulses, so that the pulse p3 output from the second frequency dividing circuit 20
The error 2 does not exceed the integration error for 24 pulses.

Next, the 25-ary counter 24 outputs the pulse p2
Is obtained, a value corresponding to the integrated error included in the pulse p2 is obtained. That is, immediately after switching from the first frequency dividing circuit 10 to the second frequency dividing circuit 20, the counters 21, 22, and 24 are all cleared, and thereafter, the 1664-base counter counts up the reference signal d. . Then, for example, when 15 pulses are output from the hexadecimal counter 21, an integration error proportional to 15 pulses is generated in the pulse p2. At this time,
The count value of the 25-ary counter 24 is also 15, which is a value corresponding to the integration error. Then, the counter 21,
The count of 22 advances and the second from the hexadecimal counter 21
When the fourth pulse is output, the count value of the 25-ary counter 24 becomes 24, and then the pulse p4 is output from the 4096-base counter 22 and the 1664-base counter 21
Is reset, the pulse p4 (more precisely, the pulse p4 passed through the OR circuit 23) is counted up by the 25-ary counter 24, and the count value of the counter 24 becomes 0.
Return to At this time, since the integrated error is also cleared to 0, the count value of the 25-ary counter 24 is also a value corresponding to the integrated error. Thereafter, the above operation is repeated periodically, but the count value of the 25-ary counter 24 always corresponds to the integration error.

The 1-bit shift circuit 25 doubles the output of the 25-decimal counter 24 to create a correction value corresponding to the integration error, and outputs it to the preset terminal of the 1920-decimal counter 12. When the logic of the internal switching signal b changes from “H” to “L”, immediately after that, the first initialization signal f is output from the control circuit 40 to the 1920-decimal counter 1.
2 is input. As a result, the 1920 decimal counter 12
Then, the correction value i which is the output of the 1-bit shift circuit 25 is preset, and thereafter, the counter 12 performs the counting operation using the correction value i as an initial value.

The operation of the circuit of FIG. 1 is shown in the timing chart of FIG. In FIG. 3, the logic of the internal switching signal b is "
H ", the first frequency dividing circuit 10 which operates at a low frequency and consumes a large amount of power is stopped, and the second frequency dividing circuit 20 which consumes a small amount of power is stopped.
As a result, a frame pulse pf is generated.

[0022]

As described above, according to the first aspect of the present invention, it is possible to obtain a pulse frequency dividing circuit having high accuracy, excellent freedom in selecting a reference frequency, and low power consumption. According to the second aspect of the present invention, since the correction value to the first pulse frequency dividing circuit is generated autonomously in the second pulse frequency dividing circuit, it is not necessary to input the correction value from outside. This has the advantage of simplifying the interface with a control device for controlling the pulse divider circuit. Further, according to the third aspect of the present invention, since the J frequency divider provided before the first pulse frequency divider is provided, the frequency division ratio of the first pulse frequency divider is reduced, and the circuit becomes This simplifies and has the advantage of being able to handle high-speed reference frequency signals.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a pulse divider according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of a second frequency divider in the embodiment.

FIG. 3 is a timing chart showing the operation of the pulse divider according to the embodiment.

FIG. 4 is a block diagram illustrating a configuration example of a conventional pulse dividing circuit.

FIG. 5 is a timing chart showing the operation of the pulse frequency dividing circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Latch circuit 2 ... Selector 10 ... First frequency dividing circuit 11 ... 50 decimal counter 12 ... 1920 decimal counter 20 ... Second frequency dividing circuit 21 ... 164 decimal counter 22 ... 4096 decimal counter 23 ... OR circuit 24 ... 25-bit counter 25 1-bit shift circuit 26 16-bit counter 30 correction value output circuit 40 control circuit a reference frequency switching signal b internal switching signal c reference signal (19.2 MHz) d reference signal (32 .768 kHz) e: first stop signal f: first initialization signal g: second stop signal h: second initialization signal i: correction value

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 21/40 H04L 7/00

Claims (3)

(57) [Claims] 1. A first reference frequency signal having a frequency of F1 [Hz], F2 <F1, and F2 ≠ (F1 / N) × i
(N and i are integers), a second reference frequency signal of a frequency F2 [Hz] is input, and a frequency F1 / N [Hz]
A pulse dividing circuit that outputs a frequency-divided pulse of: a latch unit that holds a switching signal input from the outside in synchronization with the frequency-divided pulse; A first pulse divider circuit configured by an N-ary counter that outputs a divided pulse of the second reference frequency signal; and dividing the second reference frequency signal by M [M is F2 / (F1
/ N) <M <F2 // (integer satisfying (F1 / N) +1}) and an M-ary counter, and dividing the second reference frequency signal by L (L = F2 / F3, F3 is F2 and F1 / An L-ary counter which is a common divisor of N); means for initializing the M-ary counter with an output pulse of the L-ary counter; A second pulse dividing circuit constituted by means for outputting as a second divided pulse; and a correction value output means for outputting a correction value to an N-ary counter in the first pulse dividing circuit. Switching means for switching between the first frequency-divided pulse and the second frequency-divided pulse according to the output of the latch means; an output signal of the latch means being input; The second frequency-divided pulse When selecting, a first stop signal for stopping the first pulse dividing circuit, and when the switching means selects the first frequency-divided pulse by an output signal of the latch means, A second stop signal for stopping the second pulse dividing circuit, and an output signal of the latch means when the switching means switches from the second divided pulse side to the first divided pulse side. A first initialization signal for initializing an N-ary counter in the first pulse frequency dividing circuit with the correction value; Control means for outputting a second initialization signal for initializing all counters in the second pulse frequency dividing circuit when switching to the second frequency dividing pulse side. Pulse divider circuit. 2. The method according to claim 1, wherein the correction value output means counts the number of output pulses of the M-ary counter during a period in which the second pulse divider is selected.
2. The pulse dividing circuit according to claim 1, wherein said pulse dividing circuit is constituted by (1 / N) / F3} and an arithmetic means for multiplying the count result of said K-ary counter by an integer. 3. The first reference frequency signal is J-divided by a J-ary counter (J is an integer) that operates simultaneously with the first pulse divider, and is input to the first pulse divider. 2. The pulse dividing circuit according to claim 1, wherein the first pulse dividing circuit includes an N / J-ary counter instead of the N-ary counter.