JP3336039B2 - Display device of programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device for a programmable controller.

[0002]

2. Description of the Related Art FIG. 1 shows a system using a programmable controller. A programmable controller (hereinafter abbreviated as PC) 4 comprising a power supply 1, a CPU unit 2, a communication unit 3 and the like has various I / O units 5. Are connected, and the display device 6 is connected by remote I / O using RS485, multi-drop or the like.

A display device 6 is used to display a ladder diagram or the like of a PC. The PC status setting circuit 7 sends an I / O signal to the PC 4 via a slave unit circuit 12.
It returns a fixed status indicating that the shared memory 8 is provided with 16 control points each for / O. The shared memory 8 is a memory for exchanging data with the display CPU 9. The display CPU 9 receives display data from the PC 4 through the shared memory 8 and displays the data on the liquid crystal display 9, (Not shown) Output to PC via shared memory 8
Control such as sending to the 4 side is performed. The memory 11 is a memory for a display operation.

[0004]

By the way, in the display device 6 of the above-described conventional example, the PC 4 is determined to be a unit having a fixed number of I / O control points, so that not only display data transfer but also character inversion and the like are shared. It is necessary to read / write data through the memory 8, and high-speed I / O is preferentially allocated to screen switching and key output which are considered to be always used. Therefore, when character inversion or character overwriting is used and a plurality of display devices 6 are connected to the system, the interval between data reading / writing from the PC 4 to each of the display devices 6 becomes longer, and each of them becomes longer. There has been a problem that the response of the screen display change becomes slow.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to make it possible to vary the number of high-speed I / Os and to perform high-speed and frequent control with minimum I / O.
It is an object of the present invention to provide a display device of a programmable controller which can be realized by the number of control points of / O.

[0006]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a display, a display CPU for controlling the display, and data transfer between the programmable controller and the display CPU. Shared memory for I / O
A status generating circuit for variably setting the number of control points of O to generate a status indicating the set number of I / O control points, means for reading and recognizing the generation status of the status generation circuit and returning the status to the programmable controller;
A memory address conversion circuit for converting an address generated by the status generation circuit into a memory map of the shared memory, wherein a bit area and a key output area for writing control data handled in a bit unit formed in the memory map of the shared memory are defined by I / O, and these area capacities are varied according to the number of I / O control points.

[0007]

According to the structure of the present invention, a bit area and a key output area for writing control data handled in bit units formed in a memory map of a shared memory are allocated to I / Os, and the capacity of these areas is set to the I / O. , Control data such as inversion of characters and overwriting of characters can be assigned to I / O, and I / O
Can be varied according to the memory mapping, so that a high-speed screen change response can be obtained even if a plurality of display devices are connected to the programmable controller.

[0008]

The present invention will be described below with reference to examples. FIG. 1 shows an entire configuration of an embodiment of the present invention. In this embodiment, a status generating circuit 13 and a memory address converting circuit 14 are used instead of the conventional PC status set circuit 7.
Are provided.

[0009] Status generating circuit 13 and the switch SW ₁ for input points to control points of the I / O, by setting the number of outputs switch SW _2, 0 points, 64 points, 128 points, 19
It is composed of a logic circuit and a data bus read / write switching circuit for making the status that each of the control points of 2 points and 256 points is occupied by 4 slots for input and output respectively. The memory address conversion circuit 14 comprises a logic circuit for converting an address generated from the status generation circuit 13 into a memory map shown in FIG.

[0010] Figure 2 shows the configuration of the logic circuit on the input side of the status set circuit 10, the zero point in the switch SW ₁ consisting of rotary switch switches 4 contacts, perform the 64 points selected for each slot, this The multiplexer selection signal is output from the decoding circuit 12 based on the selected value. Here, the status consists of 8 bits as shown in FIG. 3, of which the upper two bits D ₇ and D _7
6 is fixed to, for example, 0 or 1, 3 bits D _{0 to} D ₂ of the lower 6 bits indicate the number of input points, and the remaining 3 bits D _{3 to} D _3
5 indicates the number of output points.

In the above circuit, a switch SW is provided for each slot.
₁ by being adapted to be set in the zero point or 64-point, the slot selection address signal is applied to the decoding circuit 15 in the circuit of the input side shown, switch SW ₁
, A multiplexer selection signal is generated based on the setting contents, and the outputs of the multiplexers 16 _{1 to} 16 ₃ are selected so that the bits D _{0 to} D ₁ are set to “111” or “011” corresponding to the set control points. Has become. The bit D ₃ to D ₅ for bit D ₃ to D ₅ of the output side in the circuit on the input side to illustrate 0 "1" is set to the fixed bit D
₆ "1", is set to "0" fixed bit D _7.

A circuit similar to that shown in FIG. 2 is used on the output side.
But D₀~ D_TwoSet to “111”
Then D_Three~ D_FourSwitch SW_TwoBased on the settings
Then set "1" or "0" by the multiplexer
And fixed bit D₆, D ₇As above "
1 ”and“ 0 ”.
By the operation of the readdress conversion circuit 14, the status set
The address generated from the path 10 causes the shared memory shown in FIG.
It is converted into the memory map of the memory 8.

The memory map of the shared memory 8 shown in FIG.
This will be described below. First of all, the input area IA,
Output area OA and input area IA
System fixing area a₁And the display of the bit
Bit designation for writing control data such as blinking in bit units
Area a_TwoAnd a word area a used for data display or the like _Three
And are divided into On the other hand, the output area OA is fixed to the system
Area a_FourAnd key output area a_FiveAnd are divided into

The blinking of the display and the ON / OFF of the switch
, Etc., and high-speed response is required
Bit designation area a_Two, Key output area a_FiveIs the fixed area a
₁, A_FourAnd the switch SW
₁Or SW_TwoAnd the number of slots can be variably set
Bit designation area a according to the number of points_Two, Key output area A _Five
Will be determined.

The fixed area a ₁ is an area for writing a flag for changing the display mode of the screen (RV), an area for writing the screen No. in hexadecimal notation for switching the screen display (screen No.), and further provided in the apparatus. A light emitting diode lighting control area (LED), a built-in buzzer on / off flag writing area (BZ), a liquid crystal display device 6 backlight on / off flag writing area (BL),
Further, an area for setting a flag for turning on / off the relay output contact (Re), an area for writing a flag for turning on / off the external output (OF), and the like are set. The fixing region a _4, the bit and for turning on the internal relay when turning on the switch provided in the apparatus, an area for such bid to turn on the internal relay when the external input contact is turned on.

When the power is turned on as shown in FIG. 5, a status is generated by the status generating circuit 13.
The status is read and recognized by the slave unit circuit 12 and returned to the PC 4 side.
After the status recognition, the ladder control is started.

[0017]

According to the present invention, a bit area and a key output area for writing control data handled in bit units formed in a memory map of a shared memory are allocated to I / Os, and the capacity of these areas is allocated to the I / O. Since it is variable according to the number of control points, control data such as character inversion and character overwriting can be assigned to the I / O, and the number of I / O control points can be varied according to the memory mapping. Even when a plurality of display devices are connected to the programmable controller with the minimum number of I / O control points, a high-speed screen change response can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of one embodiment of the present invention.

FIG. 2 is a specific circuit diagram of a main part of the status generation circuit according to the first embodiment;

FIG. 3 is an explanatory diagram of a status according to the first embodiment.

FIG. 4 is an explanatory diagram of a memory map of the shared memory according to the first embodiment.

FIG. 5 is a flowchart for explaining the operation of the above.

FIG. 6 is a circuit block diagram of a conventional example.

[Explanation of symbols]

SW ₁ switch for input points SW ₂ switch for output points 4 PC 6 display device 8 shared memory 13 status generation circuit 14 memory address conversion circuit

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor, Isao Kashima 1048, Kazuma, Kadoma, Osaka Pref. Matsushita Electric Works, Ltd. JP, A) JP-A-3-65705 (JP, A) JP-A-60-39163 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G05B 19/04-19/05

Claims (1)

(57) [Claims] An indicator, a CPU for the indicator for controlling the indicator, a programmable controller and a CP for the indicator.
A shared memory for transferring data to and from the U, a status generation circuit for variably setting the number of I / O control points and generating a status indicating the set number of I / O control points, and a status generation circuit Means for reading and recognizing the status and returning it to the programmable controller, and a memory address conversion circuit for converting an address generated by the status generation circuit into a memory map of a shared memory,
A bit area and a key output area for writing control data handled on a bit basis formed in a memory map of the shared memory are allocated to I / Os, and the capacity of these areas is varied according to the number of I / O control points. Characteristic display device of programmable controller.