JP3335296B2 - Board connection structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board connection structure, and more particularly, to a circuit board connection for connecting a circuit board having a microstrip line structure to another circuit board by using bumps or wire bonding. Regarding the structure.

[0002]

2. Description of the Related Art In recent years, in the field of information communication, consumer use in the high frequency range of several GHz or more, which has been conventionally used only for special purposes, has been promoted one after another.
There is a demand for a small, inexpensive, high-performance high-frequency device.
Particularly, in a high-frequency device that transmits and receives radio waves of several tens of GHz or more, the wavelength is as short as several millimeters. It is important to reduce the size.

In order to reduce the size of the high-frequency circuit section, necessary circuits must be formed on one semiconductor chip as much as possible, that is, an MMIC (Monolithic Microwave Integ).
It is an effective measure to make it a rated circuit) and to improve the mounting method of the semiconductor chip.

[0004] With regard to the conversion of circuits to MMICs, the integration of circuits on a semiconductor chip has progressed along with the dramatic development of semiconductor integration technology. The degree of integration is increasing from functional circuits to functional circuit blocks that perform one circuit function of equipment, and further to a plurality of functional circuit blocks.

[0005] Improvements have also been made in the semiconductor chip mounting method as described below.

FIG. 13 shows a conventional method of mounting a semiconductor chip. A semiconductor chip 1 is mounted face up on a substrate 2 and bonding wires 3 are used for electrical connection.
Is used. In this method, when the semiconductor chip 1 is mounted on the substrate 2, the mounting area on the substrate side increases by the amount of the connection portion, and there is a limit to miniaturization. Further, since the bonding wire 3 having a length of about several hundred μm is used for the electrical connection, a parasitic component such as an inductor is added by the connection portion. Affect.

Therefore, in order to further reduce the size and increase the frequency, a method of mounting a semiconductor chip on a substrate using flip-chip connection has been proposed. In the flip-chip connection, as shown in FIG. 14, bumps 4 which are metal projecting electrodes are formed on input / output electrodes (not shown) on the semiconductor chip 1, and such a semiconductor chip 1 is connected as shown in FIG. In this method, the bumps 4 on the input / output electrodes are connected to electrodes (not shown) on the substrate 2 to make electrical connection.

According to the flip-chip connection method, since the substantial mounting area can be as large as the size of the semiconductor chip, this is the method having the smallest mounting area. In addition, since the height of the bump used for the connection portion is about several tens of μm, the physical size of the connection portion can be reduced, and the parasitic capacitance and inductance component, which are problematic in a high frequency region, are dramatically reduced. It has the advantages that it can. Therefore, flip-chip connection is most suitable for a connection portion through which a high-frequency signal of several GHz or more passes. An example in which an amplifier that operates in a high-frequency region of about 20 GHz using this technique has already been reported. (Sakai et al., “New Millimeter-Wave IC Using Flip-Chip Mounting,” IEICE Technical Report, ED94-134, MW94-121, ICD94
-196 (1995-01), p.37).

[0009]

A microstrip line is often used for wiring of a substrate handling a high frequency such as a semiconductor chip.

When flip-chip connection is applied to the connection between a semiconductor chip having a microstrip line and a substrate, as shown in FIGS. 16A to 16D, the ground of the substrate having the microstrip structure is formed using vias. It is a general and efficient method to allow connection to the ground layer of another substrate by drawing out the connection end of the layer to the side of the signal line.

More specifically, signal bumps SB are formed at the ends of the signal lines S1 and S2 of the semiconductor chip 1 and the substrate 2. The back surface ground G1 of the semiconductor chip 1 and the substrate 2
G2 is electrically connected to the ground bump GB on the signal lines S1 and S2 through via holes V1 and V2 of through holes penetrating the semiconductor chip 1 and the substrate 2. At this time, the bump GB needs to be separated from the bump SB by a certain distance so that the ground vias V1 and V2 and the bump GB do not overlap the signal line bump SB. As a result,
As compared with the transmission direction of the signal lines S1 and S2, the locus (ground path) where the ground current flows detours near the connection between the semiconductor chip 1 and the substrate 2, and the locus (signal path) where the signal current flows. The ground path is longer than the ground path.

However, in the high-frequency transmission, if the length of the ground path is longer as described above, there is a problem that the transmission loss due to discontinuity of the transmission line at the connection portion increases, so that the length of the signal path and the length of the ground path are increased. Are desirably equal.

The present invention has been made in consideration of the above circumstances, and has as its object to reduce the size and size of semiconductor components.
An object of the present invention is to provide a connection structure of a substrate that can reduce transmission loss caused by discontinuity of a transmission line of a connection portion without hindering high integration.

[0014]

In order to achieve the above object, a connection structure of a substrate according to the present invention comprises a first substrate having a first signal line and a first ground, and a second signal line. And connecting the first signal line and the second signal line to a second substrate having a multilayer structure having a second ground and having the second signal line and the second ground not on the same plane. A connection structure for connecting the first ground and the second ground via a via provided in the second substrate, the connection structure including a signal line connection portion to be connected to the first ground and the second ground. This is a connection structure of the substrate on which the signal line connection portion and the ground connection portion are arranged such that the length of the locus of the signal current flowing through the structure is close to the length of the locus of the ground current.

The signal line connection section and the ground connection section have bumps for performing flip chip connection.

The first signal line and the second signal line are arranged along a plane substantially perpendicular to the layer direction of the substrate in the vicinity of the substrate connection, and the signal line connection is provided. Has a detour that detours out of the one plane to increase the length of the trajectory of the signal current.

Alternatively, the signal line connection portion and the ground connection portion have wires for performing wire bonding connection.

The first signal line and the first ground layer are formed in a microstrip structure or a coplanar structure.

According to the substrate connection structure of the present invention, in a connection structure in which a substrate having a microstrip line structure and another substrate are connected by using bumps or wires, the signal lines in the connection region are subject to process conditions. Provide a signal line with the shortest distance in the range that satisfies it.By detouring compared to the normal case, the length of the signal path and the ground path approach or match, reducing transmission loss due to discontinuity of the connection transmission line. Is done.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The relationship between the discontinuity of connection and the transmission characteristics of a microstrip line when two substrates are connected to form the connection structure shown in FIG. 16 is as follows. .

When two substrates having the same material and thickness of conductor and dielectric are continuously connected in an ideal state (model A), GaAs having a microstrip line dielectric layer as shown in Table 1 When the semiconductor chip and the alumina substrate are connected (model B), BC using BCB (benzocyclobutene) as shown in Table 1 as a material of the wiring portion
When the semiconductor chip with the B layer is connected to the alumina substrate (model C), S at a frequency of 60 GHz
Parameters S ₁₁ , S ₁₂ , S ₂₁ , S ₂₂ , voltage standing wave ratio VSWR
Calculation of _in , VSWR _out and maximum available power gain (MAG) is as shown in Table 2. The frequency characteristics of the model A in the frequency range of 0 to 70 GHz are as shown in FIG. 1, the model B is as shown in FIG. 2, and the model C is as shown in FIG. In FIGS. 1 to 3, (a) is a Smith diagram relating to reflection characteristics showing S parameters S ₁₁ and S ₂₂ , and (b) is a diagram relating to pass characteristics showing the relationship between frequency, MAG and S parameter S ₂₁ . It is.

[0022]

Table 1 Microstrip GaAs layer Alumina layer BCB layer Dielectric layer of the transmission line −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− 12.9 9.8 3.0 Dielectric thickness (Μm) 100 200 10 Thickness of conductor (μm) 22 2 −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

[Table 2] _{----------------------------------- S 11 S 22 S 21 S} 12 VSWR in VSWR _out MAG [dB] [dB] [dB] [dB] [dB] −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−− −− Model A -40.64 -39.89 -0.08 -0.08 1.02 1.02 -0.08 Model B -12.31 -12.31 -0.28 -0.28 1.64 1.64 0.00 Model C -16.71 -16.71 -16.71 -0.11 -0.11 1.34 1.34 0.00 −−−−−−−−− −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

In an ideal connection such as the model A, the voltage standing wave ratio VSWR is 1, and the S parameter S ₂₁ is 0 dB.
Becomes a and the connection portions as the model B and model C is discontinuous, the voltage standing wave ratio VSWR by the reflection at the connection portion is increased, the greater the absolute value of the transmission loss S _21. The voltage standing wave ratio VSWR is generally desired to be about 2 or less in a functional block or the whole system. Since there are generally several connections between boards in a block, the VSWR of each connection Is desirably sufficiently close to 1. However, in reality, it is difficult to form an ideally continuous connection at the connection portion of the substrate.

Further, in a structure in which a ground layer of a substrate having a microstrip structure is connected to a ground layer of another substrate using vias as shown in FIG. 16, a locus of ground current flowing near a connection portion of the substrate (hereinafter referred to as a locus). , A ground path) is longer than a locus (hereinafter, referred to as a signal path) in which a signal current flows by bypassing the signal path, so that the transmission path becomes discontinuous. That is, there is discontinuity due to the connection form. The discontinuity due to the connection form not only increases the transmission loss due to the connection itself, but also increases the transmission loss at that portion in combination with the discontinuity due to the difference in the material and the like. Therefore, there is a need for a connection structure capable of reducing discontinuity due to the connection structure of the substrate and suppressing an increase in transmission loss.

The present invention proposes a substrate connection structure capable of suppressing transmission loss due to the discontinuity of the inter-substrate connection as described above. In the connection structure of the present invention, a microstrip substrate and another substrate are provided. The board is connected to the board, the ground layers of both boards are connected via a via provided in the board, and the signal line is arranged such that the length of the locus of the signal current flowing through the connected board approaches the length of the locus of the ground current. There is provided a length adjustment unit for adjusting the length.

Hereinafter, the connection structure of the substrate of the present invention will be described in detail with reference to specific embodiments.

FIGS. 4A to 4D show a connection structure according to the first embodiment of the present invention, wherein FIG. 4A is a plan view of the connection structure, and FIG. −B ′ line end view,
(C) is an end view taken along line CC ′ in (a), and (d) is an end view taken along line DD ′ in (a).

In the connection structure of this embodiment, the two substrates 11 and 12 having the microstrip line structure are electrically and mechanically connected via bumps B11 and B12, which are projecting electrodes formed at the ends of the respective substrates to be connected. Are connected to each other and the ends of the substrate are overlapped, and the signal lines S11 and S1 of the substrate are
2 has a structure of bypassing near the bump connection portion without being connected at the shortest distance. That is, the bumps B12 for connecting the signal lines S11 and S12 between the substrates are connected to the signal lines S11 and S12 to be connected.
, Ie, not on a plane including the longitudinal directions L11 and L12 of the signal lines S11 and S12 and perpendicular to the dielectric layer of the substrate, but at a position deviated from the plane. Then, connection is made using the detour lines C11 and C12. On the other hand, vias V11, V12 connecting the ground layers G11, G12 of both substrates and the bump B11 are connected to the signal line S.
11 and S12 are arranged on a plane including the longitudinal axis directions L11 and L12.

In the above configuration, since the ground current is affected by the signal current flowing through the detour lines C11 and C12, the actual ground path is located near the via B11 in the longitudinal axis directions L11 and L12 of the signal lines S11 and S12.
Is slightly deflected to the detour C11, C12 side from the plane including
The degree of deflection varies depending on the frequency of the transmission signal. Therefore, the vias V11, V1 are deflected toward the detours C11, C12.
2 is the length of the detour lines C11 and C12
The position of the bump B12 is set in consideration of the material and thickness of the substrate, the thickness and shape of the signal line, the frequency of the transmission signal, and the like so as to be the closest to the length of the signal path passing through. By connecting the signal lines S11 and S12 using the detour lines C11 and C12 in this manner, the length of the signal path can be made closer to the length of the ground path, and the discontinuity of the connection part of the transmission line can be reduced. Therefore, transmission loss at the connection portion can be reduced. In other words, the detour lines C11 and C12 are:
It has a role to adjust the length of the signal line.

In a normal flip-chip connection using bumps, input / output pads are formed at portions where the substrate is connected, and the bumps are formed on the pads. In the above description of the first embodiment of the connection structure according to the present invention and the description of other embodiments described later, the pad is not described. However, in the present invention, the pad itself is a normal flip chip connection. It may be used similarly or may be omitted as necessary.

In the above-described embodiment, the semiconductor chip is used as the first substrate 11 and the alumina substrate is used as the second substrate 12. However, the present invention is not limited to this configuration. The present invention can be applied to various substrates including a semiconductor substrate such as a Si substrate and a GaAs substrate, an alumina substrate, a resin substrate, and the like.

When a semiconductor chip or a semiconductor substrate is used as a substrate, an active element, a passive element, wiring,
Electrodes and the like are provided. Examples of the active element include a bipolar transistor and a field effect transistor. Examples of the passive element include a resistor, a capacitor, an inductance, a directional coupler, a filter, an impedance converter, and an antenna. For wiring materials, for example,
Au, Al, Cu and other metals, conductive resins and the like can be used. Bumps are used for the electrodes. Further, the signal line S11 of the substrate 11 and the detour line C11,
The angle formed between the signal line S12 and the detour C12 on the substrate 12 can be arbitrarily determined. However, if the angle is set to 45 degrees, the design rule is simplified, the circuit design is easy, and the design time can be shortened.

The substrate connector having the connection structure of the present invention as described above can be manufactured, for example, using a substrate on which electrodes (lands) are formed by the following process. Hereinafter, a process of manufacturing an electrode using a semiconductor chip as a substrate will be described with reference to the drawings.

First, using a GaAs wafer as a wafer, for example, a region other than the input / output pads 14 of the semiconductor chip 13 is protected by a passivation film 15 such as silicon oxide on the surface of the wafer as shown in FIG. A plurality of semiconductor chips 13 are formed, and a titanium film 16 and a copper film 17 are successively laminated by a sputtering method or the like. In addition,
The thickness of these two metal films 16 and 17 is 1 μm in total.
Degree. Here, the copper film 17 functions as a plating cathode, and the titanium film 16 functions as a connection layer for improving the adhesion between the copper film 17 and the passivation film 15 on the wafer. Therefore, the thickness of the titanium film 16 may be small,
A thickness of about 0.1 μm is sufficient.

Here, when silicon oxide is used for the passivation film 15, the adhesion between copper and silicon oxide is low, but the adhesion is improved by providing the titanium film 16 to prevent the copper film 17 from peeling off. Can be. However, since the surface of titanium is easily oxidized, after the titanium film 16 is formed, the upper copper film 1 is continuously formed without breaking vacuum.
7 is preferably formed. By forming the titanium film 16 and the copper film 17 in this manner, the interposition of a natural oxide film can be prevented, and a plated cathode film having high adhesion and low resistance can be obtained.

Next, as shown in FIG. 5B, a thick resist is applied to the surface of the wafer by spin coating, and prebaking is performed to form a plating resist layer 18 having a thickness of about 25 μm. .

After that, by exposure and development, (c) of FIG.
As shown in (1), a resist pattern is formed by forming a hole in the plating resist layer 18 at a position on the input / output pad 14. The wafer on which the resist pattern is formed is set in an electroplating apparatus, and a plated copper layer 19 for a thick electrode is formed.

In performing the electroplating, the copper film 17 formed on the wafer is connected to a cathode of an electroplating apparatus, and a phosphorous copper plate is used as an anode. As the plating solution, for example, an aqueous solution having the following composition can be used.

Copper sulfate pentahydrate 75 g / L sulfuric acid (specific gravity 1.84) 180 g / L hydrochloric acid 0.15 mL / L polyethylene glycol (molecular weight of about 400,000) 80 ppm Thioxanthate-s-propanesulfonic acid 40 ppm

The plating conditions were a liquid temperature of 25 ° C., a current density of 1
By supplying 5 A / dm ² and stirring the plating solution by blowing air, copper ions are sufficiently supplied. The required time until the thickness of the formed plating film reaches about 20 μm is determined in advance, and when the required time has elapsed, the power supply is stopped, and the wafer is taken out of the plating apparatus and sufficiently washed with water.

Next, as shown in FIG. 5D, the plating resist film is entirely removed using acetone, and then the wafer is immersed in an etchant and etched to form a copper film 17 formed by plating. And titanium film 1
The portions other than the upper portion of the input / output pad 14 are removed. In this case, the plated copper layer 19 is also etched at the same time, but since the thickness is sufficiently thicker than the copper film 17 and the titanium film 16,
The copper film 17 and the titanium film 16 around the input / output pad 14 are selectively removed. As an etchant for the copper film 17, for example, a mixed solution containing ammonium persulfide, sulfuric acid and ethanol is used, and as an etchant for the titanium film 16, for example, a mixed solution containing EDTA, ammonia and hydrogen peroxide is used. be able to.

As described above, a thick electrode made of copper having a thickness of about 20 μm can be formed on the input / output pad 7.
Thereafter, the wafer on which the thick electrodes are formed is diced into individual semiconductor chips 13.

The bump B (protruding electrode) for flip chip connection is formed by mounting a solder ball having a height of about 70 μm on the thick electrode 18 of the semiconductor chip 13. The bump B is formed by a plating method that has already been reported (EKYung and I. Turlik, IEEE Rrans.Com).
p., Hyibrids, Manufact.Techono., Vol. 14 No. 3, p. 549 (1
991)) and the like. According to the above-described configuration, the bump B is composed of the titanium film 16 having a thickness of 0.1 μm on the input / output pad 14 and the copper film 1 having a thickness of 10 μm.
7 and solder balls formed thereon. The solder ball is made of a tin / lead alloy (composition ratio: 6/4), which is generally called solder, but can be used as a bonding material including other eutectic solders without being limited to this. Those made of various alloys can be used.

In the above structure, the titanium film 16 is formed on the input / output pad 1 made of aluminum, gold or the like on the semiconductor chip.
4 has an effect of increasing the adhesion between the upper layer 4 and copper, and also acts as a barrier layer for preventing the diffusion of copper from progressing to the input / output pad 14. The copper film 17 improves the wettability of the solder and improves the bonding property of the solder ball.

Next, a joining step of flip-chip connecting the semiconductor chip 13 to the substrate 20 will be described.

First, a relatively high-viscosity flux is applied to the input / output pads 14 ′ on the substrate 20, and then, FIG.
As shown in FIG. 5, the surface on which the bumps B of the semiconductor chip 13 are formed faces downward, and is properly aligned on the substrate 20 by using an image processing technique. The semiconductor chips 13 are overlapped so that the input / output pads 14 'of the substrate 20 correspond to each other. The semiconductor chip 13 is temporarily fixed on the substrate 20 by the viscosity of the flux.

Next, using a reflow furnace in a nitrogen atmosphere,
The semiconductor chip 13 and the substrate 20 are flip-chip connected by melting the solder balls of the bumps B and simultaneously performing all bonding of the electrodes connected by the bumps B.

After the completion of the flip chip connection, the presence or absence of the flux residue, the presence or absence of the inclination of the semiconductor chip 13 and the bonding height, the wettability of the solder and the bonding shape, the semiconductor chip 1
3 is visually inspected for the presence / absence of displacement, the presence / absence of cracks in the semiconductor chip 13, and the like.

After the inspection is completed, as shown in FIG.
In order to improve the moisture resistance of the bump B and improve the connection reliability, the semiconductor chip 13 and the substrate 20 are dispensed with a dispenser.
The gap is sealed with a sealing resin R such as a bisphenol-based epoxy resin. Further, as shown in FIG.
In order to maintain the mechanical strength of the semiconductor component, the entire surface of the substrate 20 can be coated with a sealing resin R ′ or the like.

The connection structure of the present invention can be variously modified and applied. A second embodiment according to the present invention will be described below.

FIGS. 7A to 7D show a connection structure according to a second embodiment of the present invention, FIG. 7A is a plan view of the connection structure, and FIG. −B ′ line end view,
(C) is an end view taken along line CC ′ in (a), and (d) is an end view taken along line DD ′ in (a).

In the connection structure of this embodiment, the substrate 21
22 signal line S21, S22, longitudinal axis direction L21, L2
2 are connection bumps B21 and B2 arranged at a uniform pitch.
The bump B21, which passes through the midpoint of two adjacent two bumps,
It is on a plane perpendicular to the direction in which B22 is arranged. Therefore, not only the bump B22 for connecting the signal lines S21 and S22, but also the via V2 connecting the ground layers G21 and G22.
1, V22 and the bump B21 are also connected to the signal lines S21, S22.
Are arranged at positions deviated from a plane including the longitudinal axis directions L21 and L22.

In the above configuration, a signal current flows between the signal line S21 and the signal line S22 through the bypass C21 and the bump B22. Under the influence of the signal current flowing through the detours C21 and C22, the ground current slightly deflects from the plane including the longitudinal axis directions L21 and L22 toward the detours C21 and C22 to pass through the vias V21 and V22 and the bump B21. Flows to With such a configuration, the length of the signal path and the length of the ground path can be made close to each other, and the discontinuity of the connection part of the transmission line can be reduced, so that the transmission loss at the connection part can be reduced.

By arranging the signal lines and bumps as described above, crosstalk between adjacent signal lines can be reduced. Also, since the design rules are simple, circuit design is easy and the design time can be reduced.

Next, a third embodiment of the present invention will be described.

FIGS. 8A to 8D show a connection structure according to a third embodiment of the present invention, wherein FIG. 8A is a plan view of the connection structure, and FIG. −B ′ line end view,
(C) is an end view taken along line CC ′ in (a), and (d) is an end view taken along line DD ′ in (a).

In the connection structure of this embodiment, one substrate 31 to be connected is a semiconductor chip whose wiring structure is a coplanar line.

In this wiring structure, signal lines S31, S
32 are not co-planar with the longitudinal axis directions L31 and L32,
The axial direction L31 ′ of the ground layer G31 and the longitudinal axis direction L32 of the signal line S32 are on the same plane. The signal current is
A bump B32 and a detour C are connected between the signal lines S31 and S32.
32, and the ground current flows through the ground layer G3.
1 and G32 flow through the bump B31 and the via V32. Also in this case, the ground current slightly deflects and flows toward the bypass C32 due to the influence of the signal current. Also in this configuration, it is possible to make the length of the signal path close to the length of the ground path.

As is apparent from the above description, if at least one of the two substrates to be connected is a microstrip line, the substrates are connected according to the present invention so that the lengths of the signal path and the ground path are substantially equal. Is possible.

FIGS. 9A to 9D show a connection structure according to a fourth embodiment of the present invention, wherein FIG. 9A is a plan view of the connection structure, and FIG. −B ′ line end view,
(C) is an end view taken along line CC ′ in (a), and (d) is an end view taken along line DD ′ in (a).

This embodiment shows a modification of a detour for shortening the lengths of the signal path and the ground path, and connects between the signal lines S41 and S42 by detours C41 and C42 curved in an S-shape. Have been.

In this wiring structure, the signal lines S41 and S41
42, the longitudinal axis directions L41 and L42 are on the same plane,
The signal current flows between the signal lines S41 and S42 through the bump B42.
And flows via the detour lines C41 and C42. The ground current flows between the ground layers G41 and G42 and the bump B41.
And vias V41 and V42. Also in this case, it is possible to make the length of the signal path close to the length of the ground path, and the ground path detour C4
1. Detour lines C41 and C42 in consideration of the deflection to the C42 side
Is appropriately adjusted.

FIGS. 10A to 10D show a connection structure according to a fifth embodiment of the present invention, FIG. 10A is a plan view of the connection structure, and FIG. -B 'line end view, (c) is CC' line end view in (a), (d)
FIG. 3 is an end view taken along line DD ′ in FIG.

This embodiment is an example in which a curved shape is changed to a hairpin shape so that a detour for shortening the length of a signal path and a ground path approaches a bump connecting a ground layer.

In the above configuration, the signal current is supplied to the signal line S
Bump B52 and detour lines C51, C
It flows through 52. The ground current flows between the ground layers G51 and G52 between the bump B51 and the vias V51 and V51.
It flows through 52. In this embodiment, the position where the ground path is away from the signal path is closer to the bump than in the above-described embodiment. That is, the signal transmission direction, that is, the longitudinal axis directions L51, L51 of the signal lines S51, S52.
The length of the range where the ground current is deviated from the plane including 52 becomes shorter. When the length of the range where the ground current warps from the plane including the longitudinal axis directions L51 and L52 becomes sufficiently short with respect to the wavelength at the operating frequency, the ground current is hardly affected by the signal current in the detours C51 and C52, It flows almost without being deflected to the detour lines C51 and C52. Therefore, by taking the shape as in this embodiment,
Since the length of the ground path can be suppressed and the signal path can be lengthened, the matching between the signal path and the ground path becomes easy.

FIGS. 11A to 11C show a connection structure according to a sixth embodiment of the present invention, wherein FIG. 11A is a plan view of the connection structure, and FIG. FIG. 3C is an end view taken along line B ′, and FIG. 3C is an end view taken along line CC ′ in FIG.

This embodiment is an example in which two substrates are connected by bonding wires instead of flip-chip connections. Therefore, the two substrates are connected side by side on the same plane without overlapping the ends.

Specifically, the two substrates 61 and 62 are respectively
The signal lines S61 and S62 are provided on the upper surface, and the ground layer G is provided on the lower surface.
61 and G62, and an electrode E6 is provided on the upper surface of the end of the substrate 61.
1 and E62 are arranged side by side, and an electrode E
63 and E64 are juxtaposed. In order to connect the electrodes E61 and E63 to the ground layers G61 and G63 on the lower surface of the substrate, vias V61 and V62 penetrating the substrates 61 and 62 are formed, and the electrode E61 is connected to the electrode E63 by a bonding wire W61. Signal line S6 of substrate 61
1 is an electrode E6 via an S-shaped detour C61.
2, and is also connected by a bonding wire W62 to an electrode E64 similarly connected to a signal line S62 via a bypass C62.

As described above, even when the connection is made by the bonding wire, the length of the signal path can be made closer to the length of the ground path, and the deflection of the ground path to the detour lines C61 and C62 is taken into consideration. The curved shapes of the detour lines C61 and C46 are appropriately adjusted.

As understood from the above embodiment, in the present invention, the connection means of the substrate is not limited to the bump,
Bonding wire, land grid array (LGA)
And various connection means can be used.

FIGS. 12A to 12C show a connection structure according to a seventh embodiment of the present invention, FIG. 12A is a plan view of the connection structure, and FIG. FIG. 3C is an end view taken along line B ′, and FIG. 3C is an end view taken along line CC ′ in FIG.

This embodiment is an example in which the length of a signal path is adjusted by a bonding wire in connection with a substrate by a bonding wire.

Specifically, the two substrates 71 and 72 are respectively
The signal lines S71 and S72 are provided on the upper surface, and the ground layer G is provided on the lower surface.
71 and G72, and an electrode E7 is provided on the upper surface of the end of the substrate 71.
1 and E72 are provided side by side, and an electrode E
73 and E74 are juxtaposed. Vias V71 and V72 penetrating the substrates 71 and 72 are formed to connect the electrodes E71 and E73 to the ground layers G71 and G73 on the lower surface of the substrate, respectively, and the electrodes E71 and E73 are connected by bonding wires W71. . Signal line S on substrate 71
Reference numeral 71 is directly connected to the electrode E72, and is connected to the electrode E74 by a bonding wire W72 longer than the bonding wire W71, and the electrode E74 is connected to the signal line S72. That is, the lengths of the signal path and the ground path are matched by changing the length of the bonding wire.

This embodiment is characterized in that the signal path and the ground path can be matched at the stage of assembling the substrate. When used in combination with the sixth embodiment, the bonding wires are connected at the stage of assembling the substrate. By adjusting the length, the length of the signal path can be finely adjusted, and the transmission loss can be further reduced.

The present invention is not limited to the above-described embodiment, and can be implemented with various applications and modifications without departing from the spirit of the present invention. For example, the connection structure of the present invention can be applied to a connection between a semiconductor chip and a substrate, a connection between a semiconductor chip and a semiconductor chip, a connection between a substrate and a substrate, or a connection between components for other electronic devices.
Further, the above embodiments may be used in appropriate combination.

[0076]

As described in detail above, according to the substrate connection structure of the present invention, a substrate having a microstrip line structure is connected to another substrate by flip chip connection using bumps, wire bonding connection, or the like. At this time, the lengths of the signal path and the ground path can be made closer and uniform, so that the discontinuity of the transmission line at the connection can be reduced, and the transmission loss at the connection can be reduced.

[Brief description of the drawings]

FIGS. 1A and 1B are diagrams showing frequency characteristics of two substrates continuously connected in an ideal state to the structure of FIG. 16, wherein FIG. 1A is a Smith diagram relating to reflection characteristics, and FIG. M
AG and shows the relationship between the S parameters S _21.

FIG. 2 is a diagram illustrating frequency characteristics of a GaAs semiconductor chip and an alumina substrate connected to the structure of FIG. 16;
(A) shows a Smith diagram for the reflection characteristic shows (b) the relationship between the frequency and the MAG and the S-parameter S _21.

3A and 3B are diagrams showing frequency characteristics of a semiconductor chip and an alumina substrate using BCB connected to the structure of FIG. 16 as a material of a wiring portion, wherein FIG. 3A is a Smith diagram relating to reflection characteristics, and FIG. shows the relationship between the frequency and the MAG and the S-parameter S _21.

4A and 4B are diagrams showing a first embodiment of a substrate connection structure according to the present invention, wherein FIG. 4A is a plan view, and FIG.
B 'line end view, (c) is a CC' line end view in (a), (d) is a DD 'line end view in (a).

FIGS. 5A to 5D are process diagrams for explaining a process of manufacturing an electrode on a semiconductor chip. FIGS.

FIGS. 6A to 6C are process diagrams for explaining a process of flip-chip connecting a semiconductor chip to a substrate; FIGS.

FIGS. 7A and 7B are views showing a second embodiment of the substrate connection structure of the present invention, wherein FIG. 7A is a plan view, and FIG.
B 'line end view, (c) is a CC' line end view in (a), (d) is a DD 'line end view in (a).

FIGS. 8A and 8B are diagrams showing a third embodiment of the substrate connection structure of the present invention, wherein FIG. 8A is a plan view and FIG.
B 'line end view, (c) is a CC' line end view in (a), (d) is a DD 'line end view in (a).

FIGS. 9A and 9B are views showing a fourth embodiment of the substrate connection structure of the present invention, wherein FIG. 9A is a plan view and FIG.
B 'line end view, (c) is a CC' line end view in (a), (d) is a DD 'line end view in (a).

FIGS. 10A and 10B are diagrams showing a fifth embodiment of the substrate connection structure of the present invention, wherein FIG. 10A is a plan view and FIG.
-B 'line end view, (c) is CC' line end view in (a), (d) is DD 'line end view in (a).

11A and 11B are diagrams showing a sixth embodiment of the substrate connection structure of the present invention, wherein FIG. 11A is a plan view, and FIG.
-B 'line end figure, (c) is CC' line end figure in (a).

FIGS. 12A and 12B are views showing a seventh embodiment of the substrate connection structure of the present invention, wherein FIG. 12A is a plan view and FIG.
-B 'line end figure, (c) is CC' line end figure in (a).

FIG. 13 is a side view showing a mounting structure of a conventional semiconductor chip.

FIG. 14 is a perspective view showing a conventional semiconductor chip mounted by flip chip connection.

FIG. 15 is a side view showing a mounting structure in which the semiconductor chip of FIG. 14 is mounted on a substrate.

16A and 16B are diagrams showing a conventional connection structure when a substrate having a microstrip structure is connected to another substrate, wherein FIG. 16A is a plan view, FIG. 16B is an end view along line BB ′ in FIG.
(C) is an end view taken along line CC ′ in (a), and (d) is an end view taken along line DD ′ in (a).

[Explanation of symbols]

Reference Signs List 1 semiconductor chip 2 substrate 3 bonding wire 4 bump S1-2 signal line G1-2 ground layer V1-2 via GB, SB bump 11, 12, 21, 22, 31, 32, 41, 42, 5
1, 52, 61, 62, 71, 72 substrate 13 semiconductor chip 14, 14 'input / output pad (electrode) 15 passivation film 16 titanium film 17 copper film 18 plating resist layer 19 plated copper layer 20 substrate R, R' sealing Resins S11, S12, S21, S22, S31, S32, S
41, S42, S51, S52, S61, S62, S7
1, S72 signal lines G11, G12, G21, G22, G31, G32, G
41, G42, G51, G52, G61, G62, G7
1, G72 Ground layer V11, V12, V21, V22, V32, V41, V
42, V51, V52, V61, V62, V71, V7
2 Vias B11, B12, B21, B22, B31, B32, B
41, B42, B51, B52 Bump E61, E62, E63, E64, E71, E72, E
73, E74 electrode W61, W62, W71, W72 bonding wire

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-4-227101 (JP, A) JP-A-9-148373 (JP, A) JP-A-4-117702 (JP, A) 145112 (JP, A) JP-A-8-213801 (JP, A) JP-A-9-321501 (JP, A) JP-A-63-13401 (JP, A) JP-A-5-46104 (JP, U) 62-129802 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01P 1/04 H01P 3/08 H01P 5/02 603 H05K 1/14 H01L 21/66

Claims (4)

(57) [Claims] A first signal line and a first ground;
The first signal line and the first ground line are on the same plane.
Not a first substrate having a multilayer structure in microstrip, micro second signal line and a second signal line and the second ground and second graph window command is not on the same plane
A second substrate having a multilayer structure with a strip structure, and a van for flip-chip connecting the first signal line and the second signal line;
A signal line connecting portion having flop, is provided on the first substrate
The first via a via and a via provided in the second substrate.
A connection structure of a substrate having a ground connection portion having a bump for flip-chip connection between the ground and the second ground, wherein the signal line connection portion includes the first and second grounds .
There is a detour that bypasses the signal line 2 without connecting it at the shortest distance
And, wherein the length of the trajectory of the signal current flowing through the connection structure is arranged signal line connecting portion and the ground connecting portion to be close to the length of the trajectory of the graph c <br/> command current The connection structure of the substrate. 2. The first signal line and the second signal line in the vicinity of a substrate connecting portion are substantially along a plane perpendicular to a layer direction of the first and second substrates. disposed Te, the bypass line, the substrate according to claim 1, wherein the bypass to Turkey into and out from said one plane in order to increase the length of the trajectory of the signal current flowing through the connection structure Connection structure. 3. The ground connection unit according to claim 1 , wherein:
A round and the second ground on the one plane
3. The connection structure for a substrate according to claim 1 or 2, wherein
Build. 4. A semiconductor device having a first signal line and a first ground.
The first signal line and the first ground line are on the same plane.
A first substrate having a coplanar structure, a second signal line,
A second signal line having a second ground and a second ground;
Multilayer with microstrip structure that is not on the same plane
A second substrate having a structure, the first signal line and the second signal line
Line connection having bumps for flip-chip connection with
And the first through a via provided in the second substrate.
Flip chip connection between the ground and the second ground
Having a ground connection having a continuous bump
Connection structure, wherein the first signal is provided in the vicinity of the substrate connection portion.
Line and the signal line connection portion substantially correspond to the first and second
Arranged along one plane perpendicular to the layer direction of the substrate
And the second signal line is a signal line flowing through the connection structure.
If the length of the flow trajectory is close to the length of the ground current
So that it is not located in the one plane
Characteristic board connection structure.