JP3333330B2 - Semiconductor light emitting device and method of manufacturing the same - Google Patents

Semiconductor light emitting device and method of manufacturing the same

Info

Publication number
JP3333330B2
JP3333330B2 JP23625894A JP23625894A JP3333330B2 JP 3333330 B2 JP3333330 B2 JP 3333330B2 JP 23625894 A JP23625894 A JP 23625894A JP 23625894 A JP23625894 A JP 23625894A JP 3333330 B2 JP3333330 B2 JP 3333330B2
Authority
JP
Japan
Prior art keywords
layer
substrate
light
light emitting
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP23625894A
Other languages
Japanese (ja)
Other versions
JPH08102548A (en
Inventor
真理子 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP23625894A priority Critical patent/JP3333330B2/en
Publication of JPH08102548A publication Critical patent/JPH08102548A/en
Application granted granted Critical
Publication of JP3333330B2 publication Critical patent/JP3333330B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22Roughened surfaces, e.g. at the interface between epitaxial layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は光の取り出し効率の良好
な半導体発光素子及びその製造方法に係る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device having good light extraction efficiency and a method for manufacturing the same.

【0002】[0002]

【従来の技術】InGaAlP系混晶は、窒化物を除き
III ーV属化合物半導体混晶中で最大の直接遷移型エネ
ルギーギャップを有し、波長0.5〜0.6μm帯の発
光素子材料として注目されてきている。特にGaAsを
基板とし、これに格子整合するInGaAlPからなる
発光層を持つpn接合型発光ダイオード(LED)は、
直接遷移型エネルギーギャップを有しており電荷の再結
合が効率よく行われ、いわゆる内部量子効率が高いので
高い発光揮度を期待できる。
2. Description of the Related Art InGaAlP-based mixed crystals excluding nitrides
It has attracted attention as a light emitting element material having a maximum direct transition energy gap in a III-V compound semiconductor mixed crystal and a wavelength band of 0.5 to 0.6 μm. In particular, a pn junction type light emitting diode (LED) having a GaAs substrate and a light emitting layer of InGaAlP lattice-matched to the substrate is
Since it has a direct transition type energy gap, charge recombination is performed efficiently, and the so-called internal quantum efficiency is high, high light emission volatility can be expected.

【0003】しかしながら内部量子効率はその組成によ
り決定されるものであり、実質的にLEDの発光効率を
高めるには、素子内部での光吸収による損失や内部反射
等により外部に取り出されない光の損失分を考慮した外
部量子効率の向上が重要である。
However, the internal quantum efficiency is determined by its composition. To substantially increase the luminous efficiency of an LED, light which is not extracted outside due to loss due to light absorption inside the device or internal reflection, etc. It is important to improve the external quantum efficiency in consideration of the loss.

【0004】図10に発光層にInGaAlPを用いた
従来のLEDの断面図を示す。n型GaAs基板61の
主面上にn型InGaAlPクラッド層62、InGa
AlP活性層63、p型InGaAlPクラッド層64
からなるダブルヘテロ構造部(発光層65)が格子整合
され成長形成されている。この発光層65上にp型Ga
AlAs電流拡散層66が前記基板61及び発光層65
に対して格子整合され成長形成されている。更にこのG
aAlAs電流拡散層66上に電極部として、p型Ga
Asオーミックコンタクト層67、Au−Znからなる
p側電極68が円形状に形成されている。n型GaAs
基板61の裏面にはZn−Geからなるp側電極69が
形成されている。
FIG. 10 is a sectional view of a conventional LED using InGaAlP for a light emitting layer. On the main surface of an n-type GaAs substrate 61, an n-type InGaAlP cladding layer 62, InGa
AlP active layer 63, p-type InGaAlP cladding layer 64
(A light-emitting layer 65) is formed by lattice matching and growing. On this light emitting layer 65, p-type Ga
The AlAs current diffusion layer 66 includes the substrate 61 and the light emitting layer 65.
Are grown and formed with lattice matching. Furthermore, this G
a p-type Ga as an electrode portion on the AlAs current diffusion layer 66
An As ohmic contact layer 67 and a p-side electrode 68 made of Au-Zn are formed in a circular shape. n-type GaAs
On the back surface of the substrate 61, a p-side electrode 69 made of Zn-Ge is formed.

【0005】このようなLEDでは、電流拡散層66は
基板61や発光層65と格子整合して成長形成されてい
るので電流拡散層66と空気との界面70は鏡面状にな
っている。このような鏡面状の界面70では、界面70
での全反射の確率が高く、発光層65で発光された光は
界面70によりほぼ95%反射され外部に光を十分に取
り出すことができないという問題がある。
In such an LED, the interface 70 between the current spreading layer 66 and air has a mirror-like shape because the current spreading layer 66 is grown in lattice matching with the substrate 61 and the light emitting layer 65. In such a mirror-like interface 70, the interface 70
Therefore, there is a problem that the light emitted from the light emitting layer 65 is almost 95% reflected by the interface 70 and the light cannot be sufficiently extracted to the outside.

【0006】この界面における反射を防ぎ、外部に十分
に光を取り出すことを目的として、界面に幾何学的に凹
凸を形成することによって有効に外部に光を取り出すこ
とが提案されている(I.Schnitzer et al,absutract fo
r LEDS 93,pD1(1993) )。
For the purpose of preventing reflection at the interface and sufficiently extracting light to the outside, it has been proposed to effectively extract light to the outside by forming geometrical irregularities on the interface (I. Schnitzer et al, absutract fo
r LEDS 93, pD1 (1993)).

【0007】この文献によると、界面の凹凸化(粗面
化)は微小なビーズ状の粒子をマスクとし異方性ドライ
エッチングを用いて行っており、このようにして得られ
たLEDは従来のものと比べて約3倍の外部量子効率が
得られたことを報告している。
According to this document, the unevenness (roughening) of the interface is performed using anisotropic dry etching using fine bead-shaped particles as a mask, and the LED thus obtained is a conventional LED. It is reported that the external quantum efficiency was about three times as high as that obtained by the method.

【0008】[0008]

【発明が解決しようとする課題】本発明者は上記文献に
基づいて再現実験を行ったところ、微小粒子をマスクと
し異方性ドライエッチングを用いて界面を粗面化する方
法では以下の問題が生じることを見いだした。 (1)異方性ドライエッチングを用いているため、界面
にダメージを与え界面に光を吸収する準位を有する欠陥
を与えることとなり、光吸収による損失が大きくなる問
題。 (2)異方性ドライエッチングを用いているため、素子
に与えるダメージは無視できるものではなく、結果的に
素子の寿命を低下させる問題。 (3)界面の粗面化は数千オングソトロームから数ミク
ロン程度と十分に微細に且つ均一に行わなければならな
いが、微小ビーズをマスクとして用いる方法では、ウェ
ハ表面内でビーズが均一に分散しないため、ウェハ面内
で均一にエッチングすることができないので結果的に素
子を分離したときに素子間で外部量子効率のばらつきが
生ずる問題。 (4)LEDを構成する材料によってはプロセスが困難
であり、実際ZnGaAlP系LEDでは外部量子効率
の向上は得られなかった。
The present inventor conducted a reproduction experiment based on the above-mentioned literature. As a result, the following problems were encountered in the method of roughening the interface using anisotropic dry etching using fine particles as a mask. I found what would happen. (1) Since anisotropic dry etching is used, the interface is damaged and a defect having a level that absorbs light is given to the interface, resulting in a large loss due to light absorption. (2) Since anisotropic dry etching is used, damage to the device is not negligible, and consequently reduces the life of the device. (3) Roughening of the interface must be performed sufficiently finely and uniformly from several thousand angstroms to several microns, but in the method using fine beads as a mask, the beads are uniformly dispersed within the wafer surface. As a result, uniform etching cannot be performed in the wafer surface, and consequently, when the devices are separated, the external quantum efficiency varies between the devices. (4) The process is difficult depending on the material constituting the LED, and in fact, the improvement of the external quantum efficiency was not obtained in the ZnGaAlP-based LED.

【0009】そこで本発明は上記問題点に鑑みて成され
たものであり、素子にダメージを与えることがなく、界
面における光の吸収による損失を防ぎ高い量子効率を有
する半導体発光素子を提供することを目的とする。
The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a semiconductor light emitting device having high quantum efficiency without damaging the device, preventing loss due to light absorption at an interface. With the goal.

【0010】本発明の別の目的は素子の寿命を向上させ
信頼性の高い半導体発光素子を提供するところにある。
また、本発明の別の目的は高いスループットを有し、素
子間で外部量子効率のばらつきのない半導体発光素子を
提供するところにある。更に本発明の別の目的は、エッ
チング等の余分な工程がなく極めて容易に、界面を粗面
化し得る半導体発光素子の製造方法を提供するところに
ある。
Another object of the present invention is to provide a highly reliable semiconductor light emitting device by improving the life of the device.
Another object of the present invention is to provide a semiconductor light emitting device having high throughput and having no variation in external quantum efficiency between devices. Still another object of the present invention is to provide a method for manufacturing a semiconductor light emitting device capable of extremely easily roughening an interface without an extra step such as etching.

【0011】[0011]

【課題を解決するための手段】本発明者は、下地の基板
に対してプラスに格子不整合するように半導体を成長形
成すると、ある膜厚で表面に面内で均一な凹凸(粗面)
を生じる現象を見いだした。このような凹凸はいわゆる
ハッチが生じたり、部分的に多結晶化するものではな
く、結晶性を保ったまま幾何学的に凹凸が生じる現象で
ある。
The inventor of the present invention has found that when a semiconductor is grown and formed so as to be lattice-mismatched with the underlying substrate, uniform in-plane irregularities (rough surfaces) are formed at a certain film thickness.
Was found. Such irregularities do not cause so-called hatching or partially polycrystallize, but are phenomena in which geometrical irregularities occur while maintaining crystallinity.

【0012】本発明はこのような格子不整合による結晶
歪によって生じた幾何学的な凹凸面を持つ半導体層(表
面が粗面化された半導体層)を半導体発光素子の光散乱
層として用いることによって成し得たものである。
According to the present invention, a semiconductor layer having a geometrically uneven surface (a semiconductor layer having a roughened surface) caused by crystal distortion caused by such lattice mismatch is used as a light scattering layer of a semiconductor light emitting device. Can be achieved by

【0013】そこで本発明による半導体発光素子は、基
板と、この基板上に形成された半導体からなる発光層
と、この発光層上に形成され前記発光層を構成する半導
体に対してプラスに格子不整合した半導体からなり、表
面が格子歪により粗面化されている光散乱層とを具備す
ることを特徴とするものである。
Therefore, the semiconductor light-emitting device according to the present invention has a structure in which a substrate, a light-emitting layer made of a semiconductor formed on the substrate, and a semiconductor formed on the light-emitting layer and constituting the light-emitting layer are not lattice-positive. A light scattering layer made of a matched semiconductor and having a surface roughened by lattice distortion.

【0014】また基板として半導体基板を用い、光散乱
層はこの基板に対してプラスに格子不整合していること
を特徴とするものである。また本発明による半導体発光
素子の製造方法は、基板上に半導体材料からなる発光層
を成長形成する工程と、この発光層上に前記発光層或い
は前記基板に対してプラスに格子不整合させるように半
導体層を成長させ表面を粗面化させることによって光散
乱層を形成する工程とを具備することを特徴とするもの
である。
Further, the present invention is characterized in that a semiconductor substrate is used as a substrate, and the light scattering layer is lattice-mismatched to this substrate in a positive manner. Further, the method for manufacturing a semiconductor light emitting device according to the present invention includes a step of growing a light emitting layer made of a semiconductor material on a substrate and a step of forming a positive lattice mismatch with the light emitting layer or the substrate on the light emitting layer. Forming a light scattering layer by growing a semiconductor layer and roughening the surface.

【0015】光散乱層の膜厚は0.05μm以上であ
り、光散乱膜の格子不整合率は0.1%以上2.5%以
下であれば、その表面は良好に粗面化され光取り出し効
率の高い半導体発光素子を提供することができる。
If the light-scattering layer has a thickness of 0.05 μm or more and the lattice mismatch rate of the light-scattering film is 0.1% or more and 2.5% or less, the surface is satisfactorily roughened. A semiconductor light emitting element with high extraction efficiency can be provided.

【0016】その膜厚は0.05μm以上10μm以下
であることが十分に光を散乱させること、成長方向に組
成の均一性を得ることの点で好ましい。光散乱層はIn
GaAlP系からなることがGaAsに格子整合するほ
とんどのIII −V族系LEDにたいして透明であるこ
と、比較的容易に屈折率やバンドギャップを格子定数を
変えずに制御できること等の点で好ましい。基板として
はGaAsやInP、GaAlAs等種々選択して用い
ることができる。
The thickness is preferably 0.05 μm or more and 10 μm or less from the viewpoints of sufficiently scattering light and obtaining uniformity of composition in the growth direction. The light scattering layer is In
It is preferable to use a GaAlP-based material in that it is transparent to most III-V-based LEDs lattice-matched to GaAs, and that the refractive index and band gap can be controlled relatively easily without changing the lattice constant. Various substrates such as GaAs, InP, and GaAlAs can be selected and used as the substrate.

【0017】[0017]

【作用】本発明によると、光散乱層の表面を格子不整合
による結晶歪によって粗面化しているので、結晶性を保
ったままその表面に幾何学状の凹凸を形成することが可
能となり、光吸収による外部量子効率の低下を防ぐこと
が可能となる。また、ドライエッチングのようなエッチ
ング工程を不要としているので素子の信頼性の向上を図
ることができる。更に通常の気相成長法のみで製造でき
るので、エッチング等の余分な工程も必要とせず高い歩
留まりを期待できる。
According to the present invention, since the surface of the light scattering layer is roughened by crystal distortion due to lattice mismatch, it is possible to form geometric irregularities on the surface while maintaining the crystallinity. It is possible to prevent a decrease in external quantum efficiency due to light absorption. Further, since an etching step such as dry etching is not required, the reliability of the element can be improved. Further, since it can be manufactured only by a normal vapor phase growth method, a high yield can be expected without an extra step such as etching.

【0018】[0018]

【実施例】以下に図面を参照して本発明の実施例を詳細
に説明する。 (実施例1)図1は本発明の第1の実施例に係る半導体
発光素子の概略構成を示す断面図である。
Embodiments of the present invention will be described below in detail with reference to the drawings. (Embodiment 1) FIG. 1 is a sectional view showing a schematic structure of a semiconductor light emitting device according to a first embodiment of the present invention.

【0019】n型GaAs基板10の主面上に、n型I
0.5 (Ga1-x Alx0.5 Pクラッド層11、アン
ドープIn0.5 (Ga1-y Aly0.5 P活性層12、
p型In0.5 (Ga1-z Alz0.5 Pクラッド層13
からなるダブルヘテロ構造の発光層14が格子整合され
成長形成されている。ダブルヘテロ構造は高い発光効率
が得られるようにy≦x,y≦zとなるように設定す
る。すなわちバンドギャップの大きさが活性層12≦ク
ラッド層11、活性層12≦クラッド層13となるよう
にx,y,zを決定すれば良い。
An n-type GaAs substrate 10 has an n-type I
n 0.5 (Ga 1-x Al x ) 0.5 P cladding layer 11, undoped In 0.5 (Ga 1-y Al y ) 0.5 P active layer 12,
p-type In 0.5 (Ga 1 -z Al z ) 0.5 P cladding layer 13
The light-emitting layer 14 having a double hetero structure is formed by lattice matching and growing. The double hetero structure is set so that y ≦ x and y ≦ z so as to obtain high luminous efficiency. That is, x, y, and z may be determined so that the size of the band gap satisfies the relationship of the active layer 12 ≦ the cladding layer 11 and the active layer 12 ≦ the cladding layer 13.

【0020】この発光層14上にp型Ga1-t Alt
s電流拡散層15が成長形成されている。このとき電流
拡散層15のAl組成tは発光波長に対して透明である
ように設定する。
On this light emitting layer 14, p-type Ga 1-t Al t A
The s current diffusion layer 15 is grown and formed. At this time, the Al composition t of the current diffusion layer 15 is set so as to be transparent to the emission wavelength.

【0021】この電流拡散層15上に表面が粗面化され
たp型In0.5+s Al0.5-s P光散乱層16が成長形成
されている。このとき光散乱層16の混晶比sは、その
表面17が粗面となるようにGaAs基板10及び発光
層14に対して格子不整合率が+0.1%以上+2.5
%以下に設定され、好ましくはs=0.005(0.5
%)に設定されている。
On the current diffusion layer 15, a p-type In 0.5 + s Al 0.5-s P light scattering layer 16 having a roughened surface is formed by growth. At this time, the mixed crystal ratio s of the light scattering layer 16 is such that the lattice mismatch ratio with respect to the GaAs substrate 10 and the light emitting layer 14 is + 0.1% or more +2.5 so that the surface 17 is rough.
%, Preferably s = 0.005 (0.5
%).

【0022】この光散乱層16上には電極部となるp型
GaAsコンタクト層18、Au−Znからなるp側電
極19が円形状に形成されている。GaAs基板10の
裏面にはAu−Geからなるn側電極20が形成されて
いる。
On the light scattering layer 16, a p-type GaAs contact layer 18 serving as an electrode portion and a p-side electrode 19 made of Au-Zn are formed in a circular shape. On the back surface of the GaAs substrate 10, an n-side electrode 20 made of Au-Ge is formed.

【0023】次に、この半導体発光素子の製造方法を図
2から図6を参照して説明する。以下に説明する半導体
発光素子においては、x=1,y=0.5,z=1,s
=0.005,t=0.8となるように各ガスの流量や
成長温度を制御して成長形成した。III 族原料に有機金
属(トリメチルガリウム、トリメチルインジウム、トリ
メチルアルミニウム)を用い、V族原料にアルシン、ホ
スフィンを用いた。このときの成長温度は730℃、V
/III 比は450とした。
Next, a method for manufacturing the semiconductor light emitting device will be described with reference to FIGS. In the semiconductor light emitting device described below, x = 1, y = 0.5, z = 1, s
= 0.005 and t = 0.8 by controlling the flow rate of each gas and the growth temperature. Organic metals (trimethylgallium, trimethylindium, trimethylaluminum) were used as group III raw materials, and arsine and phosphine were used as group V raw materials. The growth temperature at this time is 730 ° C., V
The / III ratio was 450.

【0024】先ず図2に示すようにn型GaAs基板1
0上にn型InGaAlPクラッド層11、InGaA
lP活性層12、p型GaAlPクラッド層13、p型
GaAlAs電流拡散層15、p型InAlP光散乱層
16、p型GaAsコンタクト層18をMOCVD法に
より順次形成する。このとき光散乱層16の表面は粗面
化されていた。
First, as shown in FIG. 2, an n-type GaAs substrate 1
N on the n-type InGaAlP cladding layer 11, InGaAs
An 1P active layer 12, a p-type GaAlP cladding layer 13, a p-type GaAlAs current diffusion layer 15, a p-type InAlP light scattering layer 16, and a p-type GaAs contact layer 18 are sequentially formed by MOCVD. At this time, the surface of the light scattering layer 16 was roughened.

【0025】次に図3、図4に示すようにPEP等によ
りp型GaAsコンタクト層18上にSiO2 膜(或い
はその他のレジスト膜)21を形成し、これをマスクに
してAu/AuZnからなるp側電極19を蒸着により
形成する。このとき図5に示すようにコンタクト層18
及び光散乱層16の一部を熱燐酸等により選択エッチン
グした後にAu/AuZn電極19を蒸着してもよい。
Next, as shown in FIGS. 3 and 4, a SiO 2 film (or other resist film) 21 is formed on the p-type GaAs contact layer 18 by PEP or the like, and is made of Au / AuZn using this as a mask. The p-side electrode 19 is formed by vapor deposition. At this time, as shown in FIG.
The Au / AuZn electrode 19 may be deposited after selective etching of a part of the light scattering layer 16 with hot phosphoric acid or the like.

【0026】次に図6に示すようにレジスト膜21を除
去することによって、レジスト膜上のAu/AuZnを
リフトオフにより除去し、更にp型GaAsコンタクト
層の一部を選択エッチングにより除去し、コンタクト層
18及び電極19を円形状に形成する。このようにして
光散乱層の粗面化された表面17を素子表面に出すこと
になる。
Next, as shown in FIG. 6, by removing the resist film 21, Au / AuZn on the resist film is removed by lift-off, and a part of the p-type GaAs contact layer is removed by selective etching. The layer 18 and the electrode 19 are formed in a circular shape. Thus, the roughened surface 17 of the light scattering layer is exposed on the element surface.

【0027】その後n型基板10の光取り出し側と反対
の面にAu/AuGeからなるn側電極20を蒸着によ
り形成し、図1に示した半導体発光素子を得る。各層の
膜厚及びキャリア濃度を以下に示す。
Thereafter, an n-side electrode 20 made of Au / AuGe is formed on the surface of the n-type substrate 10 opposite to the light extraction side by vapor deposition to obtain the semiconductor light emitting device shown in FIG. The thickness and carrier concentration of each layer are shown below.

【0028】n型GaAs基板10(80μm,3×1
18cm-3) n型InGaAlPクラッド層11(1.0μm,5×
1017cm-3) InGaAlP活性層12(0.5μm,アンドープ) p型InGaAlAs電流拡散層15(5.0μm,1
×1018cm-3) p型InAlP光散乱層16(0.5μm,7×1017
cm-3) p型GaAsコンタクト層18(0.025μm,3×
1018cm-3) このようにして作成した半導体素子において、光散乱層
16についてもう少し詳細に説明する。
An n-type GaAs substrate 10 (80 μm, 3 × 1
0 18 cm −3 ) n-type InGaAlP cladding layer 11 (1.0 μm, 5 ×
10 17 cm −3 ) InGaAlP active layer 12 (0.5 μm, undoped) p-type InGaAlAs current diffusion layer 15 (5.0 μm, 1
× 10 18 cm −3 ) p-type InAlP light scattering layer 16 (0.5 μm, 7 × 10 17)
cm -3 ) p-type GaAs contact layer 18 (0.025 μm, 3 ×
10 18 cm −3 ) The light scattering layer 16 in the semiconductor device thus manufactured will be described in more detail.

【0029】InGaAlPはGaAs基板上に成長さ
せたとき、基板との格子不整合率と膜厚を変化させるこ
とにより、表面近傍に面内でほぼ均一な凹凸を生じる。
図7(a)に(311)A面GaAs基板上にInAl
P層を形成した場合、表面に凹凸が生じる条件を示す図
を示す。図中斜線で示した部分が表面に凹凸が生じる条
件である。その他の範囲では鏡面状の状態のままであっ
たり、ハッチが入ったり不均一に多結晶化した状態であ
るものである。
When InGaAlP is grown on a GaAs substrate, almost uniform in-plane irregularities are generated near the surface by changing the lattice mismatch ratio with the substrate and the film thickness.
FIG. 7A shows that (Al) on a (311) A-plane GaAs substrate.
The figure which shows the conditions which generate | occur | produce a surface unevenness when a P layer is formed is shown. The shaded portions in the figure are conditions under which the surface becomes uneven. In other ranges, the surface is in a mirror-like state, is hatched, or is non-uniformly polycrystallized.

【0030】上記のように光散乱層として用いるに十分
な結晶性を保ったまま凹凸の生じる条件で、InGaA
lP層を光散乱層として発光層の上部に成長形成するこ
とによって、エッチング等の余分な工程を経ることなく
膜質を良好に保ったまま、光散乱層を得ることが可能と
なる。従って反射による損失を防ぐことはもちろんのこ
とであり、良好な界面状態を有することで光の吸収を防
ぐことが可能であり、合わせて外部量子効率の向上を図
り得るものである。
As described above, InGaAs is formed under the condition that irregularities occur while maintaining sufficient crystallinity for use as a light scattering layer.
By growing the IP layer as a light-scattering layer above the light-emitting layer, it is possible to obtain a light-scattering layer while maintaining good film quality without performing an extra step such as etching. Therefore, it goes without saying that loss due to reflection can be prevented, light absorption can be prevented by having a favorable interface state, and external quantum efficiency can be improved in addition.

【0031】ここでInGaAlP系材料においては、
Alの混晶比が小さいほど表面に凹凸が現れ易く、より
薄い膜厚、より格子不整合率が小さい範囲においてもそ
の表面に凹凸が生じる傾向にある。図7(b)にAlの
組成が0の場合すなわちInGaPをA面GaAs基板
上に成長させた場合の良好な凹凸が生じる範囲を示す。
このように図7(a)と比較すると凹凸が生じる範囲
が、膜厚が薄く格子不整合率が低い方向に、すなわちグ
ラフの原点方向にシフトしていることが分かる。
Here, in the InGaAlP-based material,
As the mixed crystal ratio of Al is smaller, irregularities are more likely to appear on the surface, and the surface tends to have irregularities even in a range of a smaller film thickness and a smaller lattice mismatch rate. FIG. 7B shows a range where good irregularities occur when the Al composition is 0, that is, when InGaP is grown on an A-plane GaAs substrate.
As shown in FIG. 7A, it can be seen that the range in which the unevenness occurs is shifted in the direction in which the film thickness is small and the lattice mismatch rate is low, that is, in the direction toward the origin of the graph.

【0032】また図7(c)に格子不整合率が0.5%
のInAlPを、(100)面からの基板傾斜角度を変
えてGaAs基板上に成長した場合の、良好な凹凸が表
面に生じる範囲を示す図を示す。このように基板面方位
が(100)面からの傾斜角が小さくなるほどより膜厚
を厚くしなければ表面に凹凸が生じない傾向にあること
が分かる。
FIG. 7C shows that the lattice mismatch rate is 0.5%.
FIG. 3 is a diagram showing a range in which good unevenness occurs on the surface when InAlP is grown on a GaAs substrate while changing the substrate inclination angle from the (100) plane. As described above, it can be seen that as the inclination angle of the substrate from the (100) plane becomes smaller, the surface tends to have no irregularities unless the film thickness is increased.

【0033】図1で示した半導体発光素子でp側電極1
9の直径を200μmφとし、基板10をGaAs、ク
ラッド層11をIn0.5 Al0.5 P、活性層12をIn
0.5(Ga0.5 Al0.50.5 P、クラッド層13をI
0.5 Al0.5 P、電流拡散層15をGa0.2 Al0.8
As、光散乱層16をIn0.5+0.005 Al
0.5-0.005P、とした場合で順方向に電圧を印加して電
流を流したところ、558nmに発光を有し、光度が1
cdを越える高い発光を得た。比較例として光散乱層を
具備しない半導体発光素子を形成し比較したところ、本
実施例による素子は比較例に比べて約5倍の明るさを示
した。
The semiconductor light emitting device shown in FIG.
9, the substrate 10 is made of GaAs, the cladding layer 11 is made of In 0.5 Al 0.5 P, and the active layer 12 is made of In.
0.5 (Ga 0.5 Al 0.5 ) 0.5 P, the cladding layer 13
n 0.5 Al 0.5 P, and the current spreading layer 15 is Ga 0.2 Al 0.8
As, the light scattering layer 16 is made of In 0.5 + 0.005 Al
When a voltage was applied in the forward direction and a current was passed in the case of 0.5-0.005 P, light emission was at 558 nm and luminous intensity was 1
High luminescence exceeding cd was obtained. As a comparative example, when a semiconductor light emitting device having no light scattering layer was formed and compared, the device according to the present example showed about five times the brightness as compared with the comparative example.

【0034】このように本実施例によれば、光の取り出
し効率を高くすることができ非常に高い発光光度を得る
ことができる。本実施例では光散乱層としてInGaA
lPを用いたが、InGaAlPとGaAs基板に限定
されるものではなく、基板との格子不整合率及び膜厚を
選択することにより、表面に均一な凹凸を有する半導体
の組み合わせにより種々選択し用いることができる。
As described above, according to this embodiment, the light extraction efficiency can be increased, and a very high luminous intensity can be obtained. In this embodiment, InGaAs is used as the light scattering layer.
Although 1P was used, the present invention is not limited to InGaAlP and GaAs substrates, but can be selected and used in various ways by selecting a lattice mismatch ratio and a film thickness with the substrate and by combining semiconductors having uniform unevenness on the surface. Can be.

【0035】また光の取り出し効率を更に向上するため
に、光散乱層と空気との界面に更に屈折率の低いGaA
lAsキャップ層を形成することができる。また本実施
例では電流拡散層を設けたが、発光層において十分に電
流が広がるように材料系及び膜厚を選択することによっ
て、光散乱層にこの電流拡散層の機能を合わせ持たせる
ことができる。 (実施例2)図8は本発明の第2の実施例に係る半導体
発光素子の概略構成を示す断面図である。
In order to further improve the light extraction efficiency, GaAs having a lower refractive index is provided at the interface between the light scattering layer and air.
An As cap layer can be formed. Although the current diffusion layer is provided in the present embodiment, the light scattering layer can be provided with the function of the current diffusion layer by selecting the material system and the film thickness so that the current can be sufficiently spread in the light emitting layer. it can. (Embodiment 2) FIG. 8 is a sectional view showing a schematic configuration of a semiconductor light emitting device according to a second embodiment of the present invention.

【0036】n型GaAs基板80の主面上に格子整合
するようにn型Zn1-p Mgp1-q Seq クラッド層
81、アンドープCd1-r Znr Se活性層82、p型
Zn1-u Mgu1-v Sev クラッド層83からなるダ
ブルヘテロ構造部(発光層84)が成長形成されてい
る。
[0036] n-type n-type so as to be lattice-matched to GaAs substrate 80 on the main surface Zn 1-p Mg p S 1 -q Se q cladding layer 81, an undoped Cd 1-r Zn r Se active layer 82, p-type Zn 1-u Mg u S 1 -v Se v double heterostructure section constituted by the cladding layer 83 (light-emitting layer 84) is grown and formed.

【0037】この発光層84上に基板80、発光層84
に対してプラスに格子不整合するようにp型In0.5+w
Al0.5-w Pからなる光散乱層85が、格子不整合によ
る結晶歪によって表面86が粗面化され成長形成されて
いる。
On the light emitting layer 84, the substrate 80 and the light emitting layer 84
P-type In 0.5 + w
The light scattering layer 85 made of Al 0.5-w P is grown and formed with the surface 86 roughened by crystal distortion due to lattice mismatch.

【0038】この光散乱層85上に電極部としてp型I
nGaPコンタクト層87、p型GaAsコンタクト層
88、Au−Znからなるp側電極89が円形状に形成
されている。基板80の裏面にはAu−Geからなるn
側電極90が形成されている。尚、各層の成長にはMO
CVD法を用い、層81、82、83、85、87、8
8を1回の成長で形成した。
On the light scattering layer 85, a p-type I
An nGaP contact layer 87, a p-type GaAs contact layer 88, and a p-side electrode 89 made of Au-Zn are formed in a circular shape. On the back surface of the substrate 80, n made of Au-Ge
A side electrode 90 is formed. In addition, MO of each layer is grown.
The layers 81, 82, 83, 85, 87, 8 are formed by CVD.
8 was formed in one growth.

【0039】ダブルヘテロ構造を構成する発光層84の
各層の混晶比p,q,r,u,vは高い発光効率が得ら
れるようにクラッド層のバンドギャップは活性層のバン
ドギャップよりも大きくなるように選ばれる。また光散
乱層の混晶比wはp型Zn1-u Mgu1-v Sev クラ
ッド層83との格子不整合率が+0.5%となるように
設定した。
The mixed crystal ratios p, q, r, u, and v of each layer of the light emitting layer 84 constituting the double hetero structure are such that the band gap of the cladding layer is larger than the band gap of the active layer so as to obtain high luminous efficiency. Is chosen to be Mole fraction also light scattering layer w was set to be p-type Zn 1-u Mg u S 1 -v Se v lattice mismatch ratio between the cladding layer 83 is 0.5%.

【0040】また各層の膜厚及びキャリア濃度は以下に
示すものとした。 n型GaAs基板80(80μm,3×1018cm-3) n型ZnMgSSeクラッド層81(1.0μm,5×
1017cm-3) CdZnSe活性層82(0.5μm,アンドープ) p型ZnMgSSeクラッド層83(1μm,4×10
17cm-3) p型InAlP光散乱層85(0.3μm,7×1017
cm-3) p型InGaPコンタクト層87(0.025μm,3
×1018cm-3) p型GaAsコンタクト層88(0.1μm,3×10
18cm-3) このような構造でp側電極89の直径を200μmφと
して形成し、n型Zn1-p Mgp1-q Seq クラッド
層81、p型Zn1-u Mgu1-v Sev クラッド層8
3の混晶比をp=u=0.09、p=v=0.84、C
1-r Znr Se活性層82の混晶比rを0.8、p型
In0.5+w Al0.5-w P光散乱層の混晶比wをw=0.
005として素子を形成し、順方向に電圧を印加して電
流を流したところ、510nmに発光を有し光度0.5
cdを越える発光が得られた。
The thickness and carrier concentration of each layer were as shown below. n-type GaAs substrate 80 (80 μm, 3 × 10 18 cm −3 ) n-type ZnMgSSe cladding layer 81 (1.0 μm, 5 ×
10 17 cm -3 ) CdZnSe active layer 82 (0.5 μm, undoped) p-type ZnMgSSe cladding layer 83 (1 μm, 4 × 10
17 cm -3 ) p-type InAlP light scattering layer 85 (0.3 μm, 7 × 10 17)
cm -3 ) p-type InGaP contact layer 87 (0.025 μm, 3
× 10 18 cm −3 ) p-type GaAs contact layer 88 (0.1 μm, 3 × 10
18 cm -3) the diameter of the p-side electrode 89 in such a structure is formed as 200μmφ, n-type Zn 1-p Mg p S 1 -q Se q cladding layer 81, p-type Zn 1-u Mg u S 1 -v Se v clad layer 8
The mixed crystal ratio of p = u = 0.09, p = v = 0.84, C
The mixed crystal ratio r of the d 1-r Zn r Se active layer 82 is 0.8, and the mixed crystal ratio w of the p-type In 0.5 + w Al 0.5-w P light scattering layer is w = 0.
When a device was formed as 005 and a voltage was applied in the forward direction to flow a current, the device emitted light at 510 nm and had a luminous intensity of 0.5
Light emission exceeding cd was obtained.

【0041】比較例として光散乱層85がない半導体発
光素子形成し比較したところ、本実施例は比較例に比べ
約8倍の明るさを有していた。 (実施例3)図9は本発明の第3の実施例に係る半導体
発光素子の概略構成を示す断面図である。
As a comparative example, a semiconductor light emitting device without the light scattering layer 85 was formed and compared. As a result, the present example was about eight times brighter than the comparative example. (Embodiment 3) FIG. 9 is a sectional view showing a schematic structure of a semiconductor light emitting device according to a third embodiment of the present invention.

【0042】n型GaAs基板100の主面上に格子整
合するようにn型Ga1-i Ali Asクラッド層10
1、アンドープGa1-j AljAs活性層102、p型
Ga1-kAlAsクラッド層103からなるダブルヘテ
ロ構造部(発光層104)が成長形成されている。
The n-type Ga 1 -i Al i As clad layer 10 is lattice-matched on the main surface of the n-type GaAs substrate 100.
1, the double heterostructure section of undoped Ga 1-j Al j As active layer 102, p-type Ga 1-k AlAs cladding layer 103 (light emitting layer 104) is grown and formed.

【0043】この発光層104上に基板100、発光層
104に対してプラスに格子不整合するようにp型In
0.5+m Al0.5-m Pからなる光散乱層105が、格子不
整合による結晶歪によって表面106が粗面化され成長
形成されている。
On the light emitting layer 104, the p-type In is added so that the substrate 100 and the light emitting layer 104 are lattice-mismatched positively.
The light scattering layer 105 made of 0.5 + m Al 0.5-m P is grown and formed by roughening the surface 106 due to crystal strain caused by lattice mismatch.

【0044】この光散乱層105上に電極部としてp型
GaAsコンタクト層107、Au−Znからなるp側
電極108が円形状に形成されている。基板100の裏
面にはAu−Geからなるn側電極109が形成されて
いる。尚、各層の成長にはMOCVD法を用い、層10
1、102、103、105、107を1回の成長で形
成した。
On the light scattering layer 105, a p-type GaAs contact layer 107 and a p-side electrode 108 made of Au-Zn are formed in a circular shape as electrode portions. On the back surface of the substrate 100, an n-side electrode 109 made of Au-Ge is formed. The MOCVD method was used to grow each layer, and the layer 10 was grown.
1, 102, 103, 105 and 107 were formed by one growth.

【0045】ダブルヘテロ構造を構成するGaAlAs
発光層104のAl組成i,j,kは高い発光効率が得
られるように、j≦i,j≦kに設定されクラッド層の
バンドギャップは活性層のバンドギャップよりも大きく
なるように選ばれる。また光散乱層の混晶比mはGaA
s基板100との格子不整合率が+0.5%となるよう
に設定した。
GaAlAs Constituting Double Hetero Structure
The Al composition i, j, k of the light emitting layer 104 is set to j ≦ i, j ≦ k so as to obtain high luminous efficiency, and the band gap of the cladding layer is selected to be larger than the band gap of the active layer. . The mixed crystal ratio m of the light scattering layer is GaAs.
The lattice mismatch rate with the s substrate 100 was set to be + 0.5%.

【0046】また各層の膜厚及びキャリア濃度は以下に
示すものとした。 n型GaAs基板100(80μm,3×1018
-3) n型GaAlAsクラッド層101(1.0μm,5×
1017cm-3) GaAlAs活性層102(0.5μm,アンドープ) p型GaAlAsクラッド層103(1μm,4×10
17cm-3) p型InGaP光散乱層105(0.2μm,7×10
17cm-3) p型GaAsコンタクト層107(0.1μm,3×1
18cm-3) このような構造でp側電極108の直径を200μmφ
として形成し、n型Ga1-i Ali Asクラッド層10
1のAl組成iを0.8、Ga1-j Alj As活性層1
02のAl組成jを0.35、n型Ga1-k Alk As
クラッド層103のAl組成kを0.8、p型In
0.5+m Ga0.5-m P光散乱層の混晶比mを0.005と
して素子を形成し、順方向に電圧を印加して電流を流し
たところ、660nmに発光を有し外部量子効率が80
%を越える発光が得られた。
The thickness and carrier concentration of each layer were as shown below. n-type GaAs substrate 100 (80 μm, 3 × 10 18 c
m −3 ) n-type GaAlAs cladding layer 101 (1.0 μm, 5 ×
10 17 cm −3 ) GaAlAs active layer 102 (0.5 μm, undoped) p-type GaAlAs cladding layer 103 (1 μm, 4 × 10
17 cm -3 ) p-type InGaP light scattering layer 105 (0.2 μm, 7 × 10
17 cm -3 ) p-type GaAs contact layer 107 (0.1 μm, 3 × 1
0 18 cm −3 ) With such a structure, the diameter of the p-side electrode 108 is set to 200 μmφ.
And an n-type Ga 1-i Al i As clad layer 10
Al composition i of 0.8 and Ga 1-j Al j As active layer 1
02 with an Al composition j of 0.35 and n-type Ga 1-k Al k As
The Al composition k of the cladding layer 103 is 0.8, and the p-type In
A device was formed with the mixed crystal ratio m of the 0.5 + m Ga 0.5-m P light scattering layer set to 0.005, and when a voltage was applied in the forward direction and a current was passed, the device emitted light at 660 nm and had an external quantum efficiency of 660 nm. 80
% Was obtained.

【0047】比較例として光散乱層105がない半導体
発光素子形成し比較したところ、本実施例は比較例に比
べ約5倍の明るさを有していた。各実施例では基板にG
aAsを用い、ダブルヘテロ構造の発光層、電流拡散層
の機能も兼ね備えた光散乱層にInGaAlPを用いた
が、これらに限定されるものではない。
As a comparative example, when a semiconductor light emitting device without the light scattering layer 105 was formed and compared, the present example was about five times brighter than the comparative example. In each embodiment, G
Although aAs was used and InGaAlP was used for the light-scattering layer also having the functions of the light emitting layer and the current diffusion layer having the double hetero structure, the invention is not limited to these.

【0048】光散乱層としては基板や発光層とプラスに
格子不整合するような材料系を用いることを必須条件と
するが、なおかつ発光波長に対して十分に透明であるこ
とが光を取り出すためにはより好ましい。
It is essential that the light-scattering layer be made of a material system that has a lattice mismatch with the substrate or the light-emitting layer, but the light-scattering layer must be sufficiently transparent to the emission wavelength in order to extract light. Is more preferable.

【0049】また発光層はダブルヘテロ構造に限らずシ
ングルヘテロ構造、ホモ接合構造等用いることができ
る。更に発光層はSi等の1元系、InSb、BN、A
lN、InAs、InP、SiGe、GaAs、Ga
P、GaN等の2元系、GaAlN、InAsP、Ga
AlN、InAlAs、GaAsP、GaAlP、In
GaAs、CdZnSe、CdMnTe等の3元系、I
nGaAlP、InGaAsP、InGaAlAs、C
dMgZnSe、CuInAlSe、CuInGaSe
等の4元系、InGaAlAsP、InGaAlAsS
b、CdMgZnSSe、CuInGaSSe、CuI
nAlSSe等の5元系半導体等用いることができる。
The light emitting layer is not limited to the double hetero structure, but may be a single hetero structure, a homojunction structure, or the like. Further, the light emitting layer is made of a single element such as Si, InSb, BN, A
1N, InAs, InP, SiGe, GaAs, Ga
Binary system such as P, GaN, GaAlN, InAsP, Ga
AlN, InAlAs, GaAsP, GaAlP, In
Ternary system such as GaAs, CdZnSe, CdMnTe,
nGaAlP, InGaAsP, InGaAlAs, C
dMgZnSe, CuInAlSe, CuInGaSe
Quaternary, InGaAlAsP, InGaAlAsS
b, CdMgZnSSe, CuInGaSSe, CuI
A quinary semiconductor such as nAlSSe can be used.

【0050】光散乱層としては、Si、Ge等のIV族、
SiGe等のIV−IV族、GaAlAs、InGaAl
P、InGaAlAs、GaAlN、GaAlP等のII
I −V族、ZnSe、ZnSSe、CdMnTe、Zn
Te、CdMgZnSSe等のII-VI 族、カルコパイラ
イト系等の材料系のものが適用できるが、要は下地の発
光層或いは基板とプラスに格子不整合し、成長において
結晶歪によって表面に幾何学状の凹凸が生じる組み合わ
せであれば種々選択して用いることができる。
As the light scattering layer, a group IV such as Si or Ge,
IV-IV group such as SiGe, GaAlAs, InGaAl
II such as P, InGaAlAs, GaAlN, GaAlP
I-V group, ZnSe, ZnSSe, CdMnTe, Zn
Materials of the II-VI group such as Te, CdMgZnSSe and the like, such as chalcopyrite, can be used, but the point is that the lattice is positively mismatched with the underlying light emitting layer or substrate, and the surface has a geometrical shape due to crystal strain during growth. Various combinations can be selected and used as long as the combination produces the unevenness.

【0051】[0051]

【発明の効果】以上説明したように本発明によれば、基
板或いは発光層とプラスに格子不整合させることで半導
体層を成長させ、表面に幾何学状の凹凸を生じせしめる
ことによってこれを光散乱層として発光素子に用いるこ
とによって、界面にダメージを与えず、光吸収による損
失を防ぐことが可能となる。また、信頼性の高い半導体
発光素子を提供できるため素子の寿命をもたせることが
可能となる。更に、高いスループットを有し、素子間で
外部量子効率のばらつきのない半導体発光素子を提供す
ることができる。
As described above, according to the present invention, a semiconductor layer is grown by positively lattice-mismatching with a substrate or a light-emitting layer, and a geometrical unevenness is generated on the surface to reduce the light. By using the light-emitting element as the scattering layer, it is possible to prevent loss due to light absorption without damaging the interface. Further, since a highly reliable semiconductor light emitting device can be provided, the life of the device can be extended. Further, it is possible to provide a semiconductor light emitting device having high throughput and having no variation in external quantum efficiency among the devices.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の第1の実施例に係る半導体発光素子
の断面図
FIG. 1 is a cross-sectional view of a semiconductor light emitting device according to a first embodiment of the present invention.

【図2】 本発明の第1の実施例に係る半導体発光素子
の成長工程図
FIG. 2 is a growth process chart of the semiconductor light emitting device according to the first embodiment of the present invention.

【図3】 本発明の第1の実施例に係る半導体発光素子
の成長工程図
FIG. 3 is a growth process chart of the semiconductor light emitting device according to the first embodiment of the present invention.

【図4】 本発明の第1の実施例に係る半導体発光素子
の成長工程図
FIG. 4 is a growth process chart of the semiconductor light emitting device according to the first embodiment of the present invention.

【図5】 本発明の第1の実施例に係る半導体発光素子
の成長工程図
FIG. 5 is a growth process chart of the semiconductor light emitting device according to the first embodiment of the present invention.

【図6】 本発明の第1の実施例に係る半導体発光素子
の成長工程図
FIG. 6 is a growth process chart of the semiconductor light emitting device according to the first embodiment of the present invention.

【図7】 本発明の光散乱層として用いる半導体層の基
板に対する格子不整合率と膜厚の関係、成長基板の傾斜
角度と膜厚の関係を示す図。
FIG. 7 is a diagram showing a relationship between a lattice mismatch ratio and a film thickness of a semiconductor layer used as a light scattering layer of the present invention with respect to a substrate, and a relationship between a tilt angle and a film thickness of a growth substrate.

【図8】 本発明の第2の実施例に係る半導体発光素子
の断面図
FIG. 8 is a sectional view of a semiconductor light emitting device according to a second embodiment of the present invention.

【図9】 本発明の第3の実施例に係る半導体発光素子
の断面図
FIG. 9 is a sectional view of a semiconductor light emitting device according to a third embodiment of the present invention.

【図10】 従来の半導体発光素子の断面図FIG. 10 is a sectional view of a conventional semiconductor light emitting device.

【符号の説明】[Explanation of symbols]

10・・・基板 11・・・コンタクト層 12・・・活性層 13・・・コンタクト層 14・・・発光層 15・・・電流拡散層 16・・・光散乱層 17・・・粗面化された表面 18・・・コンタクト層 19・・・p側電極 20・・・n側電極 DESCRIPTION OF SYMBOLS 10 ... Substrate 11 ... Contact layer 12 ... Active layer 13 ... Contact layer 14 ... Light emitting layer 15 ... Current diffusion layer 16 ... Light scattering layer 17 ... Roughening Surface 18 18 Contact layer 19 P-side electrode 20 N-side electrode

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】GaAsからなる基板と、この基板上に形
成されたInGaAlP系の発光層と、この発光層上に
形成され、前記基板に対してプラスに0.1%以上2.
5%以下の格子不整合率で格子不整合し表面が格子歪
により粗面化されている、膜厚が0.05μm以上のI
nGaAlP系の光散乱層とを具備することを特徴とす
る半導体発光素子。
1. A substrate made of GaAs, an InGaAlP-based light emitting layer formed on the substrate , and 0.1% or more with respect to the substrate formed on the light emitting layer .
I with a film thickness of 0.05 μm or more is lattice-mismatched at a lattice mismatch rate of 5% or less, and the surface is roughened by lattice distortion.
A semiconductor light emitting device comprising an nGaAlP-based light scattering layer.
【請求項2】前記発光層から発光された光は前記光散乱
層の粗面化された表面を介して外部に取り出されること
を特徴とする請求項記載の半導体発光素子。
2. A semiconductor light emitting device according to claim 1, wherein the light emitted from the light-emitting layer, characterized in that it is taken out through the roughened surface of the light scattering layer.
【請求項3】GaAsからなる基板上にInGaAlP
系の発光層を成長形成する工程と、この発光層上に前記
基板に対してプラスに0.1%以上2.5%以下の格子
不整合率で格子不整合させるように膜厚が0.05μm
以上のInGaAlP系の半導体層を成長させ表面を粗
面化させることによって光散乱層を形成する工程とを具
備することを特徴とする半導体発光素子の製造方法。
3. An InGaAlP substrate on a GaAs substrate.
A step of growing emitting layer of the system, the to the light-emitting layer
A grid of 0.1% or more and 2.5% or less with respect to the substrate
Thickness of 0.05μm for lattice mismatch at mismatch rate
Forming a light-scattering layer by growing the above-mentioned InGaAlP-based semiconductor layer and roughening the surface to form a light-scattering layer.
【請求項4】チャンバー内に原料ガスを流すことによっ
てGaAs基板上に格子整合するように第1のクラッド
層を成長形成する工程と、前記原料ガスの混合比を調整
することによって第1のクラッド層上に、第1のクラッ
ド層に対してヘテロ接合するようにInGaAlP系
活性層を成長形成する工程と、前記原料ガスの混合比を
調整することによって前記活性層上に、前記活性層に対
してヘテロ接合するように第2のクラッド層を成長形成
する工程と、前記原料ガスの混合比を調整することによ
って前記第2のクラッド層上に、前記基板に対してプラ
スに0.1%以上2.5%以下の格子不整合率で格子不
整合するように膜厚が0.05μm以上のInGaAl
P系半導体層を成長させ、その成長時間を調整するこ
とによって前記半導体層表面に幾何学状の凹凸を形成す
る工程とを具備することを特徴とする半導体発光素子の
製造方法。
4. A step of growing and forming a first cladding layer so as to be lattice-matched on a GaAs substrate by flowing a source gas into a chamber, and adjusting the mixing ratio of the source gas to form a first cladding layer. A step of growing and forming an InGaAlP-based active layer on the layer so as to form a heterojunction with the first cladding layer; and adjusting the mixing ratio of the source gas to form an active layer on the active layer. Growing a second clad layer so as to form a heterojunction with the substrate, and adjusting the mixture ratio of the source gas to form a 0.1% plus layer on the second clad layer with respect to the substrate. InGaAl having a film thickness of 0.05 μm or more so as to perform lattice mismatch with a lattice mismatch rate of 2.5% or less and 2.5% or less.
The P type semiconductor layer is grown, a method of manufacturing a semiconductor light emitting element characterized by comprising the steps of forming a geometric shape of irregularities on the surface of the semiconductor layer by adjusting the growth time.
JP23625894A 1994-09-30 1994-09-30 Semiconductor light emitting device and method of manufacturing the same Expired - Lifetime JP3333330B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23625894A JP3333330B2 (en) 1994-09-30 1994-09-30 Semiconductor light emitting device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23625894A JP3333330B2 (en) 1994-09-30 1994-09-30 Semiconductor light emitting device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH08102548A JPH08102548A (en) 1996-04-16
JP3333330B2 true JP3333330B2 (en) 2002-10-15

Family

ID=16998121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23625894A Expired - Lifetime JP3333330B2 (en) 1994-09-30 1994-09-30 Semiconductor light emitting device and method of manufacturing the same

Country Status (1)

Country Link
JP (1) JP3333330B2 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6091085A (en) * 1998-02-19 2000-07-18 Agilent Technologies, Inc. GaN LEDs with improved output coupling efficiency
JP3469484B2 (en) 1998-12-24 2003-11-25 株式会社東芝 Semiconductor light emitting device and method of manufacturing the same
US6876003B1 (en) 1999-04-15 2005-04-05 Sumitomo Electric Industries, Ltd. Semiconductor light-emitting device, method of manufacturing transparent conductor film and method of manufacturing compound semiconductor light-emitting device
JP3586594B2 (en) 1999-08-25 2004-11-10 シャープ株式会社 Semiconductor light emitting device and method of manufacturing the same
US6486499B1 (en) * 1999-12-22 2002-11-26 Lumileds Lighting U.S., Llc III-nitride light-emitting device with increased light generating capability
JP2001298212A (en) 2000-02-07 2001-10-26 Sharp Corp Semiconductor light-emitting element and method of manufacturing the same
TW564584B (en) * 2001-06-25 2003-12-01 Toshiba Corp Semiconductor light emitting device
US7119377B2 (en) * 2004-06-18 2006-10-10 3M Innovative Properties Company II-VI/III-V layered construction on InP substrate
TWI269466B (en) * 2004-06-18 2006-12-21 Showa Denko Kk Group III nitride semiconductor light emitting device
JP4899348B2 (en) 2005-05-31 2012-03-21 信越半導体株式会社 Method for manufacturing light emitting device
JP4986445B2 (en) 2005-12-13 2012-07-25 昭和電工株式会社 Gallium nitride compound semiconductor light emitting device
JP2007220865A (en) * 2006-02-16 2007-08-30 Sumitomo Chemical Co Ltd Group iii nitride semiconductor light emitting device, and its manufacturing method
JP4903643B2 (en) * 2007-07-12 2012-03-28 株式会社東芝 Semiconductor light emitting device
CN102208507A (en) * 2011-05-03 2011-10-05 映瑞光电科技(上海)有限公司 Light-emitting diode (LED) and manufacturing method thereof
JP2012019246A (en) * 2011-10-25 2012-01-26 Toshiba Corp Semiconductor light emitting element
JP2013070099A (en) * 2013-01-08 2013-04-18 Toshiba Corp Method for manufacturing semiconductor light-emitting element

Also Published As

Publication number Publication date
JPH08102548A (en) 1996-04-16

Similar Documents

Publication Publication Date Title
JP3333330B2 (en) Semiconductor light emitting device and method of manufacturing the same
US5414281A (en) Semiconductor light emitting element with reflecting layers
JP3643665B2 (en) Semiconductor light emitting device
JPH07254732A (en) Semiconductor light emitting device
JP2007088351A (en) Light emitting diode and epitaxial wafer therefor
JP3152708B2 (en) Semiconductor light emitting device
JP3264563B2 (en) Semiconductor light emitting device and method of manufacturing the same
JPH08222763A (en) Semiconductor light emitting element
US7230281B2 (en) Semiconductor light emitting device
JP3406907B2 (en) Semiconductor light emitting diode
US8299480B2 (en) Semiconductor light emitting device and method for manufacturing same, and epitaxial wafer
JP3209786B2 (en) Semiconductor light emitting device
JPH0758808B2 (en) Light emitting element
JP3788444B2 (en) Light emitting diode and manufacturing method thereof
JP3700767B2 (en) Semiconductor light emitting device
JP3139890B2 (en) Semiconductor light emitting device
JPH0728052B2 (en) Semiconductor light emitting device and manufacturing method thereof
JP3005115B2 (en) Semiconductor light emitting device
KR100592395B1 (en) A algainp semiconductor device
JPH0983079A (en) Semiconductor element
JPH05335619A (en) Light-emitting diode and its manufacture
JPH08162670A (en) Semiconductor light emitting element
JP2894779B2 (en) Semiconductor light emitting device and method of manufacturing the same
KR100724083B1 (en) High brightness light emitting diode and fabrication method
JP4594993B2 (en) Semiconductor light emitting device and manufacturing method thereof

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080726

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090726

Year of fee payment: 7

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090726

Year of fee payment: 7

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100726

Year of fee payment: 8

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110726

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120726

Year of fee payment: 10

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130726

Year of fee payment: 11

EXPY Cancellation because of completion of term