JP3332005B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP3332005B2
JP3332005B2 JP9836699A JP9836699A JP3332005B2 JP 3332005 B2 JP3332005 B2 JP 3332005B2 JP 9836699 A JP9836699 A JP 9836699A JP 9836699 A JP9836699 A JP 9836699A JP 3332005 B2 JP3332005 B2 JP 3332005B2
Authority
JP
Japan
Prior art keywords
metal film
forming
dug portion
transparent insulating
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP9836699A
Other languages
Japanese (ja)
Other versions
JP2000294791A (en
Inventor
和美 平田
靖志 白石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP9836699A priority Critical patent/JP3332005B2/en
Publication of JP2000294791A publication Critical patent/JP2000294791A/en
Application granted granted Critical
Publication of JP3332005B2 publication Critical patent/JP3332005B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、特に基板の上に遮
光膜を配し層間膜で覆って遮光膜上方にTFTを形成す
る際にTFTの形成に悪影響を与える遮光膜に起因する
段差を低減する半導体装置および半導体製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention particularly relates to a method for forming a TFT above a light-shielding film by arranging a light-shielding film on a substrate and covering the film with an interlayer film. The present invention relates to a semiconductor device and a semiconductor manufacturing method for reducing the number of semiconductor devices.

【0002】[0002]

【従来の技術】図4は従来の半導体装置の平面図、図5
は図4の半導体装置の図4のA−A’部分の断面図、図
6は図4の半導体装置において発生するエッチング残渣
を示している。従来の半導体装置では、図4に示すよう
にガラス基板41上に遮光膜42を形成し、続いて図5
に示すように層間膜45を1μm程度の膜厚で成膜して
TFT44(薄膜トランジスタ)を形成する。この時画
素電極50を周回するようにゲート線Gおよびデータ線
Dに沿って形成される遮光膜42は図4に示すように井
桁状に形成される。
FIG. 4 is a plan view of a conventional semiconductor device, and FIG.
4 is a cross-sectional view of the semiconductor device of FIG. 4 taken along the line AA ′ of FIG. 4, and FIG. 6 shows an etching residue generated in the semiconductor device of FIG. In a conventional semiconductor device, a light-shielding film 42 is formed on a glass substrate 41 as shown in FIG.
As shown in (1), an interlayer film 45 is formed with a thickness of about 1 μm to form a TFT 44 (thin film transistor). At this time, the light-shielding film 42 formed along the gate line G and the data line D so as to go around the pixel electrode 50 is formed in a grid pattern as shown in FIG.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、従来技
術には以下に掲げる問題点があった。第1の問題点は、
遮光膜42による段差が生じ、平坦性が劣化することで
ある。
However, the prior art has the following problems. The first problem is
The step is caused by the light-shielding film 42, and the flatness is deteriorated.

【0004】そして第2の問題点は、遮光膜42による
段差が生ずるため、遮光膜42を井桁状に形成した場合
遮光膜42のない領域は穴状になり、この穴形状のため
に、この後に行われる各工程において図6に示すような
洗浄不良・エッチング残渣61等の問題が生ずることで
ある。
[0004] The second problem is that a step occurs due to the light-shielding film 42, so that when the light-shielding film 42 is formed in a grid pattern, the area without the light-shielding film 42 becomes a hole. In each of the subsequent steps, problems such as poor cleaning and etching residues 61 occur as shown in FIG.

【0005】本発明は斯かる問題点を鑑みてなされたも
のであり、その目的とするところは、基板の上に遮光膜
を配し層間膜で覆って遮光膜上方にTFTを形成する際
にTFTの形成に悪影響を与える遮光膜に起因する段差
を低減する半導体装置および半導体製造方法を提供する
点にある。
The present invention has been made in view of such a problem, and an object of the present invention is to provide a light-shielding film on a substrate, cover the film with an interlayer film, and form a TFT above the light-shielding film. It is an object of the present invention to provide a semiconductor device and a semiconductor manufacturing method for reducing a step caused by a light-shielding film that adversely affects the formation of a TFT.

【0006】[0006]

【課題を解決するための手段】本発明の請求項1に記載
の要旨は、透明絶縁基板表面に掘り込み部を形成する工
程と、前記掘り込み部の深さ以上の膜厚の金属膜を成膜
する工程と、前記金属膜の表面を平坦化する工程と、前
記金属膜を陽極酸化することにより前記掘り込み部の内
部に前記金属膜を残すとともに、前記掘り込み部の内部
以外の領域に透明絶縁層を形成する工程と、前記金属膜
の上部に薄膜トランジスタを形成する工程とを有するこ
とを特徴とする半導体装置の製造方法に存する。また本
発明の請求項2に記載の要旨は、前記金属膜の表面を平
坦化する工程は、研磨により行うことを特徴とする請求
項1に記載の半導体装置の製造方法に存する。また本発
明の請求項3に記載の要旨は、前記金属膜にアルミニウ
ムを用いることを特徴とする請求項1に記載の半導体装
置の製造方法に存する。また本発明の請求項4に記載の
要旨は、透明絶縁基板表面にフォトレジストをマスクと
して掘り込み部を形成する工程と、第1の金属膜を成膜
するとともに、リフトオフ法を用いて前記掘り込み部の
みに前記第1の金属膜を残す工程と、前記掘り込み部の
領域を含む前記透明絶縁基板の上部全面に第2の金属膜
を成膜する工程と、前記第2の金属膜の総てを陽極酸化
する工程と、前記第1の金属膜の上部に薄膜トランジス
タを形成する工程とを有することを特徴とする半導体装
置の製造方法に存する。また本発明の請求項5に記載の
要旨は、透明絶縁基板表面にフォトレジストをマスクと
して掘り込み部を形成する工程と、前記掘り込み部の深
さ以下の膜厚の金属膜を成膜するとともに、リフトオフ
法を用いて前記掘り込み部のみに前記金属膜を残す工程
と、前記金属膜を陽極酸化して前記掘り込み部の内側下
部に前記金属膜を残すとともに、前記掘り込み部の内側
上部に透明絶縁層を形成する工程と、前記掘り込み部の
領域を含む前記透明絶縁基板の上部全面に絶縁膜を形成
する工程と、前記金属膜の上部に薄膜トランジスタを形
成する工程とを有することを特徴とする半導体装置の製
造方法に存する。
The gist of the present invention resides in a step of forming a dug portion on the surface of a transparent insulating substrate, and a step of forming a metal film having a thickness not less than the depth of the dug portion. A step of forming a film, a step of flattening the surface of the metal film, and anodizing the metal film to leave the metal film inside the dug portion and an area other than the inside of the dug portion. And a step of forming a thin film transistor on the metal film. According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first aspect, wherein the step of flattening the surface of the metal film is performed by polishing. According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first aspect, wherein aluminum is used for the metal film. According to a fourth aspect of the present invention, there is provided a method of forming a dug portion on a surface of a transparent insulating substrate using a photoresist as a mask, forming a first metal film, and forming the dug portion using a lift-off method. Leaving the first metal film only in the recessed portion, forming a second metal film over the entire upper surface of the transparent insulating substrate including the region of the recessed portion, There is provided a method of manufacturing a semiconductor device, comprising: a step of anodizing all of them; and a step of forming a thin film transistor on the first metal film. The gist of claim 5 of the present invention is a step of forming a dug portion on a surface of a transparent insulating substrate using a photoresist as a mask, and forming a metal film having a thickness equal to or less than the depth of the dug portion. A step of leaving the metal film only in the dug portion using a lift-off method, and anodizing the metal film to leave the metal film at a lower portion inside the dug portion, and inside the dug portion. Forming a transparent insulating layer on the upper part, forming an insulating film on the entire upper surface of the transparent insulating substrate including the region of the dug portion, and forming a thin film transistor on the metal film. There is provided a method for manufacturing a semiconductor device, characterized in that:

【0007】[0007]

【発明の実施の形態】以下に示す各実施の形態の特徴
は、透明絶縁基板に作成した掘り込み部内に金属膜から
なる遮光膜を形成し、同時に透明絶縁層を平坦に作製す
ることで通常の遮光膜のような段差およびプロセスにお
ける洗浄不良・エッチング残渣を防止できることにあ
る。以下、本発明の実施の形態を図面に基づいて詳細に
説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The feature of each embodiment described below is that a metal film is formed in a dug portion formed on a transparent insulating substrate.
Comprising shielding film is formed is to be prevented poor cleaning etching residues in a stepped and processes as a conventional light-shielding film by flat manufactured simultaneously transparent insulating layer. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

【0008】(第1の実施の形態) 図1は本発明の第1の実施の形態にかかる半導体装置お
よび半導体製造方法を説明するためのプロセス図であっ
て、本実施の形態において示す図は、概ね図4のA−
A’部分の2ヶ所のTFTの付近を記載しているもので
ある。まず、図1(a)に示すように、透明絶縁基板と
してのガラス基板1に一般的なフォトリソグラフィとエ
ッチングを用いて例えば200nm程度の深さで掘り込
み部2を形成した後、スパッタ法を用いて600nm程
度の膜厚でアルミニウム3を成膜する。続いて、図1
(b)に示すように、アルミニウム3に例えばCMP
(化学的機械的研磨)法を用いて研磨を行い、上面が平
坦なアルミニウム31を形成する。この時に掘り込み部
2以外のガラス基板1上に残すアルミニウム3の膜厚は
例えば350nm程度とする。続いて、図1(c)に示
すように、アルミニウム31の陽極酸化を行い、掘り込
み部2以外の領域のアルミニウム31を酸化して透明絶
縁層32を形成すると同時に遮光膜35を作製する。続
いて、図1(d)に示すように、一般なTFT作製プロ
セスを用いてTFT4を作製する。この後、図示してい
ないが、層間膜コンタクトホールおよび透明電極等を形
成してLCD(液晶ディスプレイ)基板を作製すること
ができる。なお、第1の実施の形態では図1(b)に示
すようにCMP(化学的機械的研磨)法等の研磨法を用
いたが、これに特に限定されることなく、例えばリフロ
ー法を用いることも可能である。
FIG. 1 is a process diagram for explaining a semiconductor device and a semiconductor manufacturing method according to a first embodiment of the present invention. , Generally in FIG.
The figure shows the vicinity of two TFTs in the portion A '. First, as shown in FIG. 1 (a), a transparent insulating substrate
After forming a dug portion 2 at a depth of, for example, about 200 nm on the glass substrate 1 by using general photolithography and etching, aluminum 3 is formed to a thickness of about 600 nm by using a sputtering method. . Subsequently, FIG.
As shown in (b), for example, CMP is applied to the aluminum 3.
Polishing is performed using (chemical mechanical polishing) method to form aluminum 31 having a flat upper surface. At this time, the thickness of the aluminum 3 left on the glass substrate 1 other than the dug portion 2 is, for example, about 350 nm. Subsequently, as shown in FIG. 1C, anodization of the aluminum 31 is performed to oxidize the aluminum 31 in a region other than the dug portion 2 to form the transparent insulating layer 32, and at the same time, the light shielding film 35 is formed. Subsequently, as shown in FIG. 1D, a TFT 4 is manufactured using a general TFT manufacturing process. After that, although not shown, an LCD (liquid crystal display) substrate can be manufactured by forming an interlayer film contact hole and a transparent electrode. In the first embodiment, a polishing method such as a CMP (Chemical Mechanical Polishing) method is used as shown in FIG. 1B. However, the present invention is not particularly limited thereto. For example, a reflow method is used. It is also possible.

【0009】本実施の形態では、TFT4の光リークに
対する遮光膜35の膜厚は掘り込み部2の深さによって
決められ、研磨によるアルミニウム3をガラス基板1上
に残す厚さとアルミニウム3の膜厚によって透明絶縁層
32の膜厚を規定することができ、かつ、透明絶縁層3
2を平坦に作製することができる。このため、従来方法
による場合と異なり段差が生ずることがない。従って、
凹凸の緩和によりLCD基板は平坦性が向上し、また、
この後に行われるTFT作製工程における、遮光膜35
の段差に起因する洗浄不良やエッチング残渣等の問題を
解消できる。
In this embodiment, the thickness of the light-shielding film 35 against the light leakage of the TFT 4 is determined by the depth of the dug portion 2, and the thickness of the polished aluminum 3 on the glass substrate 1 and the thickness of the aluminum 3 The thickness of the transparent insulating layer 32 can be specified by the
2 can be made flat. Therefore, there is no step difference unlike the case of the conventional method. Therefore,
The flatness of the LCD substrate is improved by alleviating the unevenness.
The light shielding film 35 in the TFT manufacturing process performed thereafter
The problems such as poor cleaning and etching residue caused by the step can be solved.

【0010】以上説明したように、第1の実施の形態に
よれば、以下に掲げる効果を奏する。第1の効果は、平
坦性の向上によりLCD基板の凹凸が緩和され、また、
平坦性ゆえに遮光膜35の段差に起因する洗浄不良やエ
ッチング残渣等の問題が発生しなくなることである。そ
して第2の効果は、遮光膜35と透明絶縁層32の関係
を、掘り込み部2の深さとアルミニウム3の膜厚および
研磨量から任意に決めることができることである。
As described above, the first embodiment has the following advantages. The first effect is that the unevenness of the LCD substrate is reduced by improving the flatness.
Because of the flatness, problems such as poor cleaning and etching residues caused by steps of the light-shielding film 35 do not occur. The second effect is that the relationship between the light-shielding film 35 and the transparent insulating layer 32 can be arbitrarily determined from the depth of the dug portion 2, the thickness of the aluminum 3 and the polishing amount.

【0011】(第2の実施の形態) 図2は本発明の第2の実施の形態にかかる半導体装置お
よび半導体製造方法を説明するためのプロセス図であっ
て、本実施の形態において示す図は、概ね図4のA−
A’部分の2ヶ所のTFTの付近を記載しているもので
ある。まず、図2(a)に示すように、透明絶縁基板と
してのガラス基板1にフォトレジスト(PR)11を塗
布した後に一般的なフォトリソグラフィとエッチング技
術を用いて例えば200nm程度の深さで掘り込み部2
を形成する。続いて、図2(b)に示すように、スパッ
タ法を用いて200nm程度の膜厚でアルミニウム3を
成膜する。続いて、図2(c)に示すように、リフトオ
フ法を用いて掘り込み部2の内部にのみにアルミニウム
3を残した後、スパッタ法を用いて350nm程度の膜
厚でアルミニウム33を成膜する。続いて、図2(d)
に示すように、アルミニウム33の陽極酸化を行い、掘
り込み部2以外の領域のアルミニウム33を酸化して透
明絶縁層34を形成すると同時に遮光膜35を作製す
る。続いて、図2(e)に示すように、一般なTFT作
製プロセスを用いてTFT4を作製する。この後、図示
していない層間膜コンタクトホールおよび透明電極等を
形成してLCD基板を作製することができる。なお、第
2の実施の形態では図2(c)に示すようにリフトオフ
を行った後にアルミニウム33をスパッタしているが、
この間に研磨またはレーザ照射によるリフローを行って
より強固な平坦化を行うことも可能である。
(Second Embodiment) FIG. 2 is a process diagram for explaining a semiconductor device and a semiconductor manufacturing method according to a second embodiment of the present invention. , Generally in FIG.
The figure shows the vicinity of two TFTs in the portion A '. First, as shown in FIG. 2 (a), a transparent insulating substrate
After a photoresist (PR) 11 is applied to the glass substrate 1 thus formed, the dug portion 2 is formed to a depth of, for example, about 200 nm using a general photolithography and etching technique.
To form Subsequently, as shown in FIG. 2B, aluminum 3 is formed to a thickness of about 200 nm by using a sputtering method. Subsequently, as shown in FIG. 2C, after leaving aluminum 3 only inside the dug portion 2 using a lift-off method, aluminum 33 is formed to a thickness of about 350 nm using a sputtering method. I do. Subsequently, FIG.
As shown in FIG. 6, the anodic oxidation of the aluminum 33 is performed to oxidize the aluminum 33 in a region other than the dug portion 2 to form the transparent insulating layer 34 and simultaneously form the light shielding film 35. Subsequently, as shown in FIG. 2E, a TFT 4 is manufactured using a general TFT manufacturing process. Thereafter, a not-shown interlayer film contact hole, a transparent electrode, and the like are formed to manufacture an LCD substrate. In the second embodiment, aluminum 33 is sputtered after lift-off is performed as shown in FIG.
During this time, it is also possible to perform stronger flattening by performing reflow by polishing or laser irradiation.

【0012】以上説明したように、第2の実施の形態に
よれば、以下に掲げる効果を奏する。第1の効果は、平
坦性の向上によりLCD基板の凹凸が緩和され、また、
平坦性ゆえに遮光膜35の段差に起因する洗浄不良やエ
ッチング残渣等の問題が発生しなくなることである。そ
して第2の効果は、遮光膜35と透明絶縁層34の関係
を、掘り込み部2の深さとアルミニウム3の膜厚および
研磨量から任意に決めることができることである。
As described above, according to the second embodiment, the following effects can be obtained. The first effect is that the unevenness of the LCD substrate is reduced by improving the flatness.
Because of the flatness, problems such as poor cleaning and etching residues caused by steps of the light-shielding film 35 do not occur. The second effect is that the relationship between the light-shielding film 35 and the transparent insulating layer 34 can be arbitrarily determined from the depth of the dug portion 2, the film thickness of the aluminum 3, and the polishing amount.

【0013】(第3の実施の形態) 図3は本発明の第3の実施の形態にかかる半導体装置お
よび半導体製造方法を説明するためのプロセス図であっ
て、本実施の形態において示す図は、概ね図4のA−
A’部分の2ヶ所のTFTの付近を記載しているもので
ある。まず、図3(a)に示すように、透明絶縁基板と
してのガラス基板1にフォトレジスト(PR)11を塗
布した後に一般的なフォトリソグラフィとエッチングを
用いて例えば200nm程度の深さで掘り込み部2を形
成する。続いて、図3(b)に示すように、スパッタ法
を用いて150nm程度の膜厚でアルミニウム3を成膜
する。続いて、図3(c)に示すように、リフトオフ法
を用いて掘り込み部2の内部にのみにアルミニウム36
を残す。続いて、図3(d)に示すように、アルミニウ
ム36の陽極酸化を行い、透明絶縁層37を形成すると
同時に遮光膜35を作製し、その上に絶縁膜38を形成
する。続いて、図3(e)に示すように、一般なTFT
作製プロセスを用いてTFT4を作製する。この後、図
示していない層間膜コンタクトホールおよび透明電極等
を形成してLCD基板を作製することができる。
Third Embodiment FIG. 3 is a process diagram for explaining a semiconductor device and a semiconductor manufacturing method according to a third embodiment of the present invention. , Generally in FIG.
The figure shows the vicinity of two TFTs in the portion A '. First, as shown in FIG. 3 (a), a transparent insulating substrate
After the photoresist (PR) 11 is applied to the glass substrate 1 thus formed, the dug portion 2 is formed to a depth of, for example, about 200 nm by using general photolithography and etching. Subsequently, as shown in FIG. 3B, aluminum 3 is formed to a thickness of about 150 nm using a sputtering method. Subsequently, as shown in FIG. 3 (c), the aluminum 36 is formed only inside the dug portion 2 using the lift-off method.
Leave. Subsequently, as shown in FIG. 3D, anodization of the aluminum 36 is performed to form the transparent insulating layer 37 and simultaneously form the light shielding film 35, and the insulating film 38 is formed thereon. Subsequently, as shown in FIG.
The TFT 4 is manufactured using a manufacturing process. Thereafter, a not-shown interlayer film contact hole, a transparent electrode, and the like are formed to manufacture an LCD substrate.

【0014】以上説明したように、第3の実施の形態に
よれば、以下に掲げる効果を奏する。第1の効果は、平
坦性の向上によりLCD基板の凹凸が緩和され、また、
平坦性ゆえに遮光膜35の段差に起因する洗浄不良やエ
ッチング残渣等の問題が発生しなくなることである。そ
して第2の効果は、遮光膜35と透明絶縁層37の関係
を、掘り込み部2の深さとアルミニウム3の膜厚および
研磨量から任意に決めることができることである。
As described above, according to the third embodiment, the following effects can be obtained. The first effect is that the unevenness of the LCD substrate is reduced by improving the flatness.
Because of the flatness, problems such as poor cleaning and etching residues caused by steps of the light-shielding film 35 do not occur. The second effect is that the relationship between the light-shielding film 35 and the transparent insulating layer 37 can be arbitrarily determined from the depth of the dug portion 2, the thickness of the aluminum 3 and the polishing amount.

【0015】なお、本発明が上記各実施の形態に限定さ
れず、本発明の技術思想の範囲内において、各実施の形
態は適宜変更され得ることは明らかである。また上記構
成部材の数、位置、形状等は上記実施の形態に限定され
ず、本発明を実施する上で好適な数、位置、形状等にす
ることができる。また、各図において、同一構成要素に
は同一符号を付している。
It should be noted that the present invention is not limited to the above embodiments, and it is clear that each embodiment can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to suitable numbers, positions, shapes, and the like for implementing the present invention. In each drawing, the same components are denoted by the same reference numerals.

【0016】[0016]

【発明の効果】本発明は以上のように構成されているの
で、以下に掲げる効果を奏する。第1の効果は、平坦性
の向上によりLCD基板の凹凸が緩和され、また、平坦
性ゆえに遮光膜の段差に起因する洗浄不良やエッチング
残渣等の問題が発生しなくなることである。そして第2
の効果は、遮光膜と透明絶縁層の関係を、掘り込み部の
深さとアルミニウムの膜厚および研磨量から任意に決め
ることができることである。
Since the present invention is configured as described above, the following effects can be obtained. The first effect is that the unevenness of the LCD substrate is reduced by the improvement of the flatness, and problems such as poor cleaning and etching residue due to the step of the light shielding film due to the flatness do not occur. And the second
The effect of (1) is that the relationship between the light-shielding film and the transparent insulating layer can be arbitrarily determined from the depth of the dug portion, the film thickness of aluminum and the polishing amount.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態にかかる半導体装置
および半導体製造方法を説明するためのプロセス図であ
る。
FIG. 1 is a process diagram for explaining a semiconductor device and a semiconductor manufacturing method according to a first embodiment of the present invention.

【図2】本発明の第2の実施の形態にかかる半導体装置
および半導体製造方法を説明するためのプロセス図であ
る。
FIG. 2 is a process diagram illustrating a semiconductor device and a semiconductor manufacturing method according to a second embodiment of the present invention.

【図3】本発明の第3の実施の形態にかかる半導体装置
および半導体製造方法を説明するためのプロセス図であ
る。
FIG. 3 is a process diagram illustrating a semiconductor device and a semiconductor manufacturing method according to a third embodiment of the present invention.

【図4】従来の半導体装置の平面図である。FIG. 4 is a plan view of a conventional semiconductor device.

【図5】図4の半導体装置の図4のA−A’部分の断面
図である。
FIG. 5 is a cross-sectional view of the semiconductor device of FIG. 4 taken along the line AA ′ of FIG. 4;

【図6】図4の半導体装置において発生するエッチング
残渣を示している。
FIG. 6 shows an etching residue generated in the semiconductor device of FIG. 4;

【符号の説明】[Explanation of symbols]

1…ガラス基板 2…掘り込み部 3…アルミニウム 4…TFT(薄膜トランジスタ) 11…フォトレジスト(PR) 31…アルミニウム 32…透明絶縁層 33…アルミニウム 34…透明絶縁層 35…遮光膜 36…アルミニウム 37…透明絶縁層 38…絶縁膜 D…ゲート線 G…データ線 DESCRIPTION OF SYMBOLS 1 ... Glass substrate 2 ... Digging part 3 ... Aluminum 4 ... TFT (thin film transistor) 11 ... Photoresist (PR) 31 ... Aluminum 32 ... Transparent insulating layer 33 ... Aluminum 34 ... Transparent insulating layer 35 ... Light shielding film 36 ... Aluminum 37 ... Transparent insulating layer 38: insulating film D: gate line G: data line

フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 29/786 H01L 21/336 G02F 1/1368 Continuation of the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 29/786 H01L 21/336 G02F 1/1368

Claims (5)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 透明絶縁基板表面に掘り込み部を形成す
る工程と、前記掘り込み部の深さ以上の膜厚の金属膜を
成膜する工程と、前記金属膜の表面を平坦化する工程
と、 前記金属膜を陽極酸化することにより前記掘り込
み部の内部に前記金属膜を残すとともに、前記掘り込み
部の内部以外の領域に透明絶縁層を形成する工程と、前
記金属膜の上部に薄膜トランジスタを形成する工程とを
有することを特徴とする半導体装置の製造方法。
1. A step of forming a dug portion on the surface of a transparent insulating substrate, a step of forming a metal film having a thickness greater than the depth of the dug portion, and a step of flattening the surface of the metal film Anodizing the metal film to leave the metal film inside the dug portion, and forming a transparent insulating layer in a region other than the inside of the dug portion; Forming a thin film transistor.
【請求項2】 前記金属膜の表面を平坦化する工程は、
研磨により行うことを特徴とする請求項1に記載の半導
体装置の製造方法。
2. The step of flattening the surface of the metal film,
The method according to claim 1, wherein the method is performed by polishing.
【請求項3】 前記金属膜にアルミニウムを用いること
を特徴とする請求項1に記載の半導体装置の製造方法。
3. The method according to claim 1, wherein aluminum is used for the metal film.
【請求項4】 透明絶縁基板表面にフォトレジストをマ
スクとして掘り込み部を形成する工程と、第1の金属膜
を成膜するとともに、リフトオフ法を用いて前記掘り込
み部のみに前記第1の金属膜を残す工程と、前記掘り込
み部の領域を含む前記透明絶縁基板の上部全面に第2の
金属膜を成膜する工程と、前記第2の金属膜の総てを陽
極酸化する工程と、前記第1の金属膜の上部に薄膜トラ
ンジスタを形成する工程とを有することを特徴とする半
導体装置の製造方法。
4. A step of forming a dug portion on a surface of a transparent insulating substrate using a photoresist as a mask, forming a first metal film, and forming the first metal film only on the dug portion using a lift-off method. Leaving a metal film, forming a second metal film over the entire upper surface of the transparent insulating substrate including the region of the dug portion, and anodizing all of the second metal film. Forming a thin film transistor on the first metal film.
【請求項5】 透明絶縁基板表面にフォトレジストをマ
スクとして掘り込み部を形成する工程と、前記掘り込み
部の深さ以下の膜厚の金属膜を成膜するとともに、リフ
トオフ法を用いて前記掘り込み部のみに前記金属膜を残
す工程と、前記金属膜を陽極酸化して前記掘り込み部の
内側下部に前記金属膜を残すとともに、前記掘り込み部
の内側上部に透明絶縁層を形成する工程と、前記掘り込
み部の領域を含む前記透明絶縁基板の上部全面に絶縁膜
を形成する工程と、前記金属膜の上部に薄膜トランジス
タを形成する工程とを有することを特徴とする半導体装
置の製造方法。
5. A step of forming a dug portion on a surface of a transparent insulating substrate using a photoresist as a mask, forming a metal film having a thickness equal to or less than a depth of the dug portion, and using a lift-off method. Leaving the metal film only in the dug portion, forming the transparent insulating layer on the inner upper portion of the dug portion, while anodizing the metal film to leave the metal film in the lower inner portion of the dug portion. Manufacturing a semiconductor device, comprising: forming an insulating film on the entire upper surface of the transparent insulating substrate including the region of the dug portion; and forming a thin film transistor on the metal film. Method.
JP9836699A 1999-04-06 1999-04-06 Method for manufacturing semiconductor device Expired - Lifetime JP3332005B2 (en)

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JP9836699A JP3332005B2 (en) 1999-04-06 1999-04-06 Method for manufacturing semiconductor device

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JP3332005B2 true JP3332005B2 (en) 2002-10-07

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Country Link
JP (1) JP3332005B2 (en)

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JP2011227524A (en) * 2011-07-21 2011-11-10 Getner Foundation Llc Liquid crystal display device and method for producing the same
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