JP3328180B2 - Automatic placement and routing method of integrated circuit and computer-readable recording medium recording the automatic placement and routing program - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic placement and routing method for an integrated circuit and a computer-readable recording medium on which the automatic placement and routing program is recorded. Things.

[0002]

2. Description of the Related Art A conventional automatic placement and routing method using a CAD apparatus is, for example, as shown in FIGS. Here, FIG. 5 is a flowchart showing the procedure of automatic placement and routing, and FIG. 6 is a configuration diagram of a basic logic cell.

In FIG. 1, a basic logic cell used for automatic placement and routing is manually created in an automatic cell design 11. At that time, sub-contacts and well contacts were always buried in the cells as a measure to prevent latch-up. In the automatic cell arrangement 12, the basic logic cells created in the automatic cell design 11 are automatically arranged using a CAD device. Then, the cells are automatically arranged 12 by the automatic wiring 13 between cells.
The wiring between the basic logic cells arranged in the above is connected to complete the layout.

FIG. 6 shows an example of the basic logic cell 2
FIG. 3 is a configuration diagram of a NAND cell. In the WAKU 26, a P-channel transistor section 24, an N-channel transistor section 25, an input A21, an input B22 and an output 23 can be input / output by two-layer metal wiring, and a well contact 27 on a power supply line 30 and a sub-contact on a GND line 29. 28.

[0005]

The first problem of the prior art is that it hinders a reduction in chip size. The reason is that automatic placement and routing is performed using cells having a large cell size in order to embed sub-contacts and well contacts in basic logic cells. A second problem is that sub-contacts and well contacts are inserted more than necessary (unnecessary). The reason is that, since sub-contacts and well contacts cannot be generated after automatic placement and routing, sub-contacts and well contacts are buried in advance in basic logic cells, and automatic placement and routing are performed using the cells. A third problem is that even if the cell size of the basic logic cell is increased, the sub-contact and the well contact are embedded in the cell. The reason is that there is no method for generating sub-contacts and well contacts after automatic placement and routing. A fourth problem is that the sub-contact and the well contact cannot be inserted at necessary places. The reason is that there is no method for detecting the presence or absence of the sub-contact and the well contact.

The present invention has been made in view of the above-described problems, and has as its object to further increase the degree of integration of an integrated circuit.

[0007]

In order to achieve the above object, according to the present invention, as a first means relating to an automatic arrangement and wiring method for an integrated circuit, basic logic cells are automatically arranged, In the method of automatically arranging and routing an integrated circuit, a virtual cell for generating a sub-contact or a well contact is provided in advance around a basic logic cell, and after automatic wiring is performed, the overlapping of the wiring and the basic logic cell is performed. A means of generating a sub-contact or a well contact based on a virtual cell which does not exist, and deleting a virtual cell overlapping a wiring and a basic logic cell is employed.

[0008]

[0009]

The second related to the automatic placement and routing method for an integrated circuit.
Means for inserting a virtual cell for generating a sub-contact or a well contact around the basic logic cell, automatically arranging the basic logic cell into which the virtual cell has been inserted, and Automatically routing between the logic cells; determining whether the automatically arranged basic logic cell and the virtual cell overlap; and if the determination result is negative, the wiring and the virtual cell overlap. Determining whether or not the virtual cell overlaps with the basic logical cell or the wiring, and deleting the corresponding virtual cell if it is determined that the virtual cell overlaps with the basic logical cell or the wiring. Generating a sub-contact or well contact based on the virtual cell; A step of Ntakuto to determine whether there, if the sub contact or well contact is not present in regular intervals, employing a means and a step of insert additional sub contact or well contact.

On the other hand, according to the present invention, as a means relating to a computer-readable recording medium recording an automatic placement and routing program, a step of inserting a virtual cell which is a sub-contact or a well contact around a basic logic cell, Automatically arranging the basic logic cells into which the virtual cells have been inserted, automatically arranging the basic logic cells after the arranging process, and determining whether the automatically arranged basic logic cells overlap the virtual cells. Determining whether or not the wiring overlaps the virtual cell if the result of the determination is negative; and determining that the virtual cell overlaps the basic logical cell or the wiring. Removing the relevant virtual cell, based on the virtual cell not overlapping the basic logical cell and the wiring. Generating sub-contacts or well-contacts; determining whether sub-contacts or well-contacts exist at regular intervals; and sub-contacts or wells if there are no sub-contacts or well contacts at regular intervals. And a step of additionally inserting a contact.

[0012]

According to the present invention, after performing automatic placement and routing,
A sub-contact or a well contact is generated based on a virtual cell provided in the basic logic cell, and the presence or absence of the sub-contact or the well contact is detected. To increase the degree of integration of the integrated circuit.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart illustrating a processing procedure of the automatic placement and routing according to the present embodiment. Note that the series of processes shown in this flowchart show the processes of the automatic placement and routing program,
The automatic placement and routing of an integrated circuit described below is realized by installing the automatic placement and routing program in a computer from a magnetic or optical recording medium.

In FIG. 1, a basic logic cell is designed in an automatic cell design A1. Then, in the insertion A2 of the virtual cell, a region where the well contact can be arranged on the extension of the power supply line, a region where the well contact can be arranged on the upper side of the cell, and GND in the basic logic cell designed in the automatic cell design A1. The virtual cell is inserted into a region where the sub-contact can be arranged on the line extension and a region where the sub-contact can be arranged on the lower side of the cell.

In automatic cell arrangement A3, the basic logic cells are automatically arranged using a CAD device. Further, in the wiring A4 between the cells, the wiring between the basic logic cells arranged in the automatic cell arrangement A3 is connected. Then, if the virtual cell and another basic logical cell overlap, the virtual cell is deleted (steps A5 and A6), and if the virtual cell and the metal wiring overlap, the virtual cell is deleted (steps A7 and A).
8).

Subsequently, the production of a subcon and a wellcon A9
, A sub-contact and a well contact are generated from a virtual cell. Then, a portion where there is no sub-contact or well contact is detected within a certain interval, and a sub-contact or well contact is generated in a portion where there is no sub-contact or well contact (step A10,
A11). With the above processing, the layout of the integrated circuit is completed.

Next, FIG. 2 is a configuration diagram of a basic logic cell in this embodiment. The basic logic cell is a 2NAND cell, similar to the one shown in FIG.

In this figure, virtual cells 121, 121 are arranged on an extension of the power supply line 130 in a region where a well contact can be arranged. In addition, the power supply line 13
On the upper side of 0, a virtual cell 124 is arranged in a region where a well contact can be arranged. On the extension of the GND line 131, the virtual cells 122 are arranged in a region where the sub contact can be arranged. On the lower side of the GND line 131, a virtual cell 1
23 and 123 are arranged. By employing such a configuration, it is possible to reduce the area of the integrated circuit (semiconductor integrated circuit) only in the region B as compared with the conventional 2NAND cell (see FIG. 6).

FIG. 3 is a block diagram of the basic logic cell after the processing of the wiring A4 between the cells shown in FIG. 1 has been completed. In this figure, virtual cells 141 and 146 are:
Processing A for judging whether the arrangement overlaps with the virtual cell
5. The virtual cell to be deleted by the processing A7 for determining whether or not the virtual cell and the metal wiring overlap. Virtual cell 1
Reference numerals 43a, 142a, 143b, and 142b are virtual cells in which sub-contacts and well-contacts are generated in the generation A9 of the sub-control and well-con.

By the processing up to generation A9 of the subcontractor and the wellcon, the well contact 150 is generated from the virtual cell 143a as shown in FIG.
The sub-contact 151 is generated from b. According to this embodiment, the area can be reduced without inserting unnecessary sub-contacts and well contacts.

[0021]

As described above, according to the present invention,
Further higher integration of the integrated circuit can be achieved.
For example, if the usage rate of the basic logic cell is 15% in the layout data of 99000 elements, the area is 12
% Reduction.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating a processing procedure of automatic placement and routing according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a basic logic cell according to an embodiment of the present invention.

FIG. 3 is a first configuration diagram after automatic placement and routing according to an embodiment of the present invention.

FIG. 4 is a second configuration diagram after automatic placement and routing according to an embodiment of the present invention.

FIG. 5 is a flowchart illustrating an example of a conventional automatic placement and routing processing procedure.

FIG. 6 is a configuration diagram showing a configuration example of a conventional basic logic cell.

[Explanation of symbols]

Reference numeral 21: 2 NAND input section a 22: 2 NAND input section b 23: 2 NAND output section 24: P-channel transistor section 25: N-channel transistor section 26: WAKU 27: well contact 28: sub-contact 29: … GND line 30… Power supply line 121… Virtual cell that can be replaced with a well contact 122… Virtual cell that can be replaced with a sub contact 123… Virtual cell that can be replaced with a sub contact 124 Virtual cell 130 that can be replaced Power supply line 131 GND line 141 Virtual cell 142a Virtual cell that can be replaced with a well contact 142b Virtual cell that can be replaced with a sub contact 143a virtual cell that can be replaced with a well contact 143b virtual cell that can be replaced with a sub contact 145 metal wiring 146 virtual cell 150 well contact 151 sub contact

Continuation of the front page (56) References JP-A-8-339392 (JP, A) JP-A-3-82140 (JP, A) JP-A-3-283546 (JP, A) JP-A-9-232434 (JP) , A) JP-A-8-222640 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/82 G06F 17/50

Claims (3)

(57) [Claims] 1. A method of automatically arranging basic logic cells and automatically arranging and wiring between the basic logic cells , wherein a virtual cell for generating a sub-contact or a well contact around the basic logic cell is defined in advance. After the provision and automatic wiring, a sub-contact or a well contact is generated based on a virtual cell having no overlap with the wiring and the basic logic cell, and the virtual cell overlapping with the wiring and the basic logic cell is deleted. A method for automatically arranging and routing an integrated circuit. 2. A step of inserting a virtual cell for generating a sub-contact or a well contact around a basic logical cell; a step of automatically arranging the basic logical cell into which the virtual cell is inserted; Automatically routing between basic logic cells; determining whether the automatically arranged basic logic cell and virtual cell overlap; and if the determination result is negative, the wiring and virtual cell overlap. Determining whether or not the virtual cell overlaps the basic logical cell or the wiring; and deleting the relevant virtual cell if it is determined that the virtual cell overlaps the basic logical cell or the wiring. Generating sub-contacts or well-contacts based on the virtual cells that do not exist; A step of determining whether or not a sub-contact or a well contact exists; and a step of additionally inserting a sub-contact or a well contact when there is no sub-contact or well contact at regular intervals. Automatic placement and routing method. 3. A step of inserting a virtual cell for generating a sub-contact or a well contact around a basic logical cell; a step of automatically arranging the basic logical cell into which the virtual cell has been inserted; Automatically routing between basic logic cells; determining whether the automatically arranged basic logic cell and virtual cell overlap; and if the determination result is negative, the wiring and virtual cell overlap. Determining whether or not the virtual cell overlaps the basic logical cell or the wiring; and deleting the relevant virtual cell if it is determined that the virtual cell overlaps the basic logical cell or the wiring. Generating sub-contacts or well-contacts based on the virtual cells that do not exist; Determining whether or not a sub-contact or a well-contact exists; and, if there is no sub-contact or well-contact at regular intervals, additionally inserting a sub-contact or a well contact. A computer-readable recording medium recording a wiring program.