JP3324465B2 - Digital audio broadcast receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital audio broadcast receiver having an interference elimination function of extracting only a desired signal by eliminating adjacent channel interference and sending it to a demodulation unit.

[0002]

2. Description of the Related Art As an example of a conventional mobile receiver, a main part of a tuner section of a digital audio (also referred to as DAB) broadcast receiver using an OFDM system as a digital modulation system is configured as shown in FIG. I have. That is, the conventional D
The AB broadcast receiver takes in the power induced in the antenna,
The 1.5 GHz band L side band (1452-1492 MHz) currently used in Europe for DAB and the terrestrial television broadcasting frequency band III (175-250 MH) using the VHF band as a DAB parking slot.
z) is converted into a signal of the same frequency using the oscillation frequency from the reference frequency oscillator 1, and one of the converted signals is selected and sent to the tracking double-tuned filter 2 as an RF signal.

The RF signal output from the tracking double-tuned filter 2 is supplied to a mixer 5 via a variable gain amplifier 3 and a tracking double-tuned filter 4, and receives the oscillation frequency of the reference frequency oscillator 1 to divide the frequency and divide it into a local oscillator. The output signal of the frequency synthesizer 7 and the output signal of the tracking double-tuned filter 4 are mixed in the mixer 5 and down-converted into a signal of the first intermediate frequency (first intermediate frequency signal).

The first intermediate frequency signal is supplied to an AGC circuit 6 for envelope detection, and the gain of the variable gain amplifier 3 is controlled based on the envelope detection output to perform AGC. On the other hand, the tracking signal based on the phase comparison output of the frequency synthesizer 7 is used for tracking double-tuned filters 2 and 4.
Is supplied as a tuning control signal, and each center frequency is tuned to a desired reception frequency.

On the other hand, the first intermediate frequency signal is amplified by an amplifier 11, band-limited by a band-pass filter 12, and amplified by an amplifier 13. The first intermediate frequency signal amplified by the amplifier 13 is supplied to the mixer 15 via the attenuator 14, the oscillation frequency is mixed with the oscillation output signal from the fixed crystal oscillator 16 in the mixer 15, and the second intermediate frequency signal ( The second intermediate frequency signal is down-frequency converted.

The second intermediate frequency signal is supplied to an AGC circuit 17 for envelope detection, and the AGC is performed by controlling the attenuation rate of the attenuator 14 based on the envelope detection output.
On the other hand, the second intermediate frequency signal is amplified by the amplifier 18 and band-limited by the band-pass filter 19.
Amplified by the amplifier 20, the output of the amplifier 20 is DA
The signal is sent to the B demodulation unit 21 and demodulated.

The second intermediate frequency signal is supplied to an envelope detector 2
, And is subjected to envelope detection, and a low-pass filter 27 is provided.
And the high frequency band is cut off and output via the buffer amplifier 28. The output from the envelope detector 26 output via the buffer amplifier 28 is transmitted as an RSSI signal which is a signal for detecting the position of a NULL symbol added to the head of a transmission frame.

[0008]

However, DAB
In the case where the gap on the frequency axis between the desired wave and the undesired adjacent wave is narrower than the self-occupied bandwidth of the broadcast wave as in the case of broadcasting, the band pass provided in the intermediate frequency stage in the conventional DAB broadcast receiver With the out-of-band rejection capability of the filter, the selectivity characteristic is likely to be insufficient, and therefore, there is a problem that the filter is susceptible to adjacent interference.

[0009] Further, in a conventional DAB broadcast receiver, when performing synthesized tuning,
The frequency division value on the reference oscillator side and the voltage control oscillator side for comparing the phase of the PLL in the frequency synthesizer due to the fact that the reception channel step frequency is 16 kHz for the 1.5 GHz band of the L side band which is the reception frequency. In addition to increasing the frequency division value, the use of fast Fourier transform (FFT) processing for demodulation requires high accuracy in the oscillation frequency of the local oscillator. There was a problem that was difficult.

It is an object of the present invention to provide a DAB broadcast receiver in which the selectivity characteristics are substantially improved, and the accuracy of the oscillation frequency of the local oscillator is substantially improved by increasing the frequency division value.

[0011]

SUMMARY OF THE INVENTION A digital audio broadcast receiver according to the present invention has an FFT exceeding the number of carriers.
In a digital audio broadcast receiver in which demodulation processing is performed by FFT processing with the number of points ,
Power level data of FFT points on the high and low frequencies
Detecting means for calculating the presence or absence of the high-frequency side adjacent interference wave and the low-frequency side adjacent interference wave based on the power level data and the degree of adjacentness thereof, and detecting the degree of the adjacent interference wave detected by the detection means. First intermediate frequency shift means for shifting the center frequency of the first intermediate frequency signal at intervals of an integral multiple of the reception channel step frequency based on the degree of adjacentness; A second intermediate frequency shift means for shifting the frequency at a step frequency interval to return to the center frequency of the second intermediate frequency signal based on the center frequency of the first intermediate frequency signal before the frequency shift, and It is characterized in that it is transmitted.

In the digital audio broadcast receiver according to the present invention, the presence / absence of the high-frequency side adjacent interference wave and the low-frequency side adjacent interference wave and the degree of adjacency of the adjacent interference wave are detected by the detection means, and are detected by the detection means. The center frequency of the first intermediate frequency signal is shifted by the first intermediate frequency shift means at intervals of an integral multiple of the reception channel step frequency based on the degree of adjacency of the adjacent interference waves. Therefore, the pass band width of the band-pass filter provided between the frequency converting means for converting to the first intermediate frequency and the frequency converting means for converting to the second intermediate frequency is substantially frequency shifted. It becomes a state and the adjacent interference wave is removed.
Further, the center frequency of the frequency-shifted first intermediate frequency signal is changed to the center frequency of the second intermediate frequency signal based on the center frequency of the first intermediate frequency signal before the frequency shift at the reception channel step frequency interval. And the second intermediate frequency signal is sent to the demodulation means.
Therefore, the relationship between the carrier of the RF signal and the relationship between the carrier input to the demodulation means is maintained, and the FFT demodulation processing is not hindered.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A DAB broadcast receiver according to the present invention will be described below with reference to embodiments.

FIG. 1 shows a DA according to an embodiment of the present invention.
It is a block diagram which shows the structure of a B broadcast receiver. 1, the same components as those of the conventional DAB broadcast receiver shown in FIG. 7 are denoted by the same reference numerals.

An RF signal output from the tracking double-tuned filter 2 is supplied to a mixer 5 via a variable gain amplifier 3 and a tracking double-tuned filter 4, and receives the oscillation frequency of the reference frequency oscillator 1 and divides the frequency. The output signal of the frequency synthesizer 7 and the output signal of the tracking double-tuned filter 4 are mixed in the mixer 5 and down-frequency converted into a first intermediate frequency signal.

The first intermediate frequency signal is supplied to an AGC circuit 6 where it is subjected to envelope detection, and the gain of the variable gain amplifier 3 is controlled based on the envelope detection output to perform AGC. On the other hand, the tracking signal based on the phase comparison output of the frequency synthesizer 7 is used for tracking double-tuned filters 2 and 4.
Is supplied as a tuning control signal, and each center frequency is tuned to a desired reception frequency.

Here, the frequency synthesizer 7 is set to the frequency of the upper heterodyne, the frequency divider 8 as a prescaler for dividing the oscillation frequency of the reference frequency oscillator 1, the voltage controlled oscillator 71, and the voltage controlled oscillator 71. A frequency divider 72 as a programmable divider for dividing the oscillation output frequency, a phase comparator 74 for comparing the output of the frequency divider 8 with the output of the frequency divider 72, and a phase comparison output of the phase comparator 74 are input. P comprising a low-pass filter 73 for controlling the oscillation frequency of the voltage controlled oscillator 71 by the output
The frequency division ratio of the frequency divider 72 is controlled by a frequency division value signal output from a system controller 31 described later, and a lock detection signal when the PLL circuit 7 'is locked is an AND gate. The data is sent to the system controller 31 via the control unit 30.

On the other hand, the first intermediate frequency signal is amplified by the amplifier 11, band-limited by the band-pass filter 12, and amplified by the amplifier 13. The first intermediate frequency signal amplified by the amplifier 13 is supplied to the mixer 15 via the attenuator 14, mixed with the oscillation output signal from the frequency synthesizer 9 in the mixer 15, and down-converted into a second intermediate frequency signal. Second
The intermediate frequency signal is supplied to the AGC circuit 17 and subjected to envelope detection, and the AGC is performed by controlling the attenuation rate of the attenuator 14 based on the envelope detection output.

The frequency synthesizer 9 is set to a frequency of downheterodyne, and a frequency divider 10 as a prescaler for dividing the oscillation frequency of the reference frequency oscillator 1
A voltage-controlled oscillator 91, a frequency divider 92 as a programmable divider for dividing the oscillation output frequency of the voltage-controlled oscillator 91, and a phase comparator 94 for comparing the output of the frequency divider 10 with the output of the frequency divider 92. And a low-pass filter 93 which receives the phase comparison output of the phase comparator 94 and controls the oscillation frequency of the voltage controlled oscillator 91 by the output.
The frequency division ratio of the frequency divider 92 is controlled by a frequency division value signal output from a system controller 31 described later, and a lock detection signal when the PLL circuit 9 ′ is locked is output by an AND gate 30. Is sent to the system controller 31 via the.

On the other hand, the second intermediate frequency signal is an envelope detector 2
, And is subjected to envelope detection, and a low-pass filter 27 is provided.
And the high frequency band is cut off and output via the buffer amplifier 28. The output from the envelope detector 26 output via the buffer amplifier 28 is sent to the DAB demodulation unit 21 as an RSSI signal which is a signal for detecting the position of a NULL symbol added to the head of the transmission frame. Is done.

The second intermediate frequency signal is amplified by the amplifier 18, band-limited by the band-pass filter 19, amplified by the amplifier 20, and the output of the amplifier 20 is sent to the DAB demodulation unit 21. The DAB demodulation unit 21 includes an A / D converter 22, a quadrature detector 23 that receives the A / D conversion output and performs quadrature detection, an FFT operation that receives the quadrature detection output and performs FFT conversion and delay detection, a delay detection circuit 24, A digital signal processor 25 for calculating the symbol level is provided.

That is, in the DAB demodulation unit 21, the amplified output of the amplifier 20 is converted into digital data by the A / D converter 22, and the output data of the A / D converter 22 is supplied to the quadrature detector 23. The quadrature data I and Q are detected, and the quadrature detection output is subjected to FFT operation, delay detection circuit 24
Is supplied to a FFT operation for transforming the time domain into the frequency domain, and then delay-detected to demodulate the OFDM signal,
That is, DAB demodulation is performed. The OFDM demodulated output delayed and detected by the FFT operation and the delay detection circuit 24 is supplied to a digital signal processor 25, where the level of each symbol constituting the multicarrier is calculated and the frequency offset is estimated. The frequency offset is the A of the local oscillator for frequency conversion on the RF side.
Used as FC data.

The number of FFT points in the FFT operation and the delay detection circuit 24 in the DAB demodulation unit 21 is 2 N (N is a natural number). However, in the FFT operation and the delay detection circuit 24, a maximum of 153 6
(Transmission mode I) more than the number of multicarriers and 2
The FFT operation is performed with the number of points that is the Nth power of. Therefore, up to 1 53 6 multicarrier in DAB broadcasting receiver, that is, a bandwidth occupied 1.563MHz, since the required 2048 or more FFT points, as shown in FIG. 2, at least hope 256 kHz (= １ ／ (2048
-1 53 6)), 256FFT point in other words there will be.

In FIG. 2, the abscissa represents the frequency, the ordinate represents the power level, the symbol a represents the band limiting characteristic of the band-pass filter 12 in a normal state, and the symbol b represents the upper adjacent wave or an interference wave. A band limiting characteristic by the band-pass filter 12 is shown, and a symbol c indicates a frequency offset amount of the first intermediate frequency signal. A symbol d is a first intermediate frequency signal schematically shown with respect to a desired reception wave,
The symbol e is an upper adjacent wave or interference wave signal schematically shown, and the symbol f is a lower adjacent wave or interference wave signal schematically shown, and each of the desired reception wave d is 176 kHz.
Gap.

From the result of the FFT operation of the upper and lower bands in the DAB demodulation unit 21, the signal processor 25
Unwanted power levels such as other DBA broadcast signals and TV signals adjacent to the desired wave are detected, and the frequency signal from the system controller 31 to the frequency divider 72 of the frequency synthesizer 7 and A frequency-divided value signal is transmitted to the frequency divider 92 of the frequency synthesizer 9 to change the respective frequency-dividing ratio, thereby performing a frequency shift operation of the first intermediate frequency signal, and similarly, the second intermediate frequency signal. Is performed.

This will be described more specifically with reference to FIG. FIG. 3 shows an intermediate frequency stage extracted from FIG. The frequency of the RF signal is 175.04 to 249.984
MHz, the oscillation frequency of the reference frequency oscillator 1 is 8.96M
Hz, the frequency division ratio of the frequency divider 8 is 140 (the output frequency of the frequency divider 8 is 64 kHz), and the frequency division ratio of the frequency divider 10 is 56
0 (the frequency of the output of the frequency divider 10 is 16 kHz),
The oscillation frequency of the voltage controlled oscillator 71 is set to 213.632 to 2
89.216 MHz, and the oscillation frequency of the voltage controlled oscillator 91 is 35.488 to 36.192 MHz.

In the DAB broadcast receiver according to one embodiment of the present invention, the phase comparison frequency of the frequency synthesizer 7 for down-converting the RF signal to the first intermediate frequency signal is:
The operation is set such that the step value of the intermediate frequency shift is set, and the frequency is shifted by an integral multiple of the frequency step value. In this embodiment, the frequency step is 64 kHz, and five values before and after (5, 4,..., 1,-)
1, -2... -4, -5) .times.64 kHz. Since the receiving channel step frequency of 16 kHz, which is the standard of the transmission frequency grid of the DAB broadcasting, is set to 64 kHz, the dividing ratio of the divider 8 of the frequency synthesizer 9 is 1 / the dividing ratio of the divider 10 of the frequency synthesizer 9. It is set to 4.

The center frequency of the first intermediate frequency signal is
In the frequency synthesizer 9 for down-converting to the center frequency of the intermediate frequency signal, the setting is such that the frequency of the first intermediate frequency signal is shifted and the original frequency of the second intermediate frequency signal can be returned.

When the frequency shift of the intermediate frequency is performed, the value of the frequency division ratio N1 of the frequency divider 72 corresponding to the desired reception frequency in the two frequency synthesizers 7 and 9 and the value of the frequency divider 92 corresponding to the desired reception frequency. The relationship between the value of the frequency division ratio N2, the frequency shift amount of the first intermediate frequency signal, and the frequency shift amount of the second intermediate frequency signal is as shown in FIG. 64 kHz × d corresponding to the frequency shift amount added to the frequency by the circumferential ratio N1
N1 is the frequency shift amount added to the first intermediate frequency signal. The lower stage dN2 corresponds to the frequency shift amount added to the frequency by the frequency division ratio N2 of the frequency divider 92, and is 16 kHz ×
dN2 is the frequency shift amount added to the second intermediate frequency signal. Here, the range of the shift value (dN1) of the division ratio N1 is ± 5, and the range of the shift value (dN2) of the division ratio N2 is ± 22.

For example, if the frequency of the first intermediate frequency signal is +19
To shift the frequency by 2 kHz, the frequency of the frequency divider 72 is set to N1 + 3 (3 = dN1), and the frequency of the frequency divider 92 is set to N2 + 3 × 4 (3 × 4 = dN2). The frequency of the signal becomes the original center frequency. Here, the dividing ratio is N1 + 3 (3 = dN1), N2 + 3 × 4 (3 × 4
= DN2) and the signs of dN1 and dN2 are the same because the frequency synthesizer 7 is set to upper heterodyne and the frequency synthesizer 9 is set to downheterodyne. This example is 192 kHz.
The frequency shift of z is actually an example in the case where an adjacent wave exists above the occupied band of the desired signal as shown in FIG.

Here, even if the frequency of the first intermediate frequency signal does not change due to the dividing ratio N1, the fluctuation of the oscillation frequency of the reference frequency oscillator 1 can be compensated by the dividing ratio dN2 of the frequency synthesizer 9. .

The power level data for each of the 2048 FFT points calculated by the digital signal processor 25 is sent to the system controller 31.

Next, the system controller 31 will be described. The system controller 31 is composed of a computer. The system controller 31 has a register 32 for storing the calculated value of the total power level data including the interference part in the lower frequency band, and a register 33 for storing the calculated value of the total power level data including the interference part in the upper frequency band. The storage unit 34 in which the calculated value of the total power level when there is no interference is stored, the calculated value of the total power level data stored in the registers 32 and 33 and the calculated value of the total power level data stored in the storage unit 34 Comparator 35 to be compared, frequency division value signals dN1 and dN2 based on the comparison output of comparator 35 are preset, and frequency division ratio storage from which frequency division value signals dN1 and dN2 are read out based on the output of comparator 35. Registers 36-38,
OR gates 39 and 40 for transmitting the read frequency division value signals dN1 and dN2 to the frequency dividers 72 and 92, respectively, are provided functionally.

Here, the registers 32 and 33 and the storage unit 34
The comparator 35 corresponds to detecting means for detecting the presence or absence of the high-frequency side adjacent interference wave and the low-frequency side adjacent interference wave and the degree of adjacentness of the adjacent interference wave.
38, the OR gate 39, and the frequency divider 72 shift the center frequency of the first intermediate frequency signal at intervals of an integral multiple of the reception channel step frequency based on the degree of adjacency of the adjacent interference wave detected by the detection means. The comparator 35 and the frequency division ratio storage register 3 correspond to the intermediate frequency shift means.
6 to 38, the OR gate 40 and the frequency divider 92 shift the center frequency of the frequency-shifted first intermediate frequency signal at the reception channel step frequency interval, and perform a second shift based on the center frequency of the first intermediate frequency signal before the frequency shift. This corresponds to a second intermediate frequency shift means for returning to the center frequency of the intermediate frequency signal.

Here, dN is stored in the frequency division ratio storage register 36.
1 = 0, dN2 = −2, −1, 0, 1, 2 are set in the dividing ratio storage register 37, and dN1 = α (α is a positive integer of 0, 1,..., 5) , DN2 = 4α + (− 2,
−1, 0, 1, 2) are stored in the frequency division ratio storage register 38, dN1 = −α, dN2 = −4α + (− 2,
-1, 0, 1, 2) are set.

The system controller 3 receiving the power level data for each of the 2048 FFT points calculated by the digital signal processor 25
1, the calculated value of the total power based on the power level data of the low-frequency 768 carrier in the band of the DAB signal and the power level data of 256 points at 769 kHz to 1024 kHz outside the low-frequency band of the DAB signal. ((Pa) is obtained and temporarily stored in the register 32, and the power level of the 768 carrier on the high frequency side within the band of the DAB signal and the 769 kHz on the high frequency side outside the band of the DAB signal.
Calculated value (Pb) of total power based on power level data at 256 points at z to 1024 kHz
Is temporarily stored in the register 33.

On the other hand, when there is no interference signal outside the band of the DAB signal, the calculated value of the total power based on the power level of the low-side 768 carrier in the band of the DAB signal or the power level of the high-side 768 carrier One of the calculated total power values (Pno) is stored in the storage device 34 in advance. The comparator 35 compares the storage value (Pno) of the storage unit 34 with the storage value (Pa) of the register 32 and the storage value (Pb) of the register 33.

As shown in the flowchart of FIG. 6, the comparator 35 checks whether Pno = Pa and Pb (step S1). In step S1, Pno =
Pa and Pb (when the stored value (P
no), when it is determined that the storage value (Pa) of the register 32 and the storage value (Pb) of the register 33 are equal)
Is the case where the interfering wave and the adjacent reception wave are neither on the high frequency side nor on the low frequency side. After step S1, the contents stored in the frequency division ratio storage register 36 are read out (step S3).
dN1 = 0 is sent to the frequency divider 72 via the OR gate 39, and dN2 = (− 2, −1, 0, 1, 2) is sent to the frequency divider 92 via the OR gate 40 (step S).
3).

Therefore, in this case, since dN1 = 0, the frequency division ratio N1 of the frequency divider 72 is a value corresponding to the reception frequency, the frequency shift of the first intermediate frequency signal is not performed, and the second intermediate frequency signal is not shifted. Is performed according to dN2. After a predetermined period of time has elapsed after step S3, the process is executed from step S1 (step S4).

In step S1, Pno = Pa, Pb
If not, it is checked whether Pno <Pa (step S5). In step S5,
When it is determined that Pno <Pa (when it is determined that the storage value (Pa) of the register 32 is larger than the storage value (Pno) of the storage device 34), the interfering wave and the adjacent reception wave are shifted to the lower frequency side. If it exists, the storage content of the frequency division ratio storage register 37 is read out after step S5 (step S6), dN1 = + α is sent to the frequency divider 72 via the OR gate 39, and dN2 = 4α + (− 2, −1,
0, 1, 2) is sent to the frequency divider 92 via the OR gate 40 (step S3).

Therefore, in this case, since dN1 = + α, the frequency division ratio N1 of the frequency divider 72 is shifted by + α from the value corresponding to the reception frequency, and the first intermediate frequency is + α × 64 kHz.
The frequency shift of the second intermediate frequency signal is performed in accordance with dN2 = 4α + (− 2, −1, 0, 1, 2). After a predetermined period of time has elapsed after step S3, the process is executed from step S1 (step S4).

If it is determined in step S5 that Pno <Pa, then Pno <Pa following step S5.
It is checked whether it is Pb (step S7). When it is determined in step S7 that Pno <Pb (when it is determined that the storage value (Pb) of the register 33 is larger than the storage value (Pno) of the storage device 34), the interference wave and the adjacent reception wave are high. If it exists on the frequency side, the storage content of the frequency division ratio storage register 38 is read out after step S7 (step S6), and dN1 = −α is sent to the frequency divider 72 via the OR gate 39. And dN2 = -4
α + (− 2, −1, 0, 1, 2) is sent to the frequency divider 92 via the OR gate 40 (step S4).

Therefore, in this case, since dN1 = -α, the frequency dividing ratio N1 of the frequency divider 72 is shifted by -α from the value corresponding to the receiving frequency, and the first intermediate frequency is + α × 64 kHz.
The frequency shift of the second intermediate frequency signal is performed in accordance with dN2 = −4α + (− 2, −1, 0, 1, 2). After a predetermined period of time has elapsed after step S3, the process is executed from step S1 (step S4).

If it is determined in step S7 that Pno <Pb, step S7 is followed by step S7.
It is executed again from 1.

In the DAB broadcasting, the receiving frequency is 1
The frequency of the second intermediate frequency signal is always a fixed frequency (a multiple of 16 kHz) regardless of the reception frequency. this is,
This is because demodulation is performed by FFT, and the frequency of the second intermediate frequency signal cannot be demodulated unless it is always a fixed frequency that is a multiple of 16 kHz regardless of the reception frequency. Therefore, the first intermediate frequency is set to 64 kHz by dN1.
As a result of shifting in a direction of increasing or decreasing by a multiple of 1,... Or 5, in order to adjust the frequency of the second intermediate frequency signal to the fixed frequency described above, steps S2, S6,
In step S8, a value of -2, -1, 0, 1, or 2 is taken. Here, 64 kHz by dN1
Since a frequency shift of × α is performed, in order to cover the frequency shift and set a fixed second intermediate frequency, dN2 is −2,
The value may be -1, 0, 1, or 2. In other words, the value that dN2 should take depending on the reception frequency is −
It is determined to be one of 2, -1, 0, 1, and 2.

In the above description, for simplicity,
In step S6 and step S7, dN1 is simply described as α. However, when Pno ≠ Pa and Pb, step S1, step S5, step S6, step S3, step S4, step S1, step S1,
.. Is incremented from the value 1 to the maximum value 5 each time the operation is repeated continuously. Similarly, step S1, step S5, step S7, step S8,
Step S Step S3, Step S4, Step S
.Alpha. Is incremented from a value of 1 to a maximum value of 5 each time the step 1, step S5, step S7,.

Therefore, as schematically shown in FIG. 5, when Pno ≠ Pa, Pb, Pno-Pa, Pb
, Ie, as the total power difference increases, |
dN1 | increases to 1,...

As described above, the band-pass filter 1
2 is fixed, but the frequency of the first intermediate frequency signal is frequency-shifted to dN1 by the value, so that the band-pass filter 12 has the center frequency of the pass band substantially changed. And the interference wave is substantially eliminated. Further, regardless of the frequency shift of the first intermediate frequency signal frequency, the frequency of the second intermediate frequency signal is frequency shifted by dN2, and the second intermediate frequency becomes a fixed frequency regardless of the desired reception frequency. There is no hindrance to demodulation.

Further, since the center frequency of the pass band width of the band-pass filter 12 is shifted by the frequency shift of the intermediate frequency signal, not only the adjacent wave is filtered and attenuated, but also the signal of the desired desired signal is received. However, since the DAB modulation scheme performs strong redundancy and frequency interleaving, the minimum sensitivity due to the power loss of the multicarrier group of the desired wave to be received over a bandwidth of about 300 kHz as in the present embodiment. The deterioration is slight, and as an improvement in the interference (deterioration of the bit error rate) characteristic due to the adjacent wave, specifically, the power of the desired reception wave input to the first-stage A / D converter 22 of the DAB demodulation unit 21 is reduced. The power ratio of undesired waves and unwanted signals is greatly improved.

[0050]

As described above, according to the digital audio broadcasting receiver of the present invention, adjacent interference waves and unnecessary power are detected, and the pass band characteristic is controlled with respect to the detected value to thereby prevent interference. The effect of improving the characteristics can be obtained.

Further, according to the digital audio broadcast receiver of the present invention, the frequency divider shifts the frequency of the first intermediate frequency signal by varying the frequency division ratio of the programmable divider of the frequency synthesizer, thereby substantially eliminating the intermediate frequency filter. In addition, since the center frequency of the pass band is shifted, there is an effect that the circuit scale of the receiver does not increase.

According to the digital audio broadcast receiver of the present invention, the frequency of the first intermediate frequency signal is shifted by changing the frequency division ratio of the programmable divider of the first frequency synthesizer. Since the unnecessary power is calculated from the calculation result of the FFT point that is not used for the detection, the effect that the interference wave can be easily detected is also obtained.

According to the digital audio broadcast receiver of the present invention, the frequency of the second intermediate frequency is changed regardless of the frequency shift of the first intermediate frequency signal by varying the frequency division ratio of the second frequency synthesizer programmable divider. Since the frequency is returned to the predetermined fixed frequency regardless of the change of the reception frequency, the effect that the FFT demodulation is not hindered is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital audio broadcast receiver according to one embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining an operation of the digital audio broadcast receiver according to the embodiment of the present invention;

FIG. 3 is a block diagram showing a configuration of an intermediate frequency stage in the digital audio broadcast receiver according to one embodiment of the present invention.

FIG. 4 is an explanatory diagram for explaining a frequency shift in the digital audio broadcast receiver according to the embodiment of the present invention;

FIG. 5 is an explanatory diagram showing the relationship between the power of the interfering wave and the frequency division ratio dN1 in the digital audio broadcast receiver according to one embodiment of the present invention.

FIG. 6 is a flowchart for explaining the operation of the digital audio broadcast receiver according to the embodiment of the present invention;

FIG. 7 is a block diagram showing a configuration of a conventional digital audio broadcast receiver.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Reference frequency oscillator 5 and 15 Mixer 7 and 9 Frequency synthesizer 8 and 10 Frequency divider as prescaler 12 Bandpass filter 21 DAB demodulation unit 22 A / D converter 23 Quadrature detector 24 FFT operation, delay detection circuit 25 Digital signal Processor 31 System controller 32 and 33 Register 34 Memory 35 Comparator 36, 37 and 38 Frequency division ratio storage register 71 and 91 Voltage controlled oscillator 72 and 92 Frequency divider 73 and 93 Low pass filter 74 and 94 as a programmable divider Phase comparison vessel

Claims (3)

(57) [Claims] 1. A digital audio broadcast receiver in which demodulation processing is performed by FFT processing with the number of FFT points exceeding the number of carriers.
Calculate the power level data of the low frequency side FFT point
Detecting means for detecting the presence and absence of the high-frequency side adjacent interference wave and the low-frequency side adjacent interference wave based on the power level data, and detecting the degree of adjacentness of the adjacent interference wave detected by the detection means. First intermediate frequency shift means for shifting the center frequency of the first intermediate frequency signal by an integer multiple of the reception channel step frequency, and shifting the center frequency of the frequency-shifted first intermediate frequency signal by the reception channel step frequency interval A second intermediate frequency shift means for returning to the center frequency of the second intermediate frequency signal based on the center frequency of the first intermediate frequency signal before the frequency shift, and transmitting the second intermediate frequency signal to the demodulation means. A digital audio broadcast receiver, characterized in that: 2. The digital audio broadcast receiver according to claim 1, wherein said first intermediate frequency shift means includes a receiving RF signal.
Frequency at which the signal is converted to an intermediate frequency signal of the first intermediate frequency
A method for sequentially updating the frequency division ratio of the variable frequency divider of the synthesizer
Digital audio broadcast receiver characterized by a stage . 3. The digital audio broadcast receiver according to claim 1, wherein said second intermediate frequency shift means comprises a first intermediate frequency shift means.
To convert the frequency signal into an intermediate frequency signal of the second intermediate frequency.
The frequency division ratio of the variable frequency divider of the wave number synthesizer is updated sequentially.
Digital audio broadcast receiver, which is a that means.