JP3324446B2 - Mounting structure and mounting method of chip with bump - Google Patents

Mounting structure and mounting method of chip with bump

Info

Publication number
JP3324446B2
JP3324446B2 JP13208097A JP13208097A JP3324446B2 JP 3324446 B2 JP3324446 B2 JP 3324446B2 JP 13208097 A JP13208097 A JP 13208097A JP 13208097 A JP13208097 A JP 13208097A JP 3324446 B2 JP3324446 B2 JP 3324446B2
Authority
JP
Japan
Prior art keywords
oxide film
chip
copper bump
solder
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP13208097A
Other languages
Japanese (ja)
Other versions
JPH10321671A (en
Inventor
秀喜 永福
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP13208097A priority Critical patent/JP3324446B2/en
Publication of JPH10321671A publication Critical patent/JPH10321671A/en
Application granted granted Critical
Publication of JP3324446B2 publication Critical patent/JP3324446B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1182Applying permanent coating, e.g. in-situ coating
    • H01L2224/11822Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、バンプ付きチップ
を基板に実装するバンプ付きチップの実装構造および実
装方法に関するものである。
[0001] 1. Field of the Invention [0002] The present invention relates to a bumped chip mounting structure and a mounting method for mounting a bumped chip on a substrate.

【0002】[0002]

【従来の技術】チップの電極を基板の回路パターンの電
極に半田付けするために、予めチップの電極上に銅など
の金属によりバンプを形成し、バンプ付きチップとする
方法が知られている。電極の金属としてはアルミニウム
が多用されてる。そしてバンプ付きチップを半田付けす
るに際しては、基板の電極上にプリコートされた半田の
上にバンプを搭載し、その後半田を加熱溶融させること
によってバンプと電極とを半田付けする。
2. Description of the Related Art In order to solder an electrode of a chip to an electrode of a circuit pattern on a substrate, a method of forming a bump with a metal such as copper on the electrode of the chip in advance to obtain a chip with a bump is known. Aluminum is often used as a metal for the electrodes. When soldering the chip with bumps, the bumps are mounted on the solder pre-coated on the electrodes of the substrate, and then the solder is heated and melted to solder the bumps and the electrodes.

【0003】以下、従来のバンプ付きチップの半田付け
部について図面を参照して説明する。図19は従来のバ
ンプ付きチップおよび基板の部分断面図である。図19
において、チップ1にはアルミ電極2が形成されてお
り、アルミ電極2上には銅バンプ3が形成されている。
この銅バンプ3を基板5の電極6上にプリコートされた
半田7上に搭載し、その後加熱して半田7を溶融させ
る。すると半田7は表面張力により半田ぬれ性のよい銅
バンプ3の表面に沿ってはい上がり銅バンプ3全体の表
面を覆い、半田7の先端はアルミ電極2の表面まで到達
する。
Hereinafter, a soldering portion of a conventional bumped chip will be described with reference to the drawings. FIG. 19 is a partial sectional view of a conventional chip with a bump and a substrate. FIG.
In FIG. 1, an aluminum electrode 2 is formed on a chip 1, and a copper bump 3 is formed on the aluminum electrode 2.
The copper bump 3 is mounted on the solder 7 pre-coated on the electrode 6 of the substrate 5 and then heated to melt the solder 7. Then, the solder 7 rises along the surface of the copper bump 3 having good solder wettability by the surface tension and covers the entire surface of the copper bump 3, and the tip of the solder 7 reaches the surface of the aluminum electrode 2.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、溶融し
た半田7がアルミ電極2の表面に接触すると、この接触
部分からアルミ電極2の素材であるアルミニウムが半田
中に溶出し、アルミ電極2は腐食を生じやすい。そして
アルミ電極2が腐食すると、チップの信頼性を損なう原
因となる。
However, when the molten solder 7 comes into contact with the surface of the aluminum electrode 2, aluminum as a material of the aluminum electrode 2 elutes into the solder from the contact portion, and the aluminum electrode 2 does not corrode. Easy to occur. When the aluminum electrode 2 is corroded, the reliability of the chip is impaired.

【0005】そこで本発明は、チップのアルミ電極が半
田によって腐食されないバンプ付きチップの実装構造お
よび実装方法を提供することを目的とする。
Accordingly, an object of the present invention is to provide a mounting structure and a mounting method of a chip with bumps in which aluminum electrodes of the chip are not corroded by solder.

【0006】[0006]

【課題を解決するための手段】請求項1記載の発明は、
チップのアルミ電極上にワイヤボンディングにより銅バ
ンプを形成し、この銅バンプを基板の電極に半田付けし
て成るバンプ付きチップの実装構造であって、前記銅バ
ンプの表面に生じた酸化膜のうち先端部の酸化膜を除去
し、酸化膜の除去部を基板の電極に半田付けするように
した。
According to the first aspect of the present invention,
A copper bump is formed on an aluminum electrode of the chip by wire bonding, and the copper bump is soldered to an electrode of a substrate. The oxide film at the tip was removed, and the removed portion of the oxide film was soldered to the electrode of the substrate.

【0007】請求項2記載のバンプ付きチップの実装方
法は、チップのアルミ電極上にワイヤボンディングによ
り銅バンプを形成する工程と、この銅バンプの表面に生
じた酸化膜のうち先端部の酸化膜を除去する工程と、酸
化膜の除去部を基板の電極に半田付けする工程と、を含
む。
According to a second aspect of the present invention, there is provided a method of mounting a chip with bumps, the step of forming a copper bump on an aluminum electrode of the chip by wire bonding, and the step of forming an oxide film at the tip of an oxide film formed on the surface of the copper bump. And a step of soldering the removed portion of the oxide film to the electrode of the substrate.

【0008】請求項3記載のバンプ付きチップの実装方
法は、請求項2記載のバンプ付きチップの実装方法であ
って、前記銅バンプの先端部の酸化膜を除去する工程
が、プラズマエッチングにより銅バンプの上面に対して
上方から電子やイオンを衝突させて、酸化膜をエッチン
グして除去するようにした。
According to a third aspect of the present invention, in the method of mounting a chip with bumps according to the second aspect, the step of removing the oxide film at the tip of the copper bump is performed by plasma etching. The oxide film is removed by etching with an electron or ion bombarding the upper surface of the bump from above.

【0009】請求項4記載のバンプ付きチップの実装方
法は、請求項2記載のバンプ付きチップの実装方法であ
って、前記銅バンプの先端部の酸化膜を除去する工程
が、銅バンプの先端部をフラックスに浸けて酸化膜を除
去するようにした。
According to a fourth aspect of the present invention, in the method of mounting a chip with bumps according to the second aspect of the present invention, the step of removing the oxide film at the tip of the copper bump comprises removing the tip of the copper bump. The portion was immersed in a flux to remove the oxide film.

【0010】請求項5記載のバンプ付きチップの実装方
法は、請求項2記載のバンプ付きチップの実装方法であ
って、前記銅バンプの先端部の酸化膜を除去する工程
が、銅バンプの先端部を予め基板の電極上に塗布された
クリーム半田に埋没させて、クリーム半田中のフラック
スにより酸化膜を除去するようにした。
According to a fifth aspect of the present invention, there is provided a method of mounting a chip with bumps according to the second aspect, wherein the step of removing the oxide film at the tip of the copper bump comprises removing the tip of the copper bump. The portion was buried in cream solder previously applied to the electrodes of the substrate, and the oxide film was removed by the flux in the cream solder.

【0011】請求項6記載のバンプ付きチップの実装方
法は、請求項2記載のバンプ付きチップの実装方法であ
って、前記銅バンプの先端部の酸化膜を除去する工程
が、銅バンプの先端部を半田槽の溶融半田中に浸けて振
動発生器により溶融半田と銅バンプを相対的に振動さ
せ、この振動により酸化膜を除去するようにした。
According to a sixth aspect of the present invention, in the method of mounting a chip with a bump according to the second aspect, the step of removing the oxide film at the tip of the copper bump is performed by removing the tip of the copper bump. The part was immersed in the molten solder in the solder bath, and the molten solder and the copper bump were relatively vibrated by a vibration generator, and the oxide film was removed by the vibration.

【0012】請求項7記載のバンプ付きチップの実装方
法は、請求項2記載のバンプ付きチップの実装方法であ
って、前記銅バンプの先端部を基板の電極上に半田付け
する工程が、先端部に半田を付着させた銅バンプを保持
手段により保持して基板の電極上に押圧し、振動発生器
により銅バンプを振動させて半田付けするようにした。
According to a seventh aspect of the present invention, in the method of mounting a chip with bumps according to the second aspect, the step of soldering a tip of the copper bump on an electrode of a substrate is performed. The copper bumps with the solder adhered to the portions were held by holding means and pressed onto the electrodes of the substrate, and the copper bumps were vibrated by a vibration generator and soldered.

【0013】[0013]

【発明の実施の形態】各請求項記載の発明によれば、銅
バンプの表面に生じた酸化膜のうち、先端部の酸化膜を
除去して酸化膜の除去部を基板の電極に半田付けするこ
とにより、半田ぬれ性が悪い酸化膜が残留した銅バンプ
の基部には半田が付着しないので、チップのアルミ電極
に半田が接触することがなく、したがってアルミ電極の
半田による腐食が発生しない。
According to the invention as set forth in the claims, of the oxide film formed on the surface of the copper bump, the oxide film at the tip is removed and the removed portion of the oxide film is soldered to the electrode of the substrate. By doing so, the solder does not adhere to the base of the copper bump on which the oxide film having poor solder wettability remains, so that the solder does not come into contact with the aluminum electrode of the chip, and therefore the corrosion of the aluminum electrode by the solder does not occur.

【0014】(実施の形態1)図1は、本発明の実施の
形態1のプラズマエッチング装置の断面図、図2、図3
は同銅バンプ付きチップの部分断面図、図4、図5は同
銅バンプ付きチップおよび基板の部分断面図である。図
1において、プラズマクエッチング装置の真空チャンバ
11の中には電極12が設けられており、電極12の上
方には接地電極13が設けられ、接地部15に接続され
ている。電極12は高周波電源14に接続されている。
(Embodiment 1) FIG. 1 is a sectional view of a plasma etching apparatus according to Embodiment 1 of the present invention, and FIGS.
Is a partial sectional view of the chip with copper bumps, and FIGS. 4 and 5 are partial sectional views of the chip with copper bumps and the substrate. In FIG. 1, an electrode 12 is provided in a vacuum chamber 11 of a plasma etching apparatus, and a ground electrode 13 is provided above the electrode 12 and is connected to a ground unit 15. The electrode 12 is connected to a high frequency power supply 14.

【0015】電極12上にはチップ1が銅バンプ3を上
向きにして載置されている。銅バンプ3はワイヤボンデ
ィングによりアルミ電極2上に形成されたものである。
銅バンプ3の表面には酸化膜3aが生じている。酸化膜
3aはワイヤボンディング後、銅バンプ3が空気に触れ
ることにより自然に生じるものであるが、本発明は銅バ
ンプ3の表面に生じた酸化膜3aアルミ電極2のガード
手段として活用するものであり、したがって150°C
程度の高温雰囲気に銅バンプ3を置くことにより、酸化
膜3aを短時間で積極的に生じさせることが望ましい。
The chip 1 is mounted on the electrode 12 with the copper bump 3 facing upward. The copper bumps 3 are formed on the aluminum electrodes 2 by wire bonding.
An oxide film 3a is formed on the surface of the copper bump 3. Although the oxide film 3a is naturally generated by the copper bump 3 coming into contact with air after wire bonding, the present invention is used as a guard means for the oxide film 3a formed on the surface of the copper bump 3 and the aluminum electrode 2. Yes, so 150 ° C
It is desirable that the oxide film 3a is positively generated in a short time by placing the copper bumps 3 in a high temperature atmosphere of a certain degree.

【0016】このプラズマエッチング装置は、銅バンプ
3の表面の酸化膜3aを部分的に除去するためのもので
あり、次に動作を説明する。電極12上にチップ1を載
置した状態で真空チャンバ11内を減圧し、次いで真空
チャンバ11内にアルゴンガス等のプラズマ発生用ガス
を導入し、電極12に高周波電圧を印加することにより
真空チャンバ11内にはプラズマが発生する。その結
果、図2に示すように、銅バンプ3の表面にはプラズマ
によって発生した電子やイオン16が衝突し、電子やイ
オン16のエッチング作用により銅バンプ3の表面の酸
化膜3aが除去される。
This plasma etching apparatus is for partially removing the oxide film 3a on the surface of the copper bump 3, and its operation will be described below. The vacuum chamber 11 is depressurized while the chip 1 is mounted on the electrode 12, and then a plasma generating gas such as argon gas is introduced into the vacuum chamber 11, and a high-frequency voltage is applied to the electrode 12 to thereby form a vacuum chamber. Plasma is generated in 11. As a result, as shown in FIG. 2, electrons and ions 16 generated by the plasma collide with the surface of the copper bump 3, and the oxide film 3 a on the surface of the copper bump 3 is removed by the etching action of the electrons and ions 16. .

【0017】図3は、プラズマエッチング後の銅バンプ
3の状態を示している。銅バンプ3は略半球状をしてい
るため、先端部Aには電子やイオン16が衝突しやす
く、また衝突の際の入射角が大きいため、エッチング作
用が大きい。その結果先端部Aの酸化膜3aは除去され
て除去部Aとなる。これに対して電極2に近接した基部
Bでは酸化膜3aの表面に衝突する電子やイオン16の
入射角が小さいためエッチング作用は小さく、したがっ
てこの部分の酸化膜3aは大部分が除去されずプラズマ
エッチング後も残留する。
FIG. 3 shows a state of the copper bump 3 after the plasma etching. Since the copper bump 3 has a substantially hemispherical shape, electrons and ions 16 are likely to collide with the tip A, and the angle of incidence at the time of collision is large, so that the etching action is large. As a result, the oxide film 3a at the tip A is removed to form a removed portion A. On the other hand, in the base portion B close to the electrode 2, the etching action is small because the incident angle of the electrons or ions 16 colliding with the surface of the oxide film 3a is small, and therefore, the oxide film 3a in this portion is not largely removed and plasma It remains after etching.

【0018】次に、図4に示すように、酸化膜3aの除
去部Aが形成されたチップ1を半田が予めプリコートさ
れた基板25の電極26上に搭載する。その後基板25
はリフロー炉に送られ、加熱される。その結果半田7は
溶融するが、酸化膜3aが除去された除去部Aは半田ぬ
れ性がよいため、図5に示すように溶融した半田7が銅
バンプ3の表面に沿って表面張力によりはい上がり、除
去部Aの表面を覆う。しかし半田ぬれ性が悪い酸化膜3
aが残留している基部Bには半田7は付着しないため、
半田7はアルミ電極2の表面には接触せず、したがって
アルミ電極2は半田7によって腐食されることがない。
Next, as shown in FIG. 4, the chip 1 on which the removed portion A of the oxide film 3a is formed is mounted on the electrode 26 of the substrate 25 on which solder is precoated. Then the substrate 25
Is sent to a reflow furnace and heated. As a result, the solder 7 is melted, but the removed portion A from which the oxide film 3a has been removed has good solder wettability. Therefore, the molten solder 7 is applied along the surface of the copper bump 3 due to surface tension as shown in FIG. Ascends and covers the surface of the removal portion A. However, oxide film 3 with poor solder wettability
Since the solder 7 does not adhere to the base B where a remains,
The solder 7 does not contact the surface of the aluminum electrode 2, so that the aluminum electrode 2 is not corroded by the solder 7.

【0019】(実施の形態2)図6は本発明の実施の形
態2のフラックス塗布部の断面図、図7、図8は同銅バ
ンプ付きチップおよび基板の部分断面図である。上記実
施の形態1は、銅バンプ3の酸化膜3aを除去するため
にプラズマエッチングを用いているが、本実施の形態2
では、銅バンプ3の先端部Aをフラックスに浸けること
によって酸化膜3aを除去し、除去部を形成するもので
ある。
(Embodiment 2) FIG. 6 is a cross-sectional view of a flux application portion according to Embodiment 2 of the present invention, and FIGS. 7 and 8 are partial cross-sectional views of the chip and the substrate with copper bumps. In the first embodiment, the plasma etching is used to remove the oxide film 3a of the copper bump 3, but in the second embodiment,
In this method, the tip portion A of the copper bump 3 is immersed in a flux to remove the oxide film 3a, thereby forming a removed portion.

【0020】図6において、保持ヘッド30の下端部に
はチップ1が真空吸着して保持されている。チップ1お
よび銅バンプ3については、実施の形態1と同じであ
る。31は薄型の容器から成るフラックス塗布部であ
り、フラックス33が貯溜されている。図6に示すよう
に、保持ヘッド30を下降させてチップ1の銅バンプ3
の先端部Aをフラックス33中に浸す。このとき、銅バ
ンプ3の基部Bにはフラックス33が塗布されないよう
に保持ヘッド30の昇降ストロークが制御される。この
結果、銅バンプ3の表面の酸化膜3aはフラックス33
に浸された先端部Aのみが除去される。このとき、フラ
ックス塗布部31内のフラックス33の深さを先端部A
の高さと等しくなるように設定しておき、銅バンプ3の
頂部をフラックス塗布部31の底面に当接させることに
より、先端部Aのみにフラックス33を塗布するように
してもよい。
In FIG. 6, a chip 1 is held at the lower end of the holding head 30 by vacuum suction. The chip 1 and the copper bump 3 are the same as in the first embodiment. Reference numeral 31 denotes a flux application unit formed of a thin container, in which a flux 33 is stored. As shown in FIG. 6, the holding head 30 is lowered to
Is immersed in the flux 33. At this time, the vertical stroke of the holding head 30 is controlled so that the flux 33 is not applied to the base B of the copper bump 3. As a result, the oxide film 3a on the surface of the copper bump 3 becomes flux 33
Only the tip A immersed in is removed. At this time, the depth of the flux 33 in the flux application section 31 is
The flux 33 may be applied only to the tip A by setting the top of the copper bump 3 to contact the bottom of the flux application section 31.

【0021】次に、図7に示すように保持ヘッド30を
移動させ、先端部Aにフラックス33が塗布され、この
範囲の酸化膜3aが除去された銅バンプ3を、半田7が
プリコートされたアルミ電極2上に位置合わせする。次
いで、図8に示すように、保持ヘッド30を下降させ、
銅バンプ3を半田7上に搭載する。この後基板25はリ
フロー炉へ送られ、加熱されて半田付けが行われる。こ
れ以降については実施の形態1と同様である。
Next, as shown in FIG. 7, the holding head 30 was moved, the flux 33 was applied to the tip A, and the copper bump 3 from which the oxide film 3a was removed was pre-coated with the solder 7. It is positioned on the aluminum electrode 2. Next, as shown in FIG. 8, the holding head 30 is lowered,
The copper bump 3 is mounted on the solder 7. Thereafter, the substrate 25 is sent to a reflow furnace, where it is heated and soldered. Subsequent steps are the same as in the first embodiment.

【0022】(実施の形態3)次に、本発明の実施の形
態3を図面を参照して説明する。図9、図10は本発明
の実施の形態3の銅バンプ付きチップおよび基板の部分
断面図である。チップ1および銅バンプ3は実施の形態
1と同じであり、またチップ1を保持する保持ヘッド3
0は省略している。図9において、基板25の電極26
上にはクリーム半田27が塗布されている。クリーム半
田27は半田の粒子とフラックスの成分を含んだもので
ある。まず、保持ヘッド30を移動させて電極26の上
方に保持ヘッド30に保持されたチップ1の銅バンプ3
を位置合わせする。
(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to the drawings. 9 and 10 are partial sectional views of a chip and a substrate with copper bumps according to Embodiment 3 of the present invention. The chip 1 and the copper bumps 3 are the same as in the first embodiment, and a holding head 3 for holding the chip 1
0 is omitted. In FIG. 9, the electrode 26 of the substrate 25
A cream solder 27 is applied on the top. The cream solder 27 contains solder particles and flux components. First, the holding head 30 is moved so that the copper bumps 3 of the chip 1 held by the holding head 30 are located above the electrodes 26.
Align.

【0023】次に、図10に示すように、保持ヘッド3
0を下降させて銅バンプ3の先端部Aをクリーム半田2
7に埋没させる。この時銅バンプ3の基部Bはクリーム
半田27に埋没しないように保持ヘッド30の昇降スト
ロークが制御される。次いで、基板25はこの状態でリ
フロー炉に送られ、加熱される。これにより、銅バンプ
3の表面のクリーム半田27に埋没した先端部Aの酸化
膜3aは、クリーム半田27中のフラックス成分により
除去される。この結果、前記実施の形態1と同様に銅バ
ンプ3が基板25の電極26に半田付けされる。
Next, as shown in FIG.
0 and lower the tip A of the copper bump 3 with the cream solder 2
7 buried. At this time, the lifting stroke of the holding head 30 is controlled so that the base B of the copper bump 3 is not buried in the cream solder 27. Next, the substrate 25 is sent to a reflow furnace in this state and heated. As a result, the oxide film 3 a at the tip end A buried in the cream solder 27 on the surface of the copper bump 3 is removed by the flux component in the cream solder 27. As a result, the copper bumps 3 are soldered to the electrodes 26 on the substrate 25 as in the first embodiment.

【0024】上記説明のように、本実施の形態3では、
クリーム半田27中に銅バンプ3の先端部Aを埋没させ
ることにより、クリーム半田27中のフラックスにより
先端部Aの酸化膜3aを除去するものである。
As described above, in the third embodiment,
By embedding the tip A of the copper bump 3 in the cream solder 27, the oxide film 3a at the tip A is removed by the flux in the cream solder 27.

【0025】(実施の形態4)次に、本発明の実施の形
態4を図面を参照して説明する。図11は本発明の実施
の形態4の半田槽の断面図、図12、図13は同銅バン
プ付きチップの部分断面図、図14、図15は同銅バン
プ付きチップおよび基板の部分断面図である。
(Embodiment 4) Next, Embodiment 4 of the present invention will be described with reference to the drawings. FIG. 11 is a sectional view of a solder bath according to a fourth embodiment of the present invention, FIGS. 12 and 13 are partial sectional views of the chip with copper bumps, and FIGS. 14 and 15 are partial sectional views of the chip with copper bumps and the substrate. It is.

【0026】図11において、半田槽40の内部には溶
融半田37が貯溜されている。半田槽30にはヒータ4
3が備えられており、溶融半田37の温度を一定の温度
範囲内に維持している。半田槽40には振動発生器42
が備えられており、振動発生器42を駆動することによ
り、溶融半田37に振動を伝達する。この振動の種類と
しては、好ましくは振動周波数が超音波範囲のものを用
いる。なお、保持ヘッド30、チップ1および銅バンプ
3は実施の形態1と同じである。
In FIG. 11, molten solder 37 is stored in a solder tank 40. The heater 4 is provided in the solder tank 30.
3 for maintaining the temperature of the molten solder 37 within a certain temperature range. A vibration generator 42 is provided in the solder tank 40.
The vibration is transmitted to the molten solder 37 by driving the vibration generator 42. As the type of the vibration, one having a vibration frequency in an ultrasonic range is preferably used. The holding head 30, the chip 1, and the copper bumps 3 are the same as in the first embodiment.

【0027】図12は、保持ヘッド30を下降させて溶
融半田37中に銅バンプ3の先端部Aを浸けた状態を示
している。この時、基部Bは溶融半田37中に浸からな
いように保持ヘッド30の昇降ストロークが制御され
る。この状態で振動発生器42を駆動すると、溶融半田
37中に振動が伝達され、溶融半田37は銅バンプ3に
対して相対的に振動する。この振動の機械的作用により
溶融半田37と接触している酸化膜3aは破壊されて銅
バンプ3の表面から除去される。即ち、先端部Aの酸化
膜3aのみが除去される。
FIG. 12 shows a state in which the tip A of the copper bump 3 is immersed in the molten solder 37 by lowering the holding head 30. At this time, the lifting stroke of the holding head 30 is controlled so that the base B is not immersed in the molten solder 37. When the vibration generator 42 is driven in this state, the vibration is transmitted to the molten solder 37, and the molten solder 37 vibrates relatively to the copper bumps 3. The oxide film 3 a in contact with the molten solder 37 is broken by the mechanical action of the vibration and is removed from the surface of the copper bump 3. That is, only the oxide film 3a at the tip A is removed.

【0028】次いで、図13に示すように保持ヘッド3
0を上昇させる。すると酸化膜3aが除去されて半田ぬ
れ性がよい先端部Aには溶融半田37が略ボール状に付
着し、その後溶融半田37は固化する。このとき基部B
には酸化膜3aが除去されずに残留している。
Next, as shown in FIG.
Increase 0. Then, the oxide film 3a is removed, and the molten solder 37 adheres in a substantially ball shape to the tip A having good solder wettability, and thereafter the molten solder 37 is solidified. At this time, the base B
The oxide film 3a remains without being removed.

【0029】その後、図14に示すように、保持ヘッド
30を移動させ、銅バンプ3を基板25の電極26上に
位置あわせして搭載する。次いで基板25はリフロー炉
に送られて加熱される。その結果図15に示すように、
半田37は溶融し銅バンプ3は電極26に半田付けされ
る。このとき半田ぬれ性が悪い酸化膜3aのため基部B
には溶融半田37が到達せず、アルミ電極2は半田37
に接触することがない。
After that, as shown in FIG. 14, the holding head 30 is moved, and the copper bumps 3 are positioned and mounted on the electrodes 26 of the substrate 25. Next, the substrate 25 is sent to a reflow furnace and heated. As a result, as shown in FIG.
The solder 37 is melted and the copper bump 3 is soldered to the electrode 26. At this time, since the oxide film 3a having poor solder wettability, the base B
Does not reach the molten solder 37, and the aluminum electrode 2
Never touch.

【0030】上記のように、本実施の形態4では半田槽
40の溶融半田37中に銅バンプ3の先端部Aを浸け、
溶融半田37を振動させることにより、先端部Aの酸化
膜3aのみを除去するものである。
As described above, in the fourth embodiment, the tip A of the copper bump 3 is immersed in the molten solder 37 of the solder bath 40,
By vibrating the molten solder 37, only the oxide film 3a at the tip A is removed.

【0031】(実施の形態5)次に、本発明の実施の形
態5を図面を参照して説明する。図16は本発明の実施
の形態5の半田槽の断面図、図17、図18は同銅バン
プ付きチップおよび基板の部分断面図である。図26に
おいて、半田槽40には溶融半田37が貯留されてい
る。半田槽40にはヒータ43が備えられており、溶融
半田37の温度を一定の温度範囲内に維持している。保
持ヘッド30、チップ1および銅バンプ3は、保持ヘッ
ド30に振動発生器44が備えられている点を除いては
実施の形態4と同じである。
Embodiment 5 Next, Embodiment 5 of the present invention will be described with reference to the drawings. FIG. 16 is a sectional view of a solder bath according to the fifth embodiment of the present invention, and FIGS. 17 and 18 are partial sectional views of the chip with copper bumps and the substrate. In FIG. 26, a molten solder 37 is stored in a solder tank 40. The solder tank 40 is provided with a heater 43 to maintain the temperature of the molten solder 37 within a certain temperature range. The holding head 30, the chip 1, and the copper bumps 3 are the same as those of the fourth embodiment except that the holding head 30 is provided with a vibration generator 44.

【0032】図16に示すように、チップ1を保持した
保持ヘッド30を下降させて溶融半田37中に銅バンプ
3の先端部Aを浸ける。この時、基部Bが溶融半田37
中に浸からないように保持ヘッド30の昇降ストローク
が制御される。この状態で振動発生器44を駆動する
と、保持ヘッド30を介してチップ1に振動が伝達され
銅バンプ3は溶融半田37に対して相対的に振動する。
この振動の種類としては、好ましくは振動周波数が超音
波範囲のものを用いる。この振動の機械的作用により溶
融半田37と接触している酸化膜3aは破壊されて銅バ
ンプ3の表面から除去される。即ち、先端部Aの酸化膜
3aのみが除去される。
As shown in FIG. 16, the holding head 30 holding the chip 1 is lowered to immerse the tip A of the copper bump 3 in the molten solder 37. At this time, the base B is
The elevating stroke of the holding head 30 is controlled so as not to be immersed inside. When the vibration generator 44 is driven in this state, the vibration is transmitted to the chip 1 via the holding head 30, and the copper bump 3 vibrates relatively to the molten solder 37.
As the type of the vibration, one having a vibration frequency in an ultrasonic range is preferably used. The oxide film 3 a in contact with the molten solder 37 is broken by the mechanical action of the vibration and is removed from the surface of the copper bump 3. That is, only the oxide film 3a at the tip A is removed.

【0033】次いで、保持ヘッド30を上昇させると銅
バンプ3の酸化膜3aが除去されて半田ぬれ性がよい先
端部Aには溶融半田37が略ボール状に付着し、その後
付着した溶融半田37は固化する。
Next, when the holding head 30 is raised, the oxide film 3a of the copper bump 3 is removed, and the molten solder 37 adheres in a substantially ball shape to the tip A having good solder wettability. Solidifies.

【0034】その後、図17に示すように、保持ヘッド
30を移動させて銅バンプ3を基板25の電極26上に
位置あわせし、保持ヘッド30を下降させて銅バンプ3
に付着した半田37を電極26に着地させる。次いで保
持ヘッド30によって銅バンプ3を電極26に押圧しな
がら振動発生器44を駆動する。これにより半田37と
電極26の接触面は振動と押圧力により接合される。図
18はこのようにして銅バンプ3が電極26に半田付け
された状態を示している。このとき、酸化膜3aは既に
除去されているので、電極26の上面にフラックスを塗
布する必要がなく、したがって電極26がフラックスに
よって腐食されることがない。またアルミ電極2は半田
37に接触しないため、アルミ電極2が半田37によっ
て腐食することがない。
Thereafter, as shown in FIG. 17, the holding head 30 is moved to position the copper bump 3 on the electrode 26 of the substrate 25, and the holding head 30 is lowered to move the copper bump 3
The solder 37 attached to the electrode 26 lands on the electrode 26. Next, the vibration generator 44 is driven while the copper bump 3 is pressed against the electrode 26 by the holding head 30. Thereby, the contact surface between the solder 37 and the electrode 26 is joined by the vibration and the pressing force. FIG. 18 shows a state where the copper bumps 3 are soldered to the electrodes 26 in this manner. At this time, since the oxide film 3a has already been removed, there is no need to apply a flux to the upper surface of the electrode 26, and therefore, the electrode 26 is not corroded by the flux. Since the aluminum electrode 2 does not contact the solder 37, the aluminum electrode 2 is not corroded by the solder 37.

【0035】なお、振動発生器44を用いて振動と押圧
力により銅バンプ3を電極26に接合する方法は、本実
施の形態にに限らず実施の形態1〜4にも適用が可能で
ある。
The method of joining the copper bump 3 to the electrode 26 by using vibration and pressing force by using the vibration generator 44 is not limited to the present embodiment, but can be applied to the first to fourth embodiments. .

【0036】[0036]

【発明の効果】本発明によれば、銅バンプの表面に生じ
た酸化膜のうち、基部の酸化膜を溶融半田がアルミ電極
まで這い上がってアルミ電極を腐食させるのを防ぐガー
ド手段として残留させ、銅バンプの先端部の酸化膜のみ
を除去し、この酸化膜の除去部を基板の電極に半田付け
するようにしているので、半田ぬれ性が悪い酸化膜の表
面には半田が付着しないため、チップのアルミ電極に半
田が接触することがなく、したがってアルミ電極が半田
によって腐食することがない。また、酸化膜を除去する
方法として溶融半田と銅バンプを相対的に振動させる方
法を用いれば、フラックスを使用せずにチップを基板に
半田付けすることができるので、半田付け後にフラック
スが残留して基板の電極を腐食させることがない。
According to the present invention, of the oxide film formed on the surface of the copper bump, the base oxide film is left as a guard means for preventing the molten solder from creeping up to the aluminum electrode and corroding the aluminum electrode. Since only the oxide film at the tip of the copper bump is removed and the removed portion of the oxide film is soldered to the electrode of the substrate, the solder does not adhere to the surface of the oxide film having poor solder wettability. In addition, the solder does not come into contact with the aluminum electrode of the chip, so that the aluminum electrode is not corroded by the solder. In addition, if a method of relatively vibrating the molten solder and the copper bumps is used as a method of removing the oxide film, the chip can be soldered to the substrate without using a flux, so that the flux remains after the soldering. It does not corrode the electrodes of the substrate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態1のプラズマエッチング装
置の断面図
FIG. 1 is a sectional view of a plasma etching apparatus according to a first embodiment of the present invention.

【図2】本発明の実施の形態1の銅バンプ付きチップの
部分断面図
FIG. 2 is a partial cross-sectional view of the chip with a copper bump according to the first embodiment of the present invention.

【図3】本発明の実施の形態1の銅バンプ付きチップの
部分断面図
FIG. 3 is a partial cross-sectional view of the chip with a copper bump according to the first embodiment of the present invention.

【図4】本発明の実施の形態1の銅バンプ付きチップお
よび基板の部分断面図
FIG. 4 is a partial sectional view of a chip and a substrate with a copper bump according to the first embodiment of the present invention.

【図5】本発明の実施の形態1の銅バンプ付きチップお
よび基板の部分断面図
FIG. 5 is a partial cross-sectional view of the chip and the substrate with copper bumps according to the first embodiment of the present invention.

【図6】本発明の実施の形態2のフラックス塗布部の断
面図
FIG. 6 is a cross-sectional view of a flux application section according to a second embodiment of the present invention.

【図7】本発明の実施の形態2の銅バンプ付きチップお
よび基板の部分断面図
FIG. 7 is a partial cross-sectional view of a chip with a copper bump and a substrate according to a second embodiment of the present invention.

【図8】本発明の実施の形態2の銅バンプ付きチップお
よび基板の部分断面図
FIG. 8 is a partial sectional view of a chip and a substrate with copper bumps according to a second embodiment of the present invention.

【図9】本発明の実施の形態3の銅バンプ付きチップお
よび基板の部分断面図
FIG. 9 is a partial cross-sectional view of a chip with a copper bump and a substrate according to a third embodiment of the present invention.

【図10】本発明の実施の形態3の銅バンプ付きチップ
および基板の部分断面図
FIG. 10 is a partial cross-sectional view of a chip with a copper bump and a substrate according to a third embodiment of the present invention.

【図11】本発明の実施の形態4の半田槽の断面図FIG. 11 is a sectional view of a solder bath according to a fourth embodiment of the present invention.

【図12】本発明の実施の形態4の銅バンプ付きチップ
の部分断面図
FIG. 12 is a partial sectional view of a chip with a copper bump according to a fourth embodiment of the present invention.

【図13】本発明の実施の形態4の銅バンプ付きチップ
の部分断面図
FIG. 13 is a partial sectional view of a chip with a copper bump according to a fourth embodiment of the present invention.

【図14】本発明の実施の形態4の銅バンプ付きチップ
および基板の部分断面図
FIG. 14 is a partial sectional view of a chip and a substrate with copper bumps according to a fourth embodiment of the present invention.

【図15】本発明の実施の形態4の銅バンプ付きチップ
および基板の部分断面図
FIG. 15 is a partial cross-sectional view of a chip and a substrate with copper bumps according to a fourth embodiment of the present invention.

【図16】本発明の実施の形態5の半田槽の断面図FIG. 16 is a sectional view of a solder bath according to a fifth embodiment of the present invention.

【図17】本発明の実施の形態5の銅バンプ付きチップ
および基板の部分断面図
FIG. 17 is a partial sectional view of a chip and a substrate with copper bumps according to a fifth embodiment of the present invention.

【図18】本発明の実施の形態5の銅バンプ付きチップ
および基板の部分断面図
FIG. 18 is a partial sectional view of a chip and a substrate with copper bumps according to a fifth embodiment of the present invention.

【図19】従来のバンプ付きチップおよび基板の部分断
面図
FIG. 19 is a partial cross-sectional view of a conventional chip and substrate with bumps.

【符号の説明】[Explanation of symbols]

1 チップ 2 電極 3 銅バンプ 3a 酸化膜 5、25 基板 6、26 電極 7、27、37 半田 11 真空チャンバ 12 高周波電極 30 保持ヘッド 31 フラックス塗布部 33 フラックス 40 半田槽 42 振動発生器 DESCRIPTION OF SYMBOLS 1 Chip 2 electrode 3 Copper bump 3a Oxide film 5, 25 Substrate 6, 26 Electrode 7, 27, 37 Solder 11 Vacuum chamber 12 High frequency electrode 30 Holding head 31 Flux application part 33 Flux 40 Solder tank 42 Vibration generator

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 H01L 23/50 H05K 3/34 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/60 H01L 23/50 H05K 3/34

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】チップのアルミ電極上にワイヤボンディン
グにより銅バンプを形成し、この銅バンプを基板の電極
に半田付けして成るバンプ付きチップの実装構造であっ
て、前記銅バンプの表面に生じた酸化膜のうち先端部の
酸化膜を除去し、酸化膜の除去部を基板の電極に半田付
けすることを特徴とするバンプ付きチップの実装構造。
1. A mounting structure of a chip with bumps, wherein a copper bump is formed on an aluminum electrode of a chip by wire bonding, and the copper bump is soldered to an electrode of a substrate. A mounting structure for a chip with bumps, wherein an oxide film at a tip portion of the oxide film is removed, and the removed portion of the oxide film is soldered to an electrode of a substrate.
【請求項2】チップのアルミ電極上にワイヤボンディン
グにより銅バンプを形成する工程と、この銅バンプの表
面に生じた酸化膜のうち先端部の酸化膜を除去する工程
と、酸化膜の除去部を基板の電極に半田付けする工程
と、を含むことを特徴とするバンプ付きチップの実装方
法。
A step of forming a copper bump on the aluminum electrode of the chip by wire bonding, a step of removing an oxide film at a tip end of an oxide film formed on a surface of the copper bump, and a step of removing the oxide film. Soldering the substrate to an electrode of a substrate.
【請求項3】前記銅バンプの先端部の酸化膜を除去する
工程が、プラズマエッチングにより銅バンプの上面に対
して上方から電子やイオンを衝突させて、酸化膜をエッ
チングして除去することを特徴とする請求項2記載のバ
ンプ付きチップの実装方法。
3. The step of removing the oxide film at the tip end of the copper bump includes etching and removing the oxide film by colliding electrons or ions from above with the upper surface of the copper bump by plasma etching. The mounting method for a chip with bumps according to claim 2.
【請求項4】前記銅バンプの先端部の酸化膜を除去する
工程が、銅バンプの先端部をフラックスに浸けることに
より酸化膜を除去することを特徴とする請求項2記載の
バンプ付きチップの実装方法。
4. The bumped chip according to claim 2, wherein the step of removing the oxide film at the tip of the copper bump removes the oxide film by immersing the tip of the copper bump in a flux. Implementation method.
【請求項5】前記銅バンプの先端部の酸化膜を除去する
工程が、銅バンプの先端部を予め基板の電極上に塗布さ
れたクリーム半田に埋没させて、クリーム半田中のフラ
ックスにより酸化膜を除去することを特徴とする請求項
2記載のバンプ付きチップの実装方法。
5. The step of removing the oxide film at the tip of the copper bump includes burying the tip of the copper bump in cream solder previously coated on an electrode of a substrate, and using the flux in the cream solder. 3. The method for mounting a chip with bumps according to claim 2, wherein
【請求項6】前記銅バンプの先端部の酸化膜を除去する
工程が、銅バンプの先端部を半田槽の溶融半田中に浸け
て振動発生器により溶融半田と銅バンプを相対的に振動
させ、この振動により酸化膜を除去することを特徴とす
る請求項2記載のバンプ付きチップの実装方法。
6. The step of removing the oxide film at the tip of the copper bump includes immersing the tip of the copper bump in molten solder in a solder bath and causing the molten solder and the copper bump to vibrate relatively by a vibration generator. 3. The method according to claim 2, wherein the oxide film is removed by the vibration.
【請求項7】前記酸化膜の除去部を基板の電極に半田付
けする工程が、先端部に半田を付着させた銅バンプを保
持手段により保持して基板の電極上に押圧し、振動発生
器により銅バンプを振動させて半田付けすることを特徴
とする請求項2記載のバンプ付きチップの実装方法。
7. The step of soldering the removed portion of the oxide film to the electrode of the substrate, wherein the copper bump having the solder attached to the tip is held by holding means and pressed onto the electrode of the substrate, and a vibration generator is provided. The method for mounting a chip with bumps according to claim 2, wherein the copper bumps are vibrated and soldered.
JP13208097A 1997-05-22 1997-05-22 Mounting structure and mounting method of chip with bump Expired - Lifetime JP3324446B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13208097A JP3324446B2 (en) 1997-05-22 1997-05-22 Mounting structure and mounting method of chip with bump

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13208097A JP3324446B2 (en) 1997-05-22 1997-05-22 Mounting structure and mounting method of chip with bump

Publications (2)

Publication Number Publication Date
JPH10321671A JPH10321671A (en) 1998-12-04
JP3324446B2 true JP3324446B2 (en) 2002-09-17

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Country Link
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002289768A (en) 2000-07-17 2002-10-04 Rohm Co Ltd Semiconductor device and its manufacturing method
JP4661122B2 (en) * 2004-05-18 2011-03-30 ソニー株式会社 Component mounting wiring board and mounting method of components on wiring board
JP2006237280A (en) * 2005-02-25 2006-09-07 Sony Corp Semiconductor device and its manufacturing method
JP6282454B2 (en) * 2013-12-10 2018-02-21 新光電気工業株式会社 Manufacturing method of semiconductor package
JP6663649B2 (en) * 2015-04-14 2020-03-13 東レエンジニアリング株式会社 Semiconductor chip mounting method and semiconductor device

Also Published As

Publication number Publication date
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