JP3323352B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and is particularly suitable for a memory device such as a DRAM.

[0002]

2. Description of the Related Art FIGS. 25 and 26 are sectional views showing the structure of a conventional semiconductor device. Among them, FIG. 25 shows a structure of a DRAM having a cylindrical capacitor, while FIG. 26 shows a structure of a DRAM having a thick film capacitor.

In both figures, 1 is an isolation oxide film, 2 is a low concentration impurity layer, 3 is a high concentration impurity layer, 4 is a gate electrode, 5 is a silicon oxide film, 6 is a bit line, 7 Denotes a silicon oxide film (corresponding to a base insulating film), 8 denotes a substrate contact of a capacitor lower electrode, 9 denotes a cylindrical capacitor,
10 denotes a capacitor dielectric film, 11 denotes a cell plate (hereinafter simply referred to as CP) as a capacitor upper electrode,
2 is an Al wiring, 13 is a TiN film, 14 is a W plug, 15 is a barrier metal (Ti / TiN), 16 is an interlayer insulating film (reflow glass), 17 is another interlayer insulating film, 18 Is a thick film capacitor, 91 is a contact on the lower field (corresponding to another contact), 92 is a contact on the bit line (corresponding to another contact), 9
Reference numeral 3 denotes a lower electrode of the capacitor formed on the upper surface of the silicon oxide film 7 and in the opening thereof, and reference numeral 100 denotes a semiconductor substrate. In addition, the bit line 6 and the gate electrode 4
Are collectively referred to as a base pattern.

In another conventional technique disclosed in Japanese Patent Application Laid-Open No. 5-14889, a dummy step portion is provided in a CP contact portion, and a deep CP contact is formed in a self-aligned manner.

[0005]

In the case of a shielded bit line type DRAM stacked cell, a cell plate (CP), which is an upper electrode of a capacitor, is formed immediately below an Al wiring (see FIGS. 25 and 26). The contact on the CP formed on the plate is composed of a lower field (hereinafter referred to as FL) and a transfer gate (hereinafter referred to as TG).
And shallower than other contacts respectively formed on bit lines (hereinafter referred to as BL). Further, in order to increase the surface area of the capacitor, a capacitor having a three-dimensional structure in which the lower electrode of the capacitor is formed vertically higher than the semiconductor substrate is employed. Therefore, the thick film stack shown in FIG. 25, the difference in depth between the CP contact and other contacts becomes more remarkable.

In this case, FL, TG, BL and C
When each contact on P is opened, the contact on the shallowest CP is opened first, and the CP is scraped until the remaining contacts are opened. In the worst case,
There is a problem in that even the base insulating film is cut off through the CP, thereby causing a short circuit with the base pattern.

Further, in the case of the prior art disclosed in Japanese Patent Application Laid-Open No. 5-14889, there is a problem that an extra space is required, which leads to an increase in chip size.

On the other hand, even if each contact is not opened at the same time, as shown in FIG. 27, when the CP contact is very shallower than the other contacts, the formation of the W plug 20 after the contact opening is completed. As a result, the W plugs 20 in the CP contacts are recessed (depositing the CVD-W over the entire surface and then etched back), resulting in sidewalls 21 of the W plugs 20 and subsequently removing the underlying CP 11 (FIG. 27).

The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device capable of preventing a shallow cell plate contact from penetrating at the time of simultaneous contact opening. In addition, the present invention realizes a method of manufacturing a semiconductor device capable of preventing penetration of a cell plate contact due to a recess at the time of etch-back of a refractory metal plug, thereby achieving improvement in reliability of Al wiring. It is.

[0010]

The invention according to claim 1 is
A base pattern, a base insulating film formed to cover the base pattern and having an opening, a capacitor having a three-dimensional structure formed on an upper surface of the base insulating film and in the opening, and an upper electrode of the capacitor; An interlayer insulating film formed so as to cover the upper surface of the base insulating film, another interlayer insulating film formed so as to further cover the upper surface of the interlayer insulating film, and an interlayer insulating film different from the interlayer insulating film. A via hole formed on the upper surface of the upper electrode of the capacitor as a bottom surface thereof; a metal layer filling the via hole; a wiring layer formed on both upper surfaces of the metal layer and another interlayer insulating film; Ri semiconductor device der having a contact formed on the insulating film and the underlying insulating lining, and the metal layer
The wiring layer is formed integrally with metal wiring.
You .

[0011]

[0012]

[0013]

[0014] The invention according to claim 2 is the semiconductor device according to claim 1, wherein, which has the via hole opening by using the wet etching and dry etching,
An etch portion is formed on the upper portion by the wet etching.

[0015] According to a third aspect of the present invention, there is provided a base pattern,
A base insulating film formed to cover the base pattern and having an opening; and a three-dimensional structure formed in the opening in the base insulating film and in a portion of the upper surface of the base insulating film corresponding to a peripheral portion of the opening. A lower electrode of the capacitor having the structure;
A capacitor dummy pattern having a three-dimensional structure formed in another part of the upper surface of the base insulating film, a capacitor dielectric film covering a lower electrode of the capacitor and the capacitor dummy pattern, and a capacitor dielectric film covering the capacitor dielectric film. An upper electrode of the capacitor formed on the upper surface of the base insulating film, an interlayer insulating film formed on the upper surface of the base insulating film so as to cover the upper electrode of the capacitor, and a contact with the bottom portion of the capacitor dummy pattern within or upper electrode of the capacitor which corresponds to the right above, a semiconductor device der Ri with a further contact formed in the interlayer insulating film and the underlying insulating lining, The capacitor dummy pattern is shaped like a band.
It has been achieved .

[0016]

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

[0024]

According to the first aspect of the present invention, the formation of the via hole prevents the bottom electrode of the via hole from penetrating the upper electrode when the contact is opened. In addition, on the capacitor
The unit electrode is a multilayer wiring integrally formed by metal wiring.
Conducted with the line.

[0025]

[0026]

[0027]

(Invention of Claim 2 )
Since the upper portion is first etched by wet etching and then opened by dry etching, the bottom surface of the via hole does not penetrate the upper electrode of the capacitor when the contact is opened.

[0029] when (according the invention according to claim 3) of the other of the contact opening, even if the bottom of the contact as the worst case is penetration of the upper electrode of the capacitor, the capacitor dummy pattern, the underlying bottom of the contact is from the base insulating film Prevents reaching the pattern. Furthermore, capacitors
Dummy patterns can be contacted when opening other contacts.
To prevent the bottom of the gate from reaching the underlying pattern from the underlying insulating film.
Stop.

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

[0037]

[0038]

【Example】

(Embodiment 1) FIGS. 1 and 2 are sectional views showing the structure of a semiconductor device according to a first embodiment of the present invention. FIG. 1 is a sectional view of a shielded BL type DRAM having a thick film stacked capacitor and a cylindrical capacitor, respectively. Shows the structure.
In both figures, reference numerals common to FIGS. 25 and 26 indicate the same parts.

In order to solve the conventional problem, in this embodiment, only the contact on the CP 11 is formed as a via hole (hereinafter also referred to as TH) immediately below a multilayer wiring (hereinafter referred to as 2Al) 26 as a wiring layer. Other contacts (91, 92, etc.) are conventional examples (see FIGS. 25 and 26).
The configuration is as follows. With such a structure, CP
When the contact 11 and the other contact are simultaneously opened, a situation in which the CP11 on the shallow CP contact disappears during the contact processing does not occur.

1 and 2, a plug 25 of a high melting point metal such as W is used for a metal layer filling the via hole 23 with a barrier metal 24 such as Ti / TiN interposed therebetween. Also, 27
Is, for example, a TiN film.

Hereinafter, as a representative example, a manufacturing process of the semiconductor device of FIG. 1 will be described. However, the steps up to the formation of the CP11 of the thick-film stacked capacitor are the same as in the case of the conventional technique, and are also described in Example 6 described later, and thus are omitted here.

First, as shown in the sectional view of FIG.
After the formation of the interlayer insulating film 16 is deposited on the entire surface by CVD,
Flatten. The interlayer insulating film 16 is made of silane or TEOS SiO ₂ doped with phosphorus or boron.
(Reflow glass) obtained by reflowing by heat treatment. Alternatively, a laminated film of such reflow glass and non-doped SiO ₂ deposited by low-pressure CVD may be used.

Next, as shown in FIG. 4, a resist 95 is formed on the interlayer insulating film 16, and another contact is opened at a place other than on the CP 11 using the resist 95 as a mask.
In the example of FIG. 4, the contact 91 on the FL and the contact 92 on the BL are opened.

Next, after removing the resist 95,
So that it contacts the bottom surface of the other contacts (91, 92)
A barrier metal such as Ti / TiN is stacked, and then a high melting point metal such as W is deposited on the entire surface by a CVD method. After that, RIE
By etching the entire surface by the method, the refractory metal plug 14 is formed in the other contacts 91 and 92 (FIG. 5).
reference).

Thereafter, as shown in FIG.
An l wiring 12 is formed. Reference numeral 13 is, for example, a TiN film.

Next, as shown in FIG.
Another interlayer insulating film 17 is deposited by the method D. The interlayer insulating film 17 may be a laminated film using SOG (Toff glass).

Then, as shown in FIG. 8, after forming a new resist 96, via holes 23 are formed on CP11 and desired AL1 (first Al wiring: not shown) using this resist 96 as a mask. Form. After that, a refractory metal plug and Al2 (second Al wiring) are sequentially formed in the via hole 23.

(Embodiment 2) FIGS. 9 and 10 are sectional views showing the structure of a semiconductor device according to a second embodiment of the present invention. The structure of a DRAM having a thick film capacitor and a cylindrical capacitor is shown in FIG. Is shown.

In this embodiment, as shown in FIGS. 9 and 10, only the contact on CP11 is
H, and other contacts (91, 92, etc.) are formed as usual. Here, the above-mentioned TH opening method is performed by wet etching + dry etching, and instead of the multilayer wiring (2Al), As the wiring layer, a metal wiring 30 such as Al or CU without a plug is used. That is, in this embodiment, the multilayer wiring (2A
1) and the high melting point metal plug are integrally formed by the metal wiring 30. 28 is a wet etch, 29
Indicates a barrier metal (Ti / TiN or the like).

Also in this case, similarly to the first embodiment, when all contacts are simultaneously opened, there is no possibility that the CP11 is scraped and lost due to the penetration of the shallow CP contact.

Hereinafter, as a representative example, the main part of the manufacturing process of the semiconductor device shown in FIG. 9 will be described. However, here, only the manufacturing process sectional view (FIG. 11) after the formation of the CP11 and the other contact holes 91 and 92 is shown. The steps before that are the same as in the first embodiment.

As shown in FIG. 11, another interlayer insulating film 17 is formed.
Vias are formed on CP11 and desired AL1 (first Al wiring: also not shown) using resist 94 formed thereon as a mask. However, the opening of the via hole in this case is performed by forming the resist mask 94, then wet-etching the interlayer insulating film 17 with an HF solution, and further performing anisotropic etching by RIE.

After forming the via hole, the wiring is made of Ti / TiN
After stacking barrier metal such as
This is performed by sputtering. As this Al sputtering, Al reflow sputtering may be applied.

(Embodiment 3) FIGS. 12A and 12B are views showing the structure of a semiconductor device according to a third embodiment of the present invention, in which FIG. 12A is a sectional view and FIG. FIG.

As shown in FIG. 12A, in this embodiment, a three-dimensional structure is formed on the upper surface of the silicon oxide film 7 immediately below the CP contact 35 as a measure against the removal of the underlying pattern when the contact of the CP contact is opened. A capacitor dummy pattern 33 is provided. In this case, the capacitor dummy pattern 33 is the lower electrode 9 of the cylindrical capacitor 9.
3, and the pattern 38 is arranged in a band shape on the outermost periphery of the memory cell as shown in FIG. Reference numeral 34 denotes a metal wiring such as Al, 36 denotes a barrier metal (Ti / TiN or the like), 37 denotes a TiN film, and 39 denotes a capacitor pattern.

Such a capacitor dummy pattern 33
In the worst case, even if the bottom of the shallow CP contact 35 penetrates through CP11 at the same time when all the contacts are simultaneously opened, the scraping of the CP contact 35 is reduced within the pattern 33 due to the presence of the pattern 33, Does not penetrate the base insulating film 7. A state in which the above-described effect is obtained even in the worst case is shown in the sectional view of FIG.

In addition, the following effects can be obtained by forming the capacitor dummy pattern 33 in a strip shape on the outermost periphery. That is, (1) regularity (linearity) of the outermost peripheral edge of the memory cell array can be obtained, so that a pattern can be easily created, and (2) a dummy pattern does not contact the substrate (floating). If the pattern is formed as a small area pattern, there is a problem that the dummy pattern is scattered. However, if a large area pattern is formed in a belt shape as described above, there is an advantage that such a problem does not occur.

(Embodiment 4) FIG. 14 is a cross-sectional view showing the structure of a semiconductor device (DRAM) according to a fourth embodiment of the present invention.

As shown in FIG. 14, also in this embodiment, similarly to the third embodiment, a capacitor dummy pattern 33A having a three-dimensional structure is provided immediately below the CP contact 43. The dummy pattern 33A in this case is formed using the pattern of the lower electrode of the thick film capacitor 18, and its layout is not shown here, but is arranged in a strip shape on the outermost periphery of the memory cell as in FIG. ing.

Also in the fourth embodiment, the effects described in the third embodiment can be obtained as they are.

(Embodiment 5) Here, FIG. 12 and FIG.
And the C covering the capacitor dummy pattern shown in FIG.
P11 is connected to set the potential of the capacitor dummy pattern to the same potential as CP11 (generally 1/2 Vcc). In the worst case, the bottom surface of the shallow CP contact 35 penetrates through CP11 at the time of opening the contact, resulting in conduction between the capacitor dummy pattern and CP11.
11 is intended to be configured to have the same potential.

(Embodiment 6) Embodiment 6 relates to an improvement of the prior art shown in FIG.

FIGS. 15 to 24 are sectional views showing a method for manufacturing a semiconductor device according to the sixth embodiment of the present invention. It should be noted that, for convenience of explanation, illustration of steps before FIG. 15 is omitted. Here, as an example, a method for manufacturing a shielded bit line type stacked DRAM cell having a cylindrical capacitor will be described. 15 to 24, the same reference numerals as those in FIGS. 25 and 26 indicate the same components.

FIG. 15 shows a state after a base pattern, that is, an isolation region (isolation oxide film 1), a gate electrode 4 of a transistor, and a shield bit line 6 are sequentially formed.

Next, as shown in FIG. 16, a silicon oxide film (base insulating film) is formed so as to cover the entire surface of the shield bit line 6.
7 is deposited, and the silicon oxide film 7 is flattened by a method such as etch back. Thereafter, openings 90 are provided in the silicon oxide films 7 and 5 on the impurity regions 2 and 3 and not on the shield bit line 6 side.

Next, as shown in FIG. 17, a polycrystalline silicon layer 44 as a conductive layer is deposited on the silicon oxide film 7 so as to be in contact with the impurity region 2 at the bottom of the opening. A silicon oxide film 45 is deposited thereon.

Then, as shown in FIG. 18, the two films 44 and 45 are processed to leave only desired portions thereof (portions corresponding to the openings 90 in FIG. 8). Another polycrystalline silicon layer 47 is deposited so as to be in contact with the exposed side surface of. Both polycrystalline silicon layers 4
The remaining portion of the silicon oxide film 45 covered with 4, 47 becomes the core 46 of the cylindrical capacitor.

Next, as shown in FIG. 19, another polycrystalline silicon layer (47 in FIG. 18) deposited last in the above step is anisotropically etched without using the entire surface mask, so that the side surfaces of the polycrystalline silicon are removed. A wall 47A is formed. Then, the silicon oxide film left at a desired place (4 in FIG. 18)
If 6) is removed by gas phase HF, a lower electrode of a cylindrical stacked capacitor composed of the sidewall 47A and the polycrystalline silicon layer 44 is completed. Thereafter, a capacitor dielectric film 10 and a cell plate 11 as an upper electrode of the stacked capacitor are sequentially deposited on the exposed surface of the lower electrode and the exposed surface of the silicon oxide film 7.

Next, as shown in FIG. 20, an interlayer insulating film 48 is deposited so as to cover the cell plate 11 as the capacitor upper electrode, and is flattened.

Originally, the interlayer insulating film 48 is thickly deposited and flattened by etch back or the like. However, undercutting occurs when performing W etch back or the like as shown in FIG. 27 of the conventional example. Therefore, in order to prevent this, after depositing the thick interlayer insulating film 48, each contact is separately opened directly to the interlayer insulating film 48 without performing an etch-back, and the contact hole 49 is formed in the contact hole 49. After forming the barrier metal 51, the W plug 50 is formed (see FIG. 23).

The method of opening each contact is described below. First, as shown in FIG. 21, a resist pattern 97 is formed on the interlayer insulating film 48, and using this resist pattern 97, other contact holes (91, 92) are opened in places other than on the CP11. Next, after removing the resist pattern 97, a new resist pattern 98 is formed.
Then, a contact hole is opened on the substrate 1 (FIG. 22). Thereafter, the process shown in FIG. 23 is performed.

After the step of FIG. 23, as shown in FIG.
If the interlayer insulating film 48 is etched back to a predetermined film thickness after the formation of the W plug 50, the DRAM can be manufactured without causing the problems that have occurred in the prior art. Here, the W plug 50 is etched back until the protrusion 52 of the W plug 50 is formed.

In this embodiment, the silicon oxide film 45 serving as the core 46 at the time of forming the cylindrical capacitor is a normal pressure oxide film doped with boron and phosphorus. Then, when the cylindrical core 46 is removed by the gas phase HF, the underlying silicon oxide film 7 is not shaved. In this case, the underlying silicon oxide film 7 is a non-doped silicon oxide film deposited in a low pressure CVD furnace.

The interlayer insulating film 48 deposited on the cell plate 11 as the upper electrode of the capacitor may be a TEOS-based or silane-based oxide film doped with boron or phosphorus, and may be a non-doped film deposited in a reduced pressure furnace. It may be a silicon oxide film. Also, a layered film thereof may be used.

(Effects on Embodiment) In a stacked DRAM cell of a shielded bit line type, according to the prior art, the CP of the contact portion on the shallow CP at the time of contact opening is formed.
In the worst case, there is a problem that the underlying insulating film is removed to cause a short circuit with the underlying wiring (the underlying pattern). However, according to the first and second embodiments of the present invention, the CP contact is replaced with TH. This can solve the above problem.

According to the third to fifth embodiments of the present invention, C
By providing a three-dimensional dummy pattern such as a cylinder or a thick film just below the P contact in the outermost periphery using the lower electrode of the capacitor, the bottom surface of the CP contact penetrates the CP as a worst case when opening the contact. Even if it does, short-circuiting between the lower surface of the CP contact and the underlying pattern can be prevented.

According to the prior art, when a high melting point metal plug is formed in a contact by W-CVD + etchback, a recess at the time of etchback cuts the CP at the bottom of the contact above the shallow CP. A
There is a problem that the reliability of the l wiring is deteriorated. However, if the method of etching back the interlayer insulating film after the formation of the W plug as in the sixth embodiment of the present invention is used, the above problem can be solved.

[0078]

According to the first aspect of the present invention, there is an effect that it is possible to prevent the contact on the upper electrode of the capacitor from penetrating through at the time of opening the contact.
In addition, the capacitor generated when opening the contact
Penetration of contacts on external electrodes can be prevented.
Has an effect.

[0079]

[0080]

[0081]

According to the second aspect of the present invention, there is an effect that it is possible to prevent the contact on the upper electrode of the capacitor from penetrating through at the time of opening the contact.

According to the third aspect of the present invention, there is an effect that it is possible to prevent a contact on the upper electrode of the capacitor from penetrating through the upper electrode and short-circuiting with the underlying pattern when another contact is opened. In addition, other
Contact on top electrode of capacitor when opening tact
Penetrates through the upper electrode and shorts with the underlying pattern.
There is an effect that can be prevented.

[0084]

[0085]

[0086]

[0087]

[0088]

[0089]

[0090]

[0091]

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing the structure of another semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 7 is a sectional view illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention;

FIG. 8 is a sectional view showing a manufacturing step of the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a sectional view showing the structure of another semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a sectional view illustrating a manufacturing step of a semiconductor device according to a second embodiment of the present invention;

FIG. 12 is a sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 13 is a cross-sectional view for explaining that the semiconductor device according to the third embodiment of the present invention can exert its effects even in the worst case.

FIG. 14 is a sectional view showing a structure of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 15 is a sectional view showing a manufacturing step of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 16 is a sectional view illustrating a manufacturing step of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 17 is a sectional view illustrating a manufacturing step of a semiconductor device according to a sixth embodiment of the present invention;

FIG. 18 is a sectional view illustrating a manufacturing step of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 19 is a sectional view showing a manufacturing step of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 20 is a sectional view illustrating a manufacturing step of the semiconductor device according to the sixth embodiment of the present invention;

FIG. 21 is a sectional view illustrating a manufacturing step of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 22 is a sectional view illustrating a manufacturing step of the semiconductor device according to the sixth embodiment of the present invention;

FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device according to the sixth embodiment of the present invention.

FIG. 24 is a sectional view showing a manufacturing step of the semiconductor device according to the sixth embodiment of the present invention;

FIG. 25 is a cross-sectional view showing a structure of a conventional semiconductor device.

FIG. 26 is a cross-sectional view showing the structure of another conventional semiconductor device.

FIG. 27 is a cross-sectional view showing the structure of another conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Isolation oxide film, 2 Low concentration impurity layer, 3 High concentration impurity layer, 4 Gate electrode, 5 Silicon oxide film, 6 Bit line, 7 Silicon oxide film, 8 Substrate contact of capacitor lower electrode, 9 Cylindrical capacitor, 10 Capacitor dielectric Film, 11 cell plate, 12 Al wiring, 13
TiN film, 14W plug, 15 barrier metal (Ti
/ TiN), 16 interlayer insulating film (reflow glass), 1
7 Another interlayer insulating film, 18 Thick film capacitor, 19 Underground collapse, 20 W plug, 21 W plug side wall, 22 via hole, 24 barrier metal, 25 W plug, 26 multilayer wiring (2Al), 27 TiN film, 2
8 Wet etch of via hole, 29 Barrier metal, 30 Al wiring, 31 TiN film (ARC), 33
Capacitor dummy pattern (cylindrical), 34 Al wiring, 35 CP contact, 36 barrier metal, 37
TiN film (ARC), 38 capacitor dummy pattern, 39 capacitor, 40 TiN film (ARC), 4
1 Al wiring, 42 barrier metal, 43 CP contact, 44 polycrystalline silicon, 45 silicon oxide film, 4
6 Core of cylindrical capacitor, 47 polycrystalline silicon, 48
Interlayer insulating film, 49 contact hole, 50 W plug, 51 barrier metal, 52 W plug protruding above the interlayer insulating film (projection), 91 FL contact, 92 BL contact, 93 capacitor Lower electrode, 100 semiconductor substrate.

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ identification code FI H01L 27/10 621C 681B (58) Investigated field (Int.Cl. ⁷ , DB name) H01L 21/8242 H01L 21/28 H01L 21 / 768 H01L 27/108

Claims (3)

(57) [Claims] A base pattern, a base insulating film formed to cover the base pattern and having an opening, a capacitor having a three-dimensional structure formed on an upper surface of the base insulating film and in the opening, An interlayer insulating film formed so as to cover the upper electrode of the capacitor and the upper surface of the base insulating film; another interlayer insulating film formed so as to cover the upper surface of the interlayer insulating film; A via hole formed in the interlayer insulating film and having the upper surface of the upper electrode of the capacitor as a bottom surface, a metal layer filling the via hole, and wiring formed on both upper surfaces of the metal layer and another interlayer insulating film And a contact formed in the interlayer insulating film and the base insulating film , wherein the metal layer and the wiring layer are integrally formed by metal wiring.
A semiconductor device characterized by being performed . 2. The semiconductor device according to claim 1, wherein said via hole is formed by wet etching and dry etching.
The opening is formed by using
Etch part formed by etch etching
A semiconductor device characterized by the above-mentioned . 3. An underlayer pattern and an opening formed to cover the underlayer pattern.
A base insulating film, and an opening in the base insulating film and an upper surface of the base insulating film.
3 formed in a portion corresponding to a peripheral portion of the opening portion.
A lower electrode of a capacitor having a three- dimensional structure, and a third electrode formed in another portion of the upper surface of the base insulating film.
Original structure capacitor dummy pattern, lower electrode of capacitor and capacitor dummy pattern
And a capacitor dielectric film covering the capacitor insulating film, and covering the base insulating film so as to cover the capacitor dielectric film.
An upper electrode of the capacitor formed on the surface, and the base insulating film covering the upper electrode of the capacitor.
An interlayer insulating film formed on the upper surface of the capacitor dummy, and the capacitor dummy formed in the interlayer insulating film and
The top of the capacitor in or just above the pattern
A contact having a bottom at the electrode portion and another contact formed in the interlayer insulating film and the underlying insulating film;
And the capacitor dummy pattern is formed in a band shape.
A semiconductor device characterized by the above-mentioned .