JP3323207B2 - Frequency-voltage conversion circuit, delay amount determination circuit, system including frequency-voltage conversion circuit, method for adjusting input / output characteristics of frequency-voltage conversion circuit, and apparatus for automatically adjusting input / output characteristics of frequency-voltage conversion circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a frequency-voltage conversion circuit and its application, and a delay amount determination circuit.

2. Description of the Related Art Conventionally, in the design of a semiconductor integrated circuit (LSI), the specifications of the LSI (for example, the minimum power supply voltage of the LSI, the maximum operating frequency, and the like) are determined in consideration of the worst conditions for process variation and temperature variation. Was.

When operating the LSI at a frequency lower than the maximum operating frequency or when the processing performance of the LSI changes due to process fluctuations or temperature fluctuations, it is possible to operate the LSI at a voltage lower than the minimum power supply voltage based on the LSI specifications It should be. However, the power supply voltage supplied to the LSI is fixed regardless of the operating environment of the LSI. For this reason, the LSI consumed unnecessary power.

An object of the present invention is to provide a frequency-to-voltage conversion circuit that can be adjusted to adapt to the characteristics of a target circuit.

It is another object of the present invention to provide a system including a frequency-to-voltage conversion circuit that supplies a minimum operating voltage necessary for a target circuit to operate normally.

It is another object of the present invention to provide a method for adjusting input / output characteristics of a frequency-voltage conversion circuit in the above system.

Another object of the present invention is to provide an apparatus for automatically adjusting input / output characteristics of a frequency-voltage conversion circuit in the above system.

Another object of the present invention is to provide a delay amount determination circuit having a simple configuration suitable for use in a frequency-voltage conversion circuit.

DISCLOSURE OF THE INVENTION A frequency-to-voltage conversion circuit of the present invention is a frequency-to-voltage conversion circuit that receives a clock as an input and provides a voltage corresponding to the frequency of the clock as an output. Adjustment can be made so that the characteristics substantially match the given input / output characteristics. Thereby, the above object is achieved.

The frequency-voltage conversion circuit may be configured such that a slope and an offset amount of input / output characteristics of the frequency-voltage conversion circuit can be adjusted.

Another frequency-voltage conversion circuit of the present invention includes an input pulse signal generation circuit that generates an input pulse signal having a pulse width representing a target delay amount according to a clock frequency, and a delay circuit that delays the input pulse signal. A delay circuit that outputs a pulse signal obtained by delaying the input pulse signal as an output pulse signal; and a delay circuit that corresponds to the target delay amount based on a delay amount of the output pulse signal with respect to the input pulse signal. A delay-voltage conversion circuit that outputs a voltage and supplies the voltage to the delay circuit, wherein the delay circuit delays the input pulse signal according to the voltage output from the delay-voltage conversion circuit. Let it. This achieves the above object.

The input pulse signal generation circuit may generate the input pulse signal intermittently.

The cycle at which the input pulse signal is generated intermittently may be variable.

The input pulse signal generation circuit may stop generating the input pulse signal in a specific mode.

The delay circuit may be configured such that a delay time-power supply voltage characteristic of the delay circuit is adjustable.

The delay circuit may be configured such that a delay time of the delay circuit and a slope and an offset amount of a power supply voltage characteristic can be adjusted.

The delay circuit includes a first delay block that operates according to the voltage output from the delay-voltage conversion circuit, and the first delay block includes a plurality of first delay units. The number of stages of the first delay unit through which the input pulse signal passes among the plurality of first delay units may be adjusted according to a first delay control signal.

The delay circuit further includes a second delay block that operates according to a predetermined fixed voltage, wherein the second delay block includes a plurality of second delay units, and includes a plurality of second delay units. The number of stages of the second delay unit through which the input pulse signal passes may be adjusted according to a second delay control signal.

The pulse width of the input pulse signal may be determined as a function of the frequency of the clock.

The function is represented by Pw = α / f + β, where
Pw may be a pulse width of the input pulse signal, f may be a frequency of the clock, and α and β may be constants.

The delay amount-voltage conversion circuit increases an output voltage when a delay amount of the output pulse signal with respect to the input pulse signal is larger than the target delay amount, and increases a delay amount of the output pulse signal with respect to the input pulse signal. When the output voltage is lower than the target delay amount,
The output voltage may be feedback controlled.

A delay-voltage conversion circuit that determines whether a delay amount of the output pulse signal with respect to the input pulse signal is greater than the target delay amount, and outputs a determination signal indicating a determination result; A voltage selection circuit for selectively outputting one of a plurality of voltages according to a signal.

The voltage selection circuit includes a bidirectional shift control circuit that shifts data specifying one voltage to be selected from among the plurality of voltages in a direction corresponding to the determination signal, and based on the data, And a switch circuit for selecting one of them.

The voltage selection circuit may output a highest voltage among the plurality of voltages as an initial output voltage.

The voltage selection circuit includes a resistor, one end of the resistor is connected to a high potential, the other end of the resistor is connected to a low potential, and the plurality of voltages are obtained by dividing the resistor. You may.

The voltage selection circuit may further include a switch connected in series with the resistor, and the switch may be turned off in a specific mode.

The bidirectional shift control circuit includes a plurality of stages of units, each of the plurality of stages of units includes a memory circuit for storing the data and a two-input one-output selector, The output of the selector included in the unit of the specific stage among the units of the stage is connected to the memory circuit included in the unit of the specific stage, and the unit of the specific stage among the units of the plurality of stages The input of the selector included in the memory circuit is included in the memory circuit included in the unit in the stage immediately before the unit in the specific stage and the memory circuit included in the unit in the stage after the unit in the specific stage. And the selector included in each of the units of the plurality of stages may be controlled by the determination signal.

The bidirectional shift control means includes means for preventing the data stored in the memory circuit included in the first one of the plurality of units from being erased, and Means for preventing the data stored in the memory circuit included in the last unit from being erased may be further provided.

The delay amount-voltage conversion circuit calculates the delay amount by 1
Means for storing a previous output voltage, wherein the delay amount-voltage conversion circuit converts the current output voltage to a first output voltage.
And outputs the current output voltage and the 1
One of the previous output voltages may be output as a second output voltage, and the first output voltage may be supplied to the delay circuit.

The delay amount-voltage conversion circuit further includes means for storing an initial output voltage, the delay amount-voltage conversion circuit outputs a current output voltage as a first output voltage, and outputs the initial output voltage. Output as a second output voltage, the first output voltage is supplied to the delay circuit, and the initial output voltage is updated to the current output voltage when the current output voltage increases. Good.

The delay amount determination circuit according to the present invention includes an input pulse signal generation circuit that generates an input pulse signal having a pulse width representing a target delay amount, and a delay circuit that delays the input pulse signal, wherein the input pulse signal is delayed. A delay circuit that outputs a pulse signal obtained by the output pulse signal as an output pulse signal; and a determination signal that determines whether a delay amount of the output pulse signal with respect to the input pulse signal is greater than the target delay amount, and that indicates a determination result. And a decision circuit for outputting the result, thereby achieving the above object.

The pulse width of the input pulse signal may be variably adjustable.

The determination circuit may include a data latch circuit that receives the input pulse signal as a clock input and receives the output pulse signal as a data input, and an output of the data latch circuit may be output as the determination signal.

The system of the present invention is a system comprising: a target circuit that operates according to a clock; and a power management circuit that supplies a minimum voltage at which the target circuit can operate according to the frequency of the clock to the target circuit. The power management circuit includes the above-described frequency-voltage conversion circuit, and the power management circuit supplies the voltage output from the frequency-voltage conversion circuit to the target circuit as the minimum voltage. This achieves the above object.

The system may be formed on a single semiconductor chip.

The power management circuit further includes voltage conversion means for converting a given power supply voltage to the voltage output from the frequency-voltage conversion circuit, and the power management circuit outputs the output of the voltage conversion means The minimum voltage may be supplied to the target circuit.

Another system of the present invention includes a target circuit that operates according to a clock, and a frequency-voltage conversion circuit that receives the clock as an input and provides a voltage corresponding to the frequency of the clock as an operation voltage of the target circuit. Input / output characteristics of the frequency-to-voltage conversion circuit so that the voltage output from the frequency-to-voltage conversion circuit substantially matches a minimum voltage at which the target circuit can operate at the frequency of the clock. Is adjustable. This achieves the above object.

The target circuit has a plurality of different delay time-power supply voltage characteristics, and an input / output characteristic of the frequency-voltage conversion circuit is a delay obtained by combining the plurality of different delay time-power supply voltage characteristics. It may be adjusted based on the time-power supply voltage characteristics.

The frequency-voltage conversion circuit has a plurality of delay circuits corresponding to the plurality of different delay time-power supply voltage characteristics, and each of the plurality of delay circuits has an adjustable delay time-power supply voltage characteristic. It may be configured as such.

The frequency-voltage conversion circuit may be configured such that a slope and an offset amount of input / output characteristics of the frequency-voltage conversion circuit can be adjusted.

The method of the present invention is directed to a system including a target circuit that operates according to a clock, and a frequency-voltage conversion circuit that receives the clock as an input and provides a voltage corresponding to the frequency of the clock as an operation voltage of the target circuit. A method of adjusting input / output characteristics of the frequency-voltage conversion circuit, wherein the frequency-voltage conversion circuit adjusts the input / output characteristics of the frequency-voltage conversion circuit based on an operating voltage of the target circuit measured for each of a plurality of frequencies of the clock. Adjusting the slope of the input / output characteristics, and adjusting an offset amount of the input / output characteristics of the frequency-voltage conversion circuit so that the target circuit can operate in a predetermined frequency range of the clock. Which achieves the above object.

The frequency-voltage conversion circuit is an input pulse signal generation circuit that generates an input pulse signal having a pulse width representing a target delay amount according to the frequency of the clock, and a delay circuit that delays the input pulse signal, A delay circuit that outputs a pulse signal obtained by delaying an input pulse signal as an output pulse signal, based on a delay amount of the output pulse signal with respect to the input pulse signal,
A delay-voltage conversion circuit that outputs a voltage corresponding to the target delay amount and supplies the voltage to the delay circuit, wherein the delay circuit outputs the voltage output from the delay-voltage conversion circuit. The input pulse signal is delayed according to the following equation, and the slope of the input / output characteristic of the frequency-voltage conversion circuit is:
The delay amount of the delay circuit is adjusted by adjusting the slope of the power supply voltage characteristic, and the offset amount of the input / output characteristic of the frequency-voltage conversion circuit is adjusted by adjusting the offset amount of the delay time-power supply voltage characteristic of the delay circuit. May be adjusted.

The delay circuit includes a first delay block that operates according to the voltage output from the delay amount-voltage conversion circuit, and a second delay block that operates according to a predetermined fixed voltage. The delay block includes a plurality of first delay units, the second delay block includes a plurality of second delay units, and a slope of a delay time-power supply voltage characteristic of the delay circuit is the plurality of first delay units. The first delay unit is adjusted by adjusting the number of stages of the first delay unit through which the input pulse signal passes, and the offset amount of the delay time-power supply voltage characteristic of the delay circuit is adjusted by the plurality of second delay units. It may be adjusted by adjusting the number of stages of the second delay unit through which the input pulse signal passes.

The frequency-voltage conversion circuit is an input pulse signal generation circuit that generates an input pulse signal having a pulse width representing a target delay amount according to the frequency of the clock, and a delay circuit that delays the input pulse signal, A delay circuit that outputs a pulse signal obtained by delaying an input pulse signal as an output pulse signal, based on a delay amount of the output pulse signal with respect to the input pulse signal,
A delay-voltage conversion circuit that outputs a voltage corresponding to the target delay amount and supplies the voltage to the delay circuit, wherein the delay circuit outputs the voltage output from the delay-voltage conversion circuit. The input pulse signal is delayed according to the following equation, and the slope and offset amount of the input / output characteristics of the frequency-voltage conversion circuit are adjusted by adjusting the pulse width of the input pulse signal as a function of the frequency of the clock. Is also good.

The function is represented by Pw = α / f + β, where
Pw is the pulse width of the input pulse signal, f is the frequency of the clock, α and β are constants, and the slope of the input / output characteristic of the frequency-voltage conversion circuit is adjusted by adjusting the value of the constant α. The offset amount of the input / output characteristic of the frequency-voltage conversion circuit may be adjusted by adjusting the value of the constant β.

An apparatus of the present invention is a system including a target circuit that operates according to a clock, and a frequency-voltage conversion circuit that receives the clock as an input and provides a voltage corresponding to the frequency of the clock as an operation voltage of the target circuit. A device for automatically adjusting an input / output relationship of the frequency-voltage conversion circuit, wherein a self-diagnosis means for determining whether or not the target circuit operates normally in a relationship between the operating voltage and the clock frequency. And adjusting means for adjusting the input / output relationship of the frequency-voltage conversion circuit based on the determination result by the self-diagnosis means, whereby the above object is achieved.

The self-diagnosis unit includes an operation unit that operates the target circuit with respect to an input vector that implements a longest delay path of the target circuit, an output of the target circuit with respect to the input vector, and a predetermined expected value with respect to the input vector. And matching means for matching

The adjusting means may include means for adjusting a slope of input / output characteristics of the frequency-voltage conversion circuit, and means for adjusting an offset amount of input / output characteristics of the frequency-voltage conversion circuit.

The system and the device may be formed on a single semiconductor chip.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a configuration of a system 1 according to a first embodiment of the present invention.

FIG. 2 is a diagram showing the relationship between the delay time-power supply voltage characteristic of the target circuit 10 and the delay time-power supply voltage characteristic of the delay circuit 40.

 FIG. 3 is a diagram showing a configuration of the delay circuit 40.

FIG. 4 is a diagram for explaining a method of adjusting the delay time-power supply voltage characteristic of the delay circuit 40.

 FIG. 5 is a diagram showing a configuration of the minimum voltage detection circuit 30.

 FIG. 6 is a diagram showing a configuration of the voltage selection circuit 33.

 FIG. 7 is a diagram showing a configuration of the delay amount determination circuit 32.

8A to 8C show the input pulse signal P1 and the output pulse signal P2.
FIG. 4 is a diagram showing a phase relationship between

FIG. 9 is a diagram showing a transition of the minimum voltage _IVdd from the transition state to the lock state.

10A to 10C are diagrams illustrating a method of dividing the resistor 332.

FIG. 11A shows the input pulse signal P in the appropriate locked state.
FIG. 4 is a diagram showing a correspondence between a rising edge of No. 1 and a rising edge of an output pulse signal P2.

FIG. 11B is a diagram illustrating an example of a correspondence relationship between a rising edge of the input pulse signal P1 and a rising edge of the output pulse signal P2 in an inappropriate lock state.

Figure 12A is a diagram showing an example of a generation interval I ₁ of the input pulse signal P1 during transient response.

Figure 12B is a diagram illustrating an example of a generation interval I ₂ of the input pulse signal P1 in the locked state.

FIG. 13 is a diagram showing a configuration of an improved voltage selection circuit 33a.

FIG. 14 is a diagram illustrating transition of the voltage output from the improved voltage selection circuit 33a during the period from the transition state to the lock state.

FIG. 15A is a diagram showing a configuration of an improved state holding circuit 334a.

 FIG. 15B is a diagram showing the waveforms of the pulse signals P3 and P4.

FIG. 16 is a diagram illustrating transition of the voltage output from the improved voltage selection circuit 33a during the period from the transition state to the lock state.

FIG. 17 is a diagram illustrating a configuration of the system 1 according to the first embodiment of the present invention.

FIG. 18 is a diagram showing a configuration of the delay amount-voltage conversion circuit 30a.

FIG. 19 is a diagram showing a configuration of the system 1 when the power management circuit 20 is used as a core of the power management circuit.

FIGS.20A to 20E show the case where the target circuit 10 has a plurality of critical paths depending on the power supply voltage.
FIG. 3 is a diagram for explaining the principle of adjusting input / output characteristics of the voltage conversion circuit 21.

FIG. 21 is a diagram illustrating a configuration of a modification of the frequency-voltage conversion circuit 21.

FIGS. 22A and 22B are diagrams showing waveforms of the input pulse signal P1, the output pulse signal PA, the output pulse signal PB, and the output pulse signal P2.

FIG. 23 is a diagram illustrating a configuration of the system 2 according to the second embodiment of the present invention.

FIGS. 24A and 24B are diagrams illustrating the principle of adjusting the input / output characteristics of the frequency-voltage conversion circuit 21a by adjusting the pulse width of the input pulse signal P1.

FIG. 25 is a diagram for explaining a method of adjusting the input / output characteristics of the frequency-voltage conversion circuit 21a.

FIG. 26 is a diagram illustrating a configuration of the system 2 when the power management circuit 20a is used as a core of the power management circuit.

FIG. 27 is a diagram showing a configuration of the device 3 for automatically adjusting the input / output characteristics of the frequency-voltage conversion circuit 21a.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings.

First Embodiment FIG. 1 shows a configuration of a system 1 according to a first embodiment of the present invention. The system 1 includes a target circuit 10 and a power management circuit 20 that supplies a minimum operating voltage _VOP to the target circuit 10 according to the frequency of the clock CLK. The system 1 can be formed on a single semiconductor chip.

The target circuit 10 includes, for example, a digital signal processor (DS)
P) or a central processing unit (CPU). The target circuit 10 is
It operates according to the clock CLK.

The power management circuit 20 includes a minimum voltage detection circuit 30
, A delay circuit 40, and a power supply circuit 50.

The minimum voltage detection circuit 30 controls the minimum voltage _IVdd based on the phase difference between the input pulse signal P1 input to the delay circuit 40 and the output pulse signal P2 output from the delay circuit 40. The minimum voltage _IVdd is supplied to the delay circuit 40 and the power supply circuit 50.

The input pulse signal P1 is generated by the minimum voltage detection circuit 30, and is input to the delay circuit. Input pulse signal P1
Has a pulse width representing the target delay amount. The target delay amount is determined based on the frequency of the clock CLK. The target delay amount is, for example, the length of one cycle of the clock CLK.

The delay circuit 40 delays the input pulse signal P1. The time during which the input pulse signal P1 is delayed by the delay circuit 40 changes according to the minimum voltage _IVdd . The input pulse signal P1 delayed by the delay circuit 40 is output to the minimum voltage detection circuit 30 as an output pulse signal P2.

The power supply circuit 50 operates based on the minimum voltage _IVdd.
Generate V _OP . For example, the power supply circuit 50 has the minimum voltage I
The V _dd as the target voltage may be a voltage converter for converting a power supply voltage V _dd to the operating voltage V _OP. Such a voltage converter is preferably a DC / DC converter that converts a DC power supply voltage V _dd (eg, 3 V) into a DC operating voltage V _OP with high efficiency (eg, 95%). Power management circuit 20
This is to reduce the overall power consumption. Alternatively, the power supply circuit 50 may be an operational amplifier.

However, the power supply circuit 50 is
Is not required to be included. Instead of generating the operating voltage V _OP based on the minimum voltage IV _dd , the minimum voltage detection circuit 3
0 may be supplied to the target circuit 10 a minimum voltage IV _dd controlled as the operating voltage V _OP by.

FIG. 2 shows the relationship between the delay time-power supply voltage characteristic of the target circuit 10 and the delay time-power supply voltage characteristic of the delay circuit 40. The target circuit 10 operates using the operating voltage V _OP as a power supply voltage. The target circuit 10 operates with a shorter delay time as the power supply voltage is higher, and operates with a longer delay time as the power supply voltage is lower. The delay circuit 40 operates using the minimum voltage _IVdd as a power supply voltage.

The delay time-power supply voltage characteristic of the delay circuit 40 has a margin Δ
With V, it is adjusted in advance so as to conform to the delay time-power supply voltage characteristic of the target circuit 10. As shown in FIG. 2, the power supply voltage when the target circuit 10 operates with the target delay time _Td is V _min
Then, the minimum voltage IV _dd corresponding to the target delay time T _d is
It is represented by IV _dd = V _min + ΔV. Here, ΔV ≧ 0
It is.

Such a margin ΔV is equal to the minimum voltage IV _dd (or
It is provided to absorb the influence of the voltage drop of the operating voltage V _OP ) supplied by the power supply circuit 50 and the variation in performance between different semiconductor chips. When ΔV = 0 (that is, IV _dd = V _min ), a margin ΔV is added between the minimum voltage detection circuit 30 and the target circuit 10 to the minimum voltage IV _dd output from the minimum voltage detection circuit 30. Preferably, a circuit is provided.

The relationship between the delay time-power supply voltage characteristic of the target circuit 10 and the delay time-power supply voltage characteristic of the delay circuit 40 fluctuates so that the margin ΔV is maintained at a substantially constant value with respect to process fluctuations and temperature fluctuations. . This is because the target circuit 10 and the delay circuit 40
Are integrated on the same LSI chip.
Therefore, by monitoring the delay time-power supply voltage characteristics of the delay circuit 40, it is possible to obtain the minimum voltage _IVdd that satisfies the processing performance of the target circuit 10 under all circumstances.

FIG. 3 shows the configuration of the delay circuit 40. The delay circuit 40 includes a delay block 41 to which a fixed voltage IV _fix is applied, and a variable voltage I
And a delay block 42 to which _Vdd is applied. After passing through the delay block 41 and the delay block 42, the input pulse signal P1 is output as an output pulse signal P2.

The delay block 41 includes m delay units 41-1 to 41-
m and the selector 41-s. Here, m is an arbitrary integer. Each of the delay units 41-1 to 41-m may be, for example, an inverter. Selector 41-s
Is the input pulse signal of the delay units 41-1 to 41-m
It is used to adjust the number N1 of stages of delay units through which P1 passes. The selector 41-s is controlled by the delay amount control signal _SCTL1 . The delay control signal _SCTL1 is connected to the external terminal 61
(See FIG. 1).

The delay block 42 includes n delay units 42-1 to 42-
n and a selector 42-s. Here, n is an arbitrary integer. Each of the delay units 42-1 to 42-n may be, for example, an inverter. Selector 42-s
Is the input pulse signal of the delay units 42-1 to 42-n.
It is used to adjust the number N2 of delay units through which P1 passes. The selector 42-s is controlled by the delay control signal _SCTL2 . The delay control signal _SCTL2 is connected to the external terminal 62
(See FIG. 1). Here, the external terminals 61 and 62 may be common terminals.

Further, while the target circuit 10 is operating, the target circuit 10 generates the delay control signal S _CTL1 and / or the delay control signal S _CTL2 ,
By inputting them to the delay circuit 40, the number N1 of stages of delay units in the delay block 41 and / or the number N2 of stages of delay units in the delay block 42 may be changed.

FIG. 4 is a diagram for explaining a method of adjusting the delay time-power supply voltage characteristic of the delay circuit 40. In FIG. 4, a solid line indicates a delay time-power supply voltage characteristic of the target circuit 10. The delay time-power supply voltage characteristic of the target circuit 10 is, for example,
A plurality of test vectors including a test vector corresponding to a maximum delay (critical path) of 10 are input to the target circuit 10,
For each of the test vectors, the target circuit
It is obtained by comparing 10 actual operation results (good or bad) with predetermined expected values.

By adjusting the number N1 of stages of the delay unit through which the input pulse signal P1 passes in the delay block 41 according to the delay control signal _SCTL1 , the offset in the Y-axis direction of the curve showing the delay time-power supply voltage characteristic of the delay circuit 40 is adjusted. be able to.

By adjusting the number of stages N2 of the delay unit through which the input pulse signal P1 passes in the delay block 42 according to the delay control signal _SCTL2 , the slope of the curve showing the delay time-power supply voltage characteristic of the delay circuit 40 can be adjusted.

For example, in FIG. 4, the plot of the black triangle (▲)
6 shows the delay time-power supply voltage characteristics of the delay circuit 40 when N1 = 0 and N2 = 50. The black circle (●) plot shows N1 = 0 and
6 shows a delay time-power supply voltage characteristic of the delay circuit 40 when N2 = 150. Comparing the plot of the black triangle (▲) with the plot of the black circle (●), it can be seen that the plot of the black circle (●) has a larger slope of the curve indicating the delay time-power supply voltage characteristic of the delay circuit 40. In addition, the plot of white circles (○) indicates that N1 =
6 shows a delay time-power supply voltage characteristic of the delay circuit 40 when 150 and N2 = 150. Comparing the plot of black circles (●) and the plot of white circles (（) shows that the plot of white circles (○) has a larger offset of the curve showing the delay time-power supply voltage characteristic of the delay circuit 40.

As described above, by adjusting the offset and the slope of the curve indicating the delay time-power supply voltage characteristic of the delay circuit 40 in advance, the delay time-power supply voltage characteristic of the delay circuit 40 can be adjusted to the margin Δ
With V, it is possible to adapt to the delay time-power supply voltage characteristic of the target circuit 10. Alternatively, by adjusting the slope of the curve without adjusting the offset of the curve, the delay time-power supply voltage characteristic of the delay circuit 40 can be changed to the delay time-power supply voltage characteristic of the target circuit 10 with a margin ΔV. It may be possible to adapt. In this case, the delay block 41 may be omitted from the delay circuit 40, and the input pulse signal P1 may be input to the delay block 42 without passing through the delay block 41.

FIG. 5 shows the configuration of the minimum voltage detection circuit 30. The minimum voltage detection circuit 30 includes an input pulse signal generation circuit 31, a delay amount determination circuit 32, and a voltage selection circuit 33.

The input pulse signal generation circuit 31 intermittently generates the input pulse signal P1 based on the frequency of the clock CLK. The input pulse signal P1 has a pulse width representing a target delay amount. The target delay amount is determined based on the frequency of the clock CLK. The target delay amount is, for example, the length of one cycle of the clock CLK.

The delay amount determination circuit 32 determines whether the delay amount of the output pulse signal P2 with respect to the input pulse signal P1 is larger than the target delay amount, and outputs a determination signal K1 indicating the determination result to a voltage selection circuit.
Output to 33. When the delay amount of the output pulse signal P2 with respect to the input pulse signal P1 is larger than the target delay amount, the determination signal K1 is at a high level; otherwise, the determination signal K1 is at a low level. Therefore, the determination signal K1 can be represented by one bit.

The voltage selection circuit 33 selects one of a plurality of different voltages prepared in advance according to the determination signal K1, and outputs the selected voltage as the minimum voltage _IVdd . Judgment signal K1
Is used to indicate whether to output a higher voltage or a lower voltage among the plurality of voltages. Specifically, that the determination signal K1 is at a high level indicates that a higher voltage among the plurality of voltages is to be output, and that the determination signal K1 is at a low level indicates that the plurality of voltages are Indicates that a lower voltage should be output. Note that the output pulse signal P2 is used to control the timing at which the minimum voltage _IVdd is updated.

FIG. 6 shows the configuration of the voltage selection circuit 33. Voltage selection circuit
33 includes a bidirectional shift control circuit 331, a resistor 332, and a switch circuit 333.

The bidirectional shift control circuit 331 includes a D flip-flop 331
f-1 to 331f-5 and a multiplexer 331 with two inputs and one output
m-1 to 331m-5, and OR circuits 331o-1 and 331o-2.

Each of the D flip-flops 331f-1 to 331f-5 is synchronized with the rising edge of the output pulse signal P2,
Data is input from the preceding D flip-flop or the subsequent D flip-flop. D flip-flop 331f
Data having a value of "1" is held in any one of -1 to 331f-5, and data having a value of "0" is held in the remaining D flip-flops.

Each of the multiplexers 331m-1 to 331m-5 selects data to be stored in the corresponding D flip-flop according to the level of the determination signal K1.

The OR circuit 331o-1 stores the data having the value of "1" in the D flip-flop 331f-1 and the data having the value of "1" when the determination signal K1 is at the low level. It is provided to prevent erasure.

Similarly, the OR circuit 331o-2 includes a D flip-flop 331f.
When data having a value of “1” is stored in −5 and the determination signal K1 is at a high level,
It is provided to prevent data having a value of “1” from being erased.

The OR circuits 331o-1 and 331o-2 also have a function of preventing a malfunction in a transient state when the power of the power management circuit 20 is turned on.

The bidirectional shift control circuit 331 having the above-described configuration includes:
According to the determination signal K1, one of the control signals S1 to S5 is set to a high level, and the remaining control signals are set to a low level. For example, the state of the bidirectional shift control circuit 331 when the control signal S5 is at a high level and the control signals S1 to S4 are at a low level is set to state 1. State 1 can be represented as follows.

State 1: (S1, S2, S3, S4, S5) = (0, 0, 0, 0, 1) In state 1, when the low-level determination signal K1 is input to the bidirectional shift control circuit 331, State 1 is state 2
Transitions to.

State 2: (S1, S2, S3, S4, S5) = (0, 0, 0, 1, 0) In state 2, when the low-level determination signal K1 is input to the bidirectional shift control circuit 331, State 2 is state 3
Transitions to.

State 3: (S1, S2, S3, S4, S5) = (0, 0, 1, 0, 0) In state 3, when the high-level determination signal K1 is input to the bidirectional shift control circuit 331, State 3 is state 4
Transitions to.

State 4: (S1, S2, S3, S4, S5) = (0, 0, 0, 1, 0) Thus, according to the level of the determination signal K1, the control signal
The high-level control signals among S1 to S5 are shifted one by one. The level of the determination signal K1 indicates the direction of the shift. The timing at which the state of the bidirectional shift control circuit 331 changes is synchronized with the rising edge of the output pulse signal P2.

As described above, the bidirectional shift control circuit 331 outputs the determination signal K
It operates in response to only 1 and the output pulse signal P2. Therefore, it is very easy to control the bidirectional shift control circuit 331.

One end of the resistor 332 is connected to the power supply voltage V _c, the other end of the resistor 332 is connected to the ground voltage. According to the resistance division method,
The voltages at points R1 to R5 of the resistor 332 are supplied to the switch circuit 333 as voltages V1 to V5, respectively. Where V1 <V2
<V3 <V4 <V5.

The switch circuit 333 includes a plurality of switch elements 333-1 to 33-33.
3-5. A corresponding voltage is supplied to one end of each of the switch elements 333-1 to 333-5.
The control signals S1 to S5 are used to control on / off of the switch elements 333-1 to 333-5, respectively. Only the switch element corresponding to the high-level control signal is turned on, and the voltage corresponding to the switch element is selectively output.

It is preferable that the voltage selection circuit 33 has a function of limiting the range of the voltage _IVdd output from the voltage selection circuit 33 to a predetermined range. This is because the target circuit 10 may have a specification that it does not operate in the low voltage region. Restriction of the range of voltage IV _dd is achieved, for example, by limiting the number of stages of D flip-flops and selectors included in bidirectional shift control circuit 331.

FIG. 7 shows the configuration of the delay amount determination circuit 32. The delay amount determination circuit 32 includes a D flip-flop 321. The D flip-flop 321 has a data input terminal D, a clock input terminal CK, and an output terminal Q. The output pulse signal P2 is input to the data input terminal D. The input pulse signal P1 is input to the clock input terminal CK. The determination signal K1 is output from the output terminal Q.

The phase relationship between the input pulse signal P1 and the output pulse signal P2 is classified into two cases. One is the input pulse signal
The case where the output pulse signal P2 is at a low level at the rising edge of P1, and the other is the case where the input pulse signal
This is a case where the output pulse signal P2 is at a high level at the rising edge of P1.

FIG. 8A shows a case where the output pulse signal P2 is at a low level at the rising edge of the input pulse signal P1. In this case, the output pulse signal P2 with respect to the input pulse signal P1
Is smaller than the target delay amount. This is because the pulse width of the input pulse signal P1 corresponds to the target delay amount.

In the case shown in FIG. 8A, the delay amount determination circuit 32 outputs a low-level determination signal K1. This is because the D flip-flop 321 of the delay amount determination circuit 32 takes in the level (low level) of the output pulse signal P2 as data at the rising edge of the input pulse signal P1. As described above, in response to the low-level determination signal K1, the voltage selection circuit 33 controls the minimum voltage _IVdd to be lower than before.
As a result, the output pulse signal P2 with respect to the input pulse signal P1
Is increased. Thus, the input pulse signal
Feedback control is performed so that the delay amount of the output pulse signal P2 with respect to P1 approaches the target delay amount.

FIG. 8B shows a case where the output pulse signal P2 is at the high level at the rising edge of the input pulse signal P1. In this case, the output pulse signal P2 with respect to the input pulse signal P1
(Actual delay amount) is larger than the target delay amount. This is because the pulse width of the input pulse signal P1 corresponds to the target delay amount.

In the case shown in FIG. 8B, the delay amount determination circuit 32 outputs a high-level determination signal K1. This is because the D flip-flop 321 of the delay amount determination circuit 32 takes in the level (high level) of the output pulse signal P2 as data at the rising edge of the input pulse signal P1. As described above, in response to the high-level determination signal K1, the voltage selection circuit 33 controls the minimum voltage _IVdd to be higher than before.
As a result, the output pulse signal P2 with respect to the input pulse signal P1
Is reduced. Thus, the input pulse signal
Feedback control is performed so that the delay amount of the output pulse signal P2 with respect to P1 approaches the target delay amount.

FIG. 8C shows a state in which the phase relationship between input pulse signal P1 and output pulse signal P2 is locked by the feedback control described above. As described above, the voltage selection circuit 33 detects the rising edge of the input pulse signal P1 and the output pulse signal P2
The feedback control of the minimum voltage IV _dd is performed so that the falling edges of the two signals coincide.

Note that in such a locked state, the minimum voltage _IVdd oscillates between the two voltages. This is because even in the locked state, the determination signal K1 can take only one of a high level and a low level. The improvement for _keeping the level of the minimum voltage _IVdd constant in the locked state will be described later.

FIG. 9 shows the transition of the minimum voltage IV _dd from the transient state to the locked state. In this example, the minimum voltage _IVdd is initialized to the highest voltage V5 that can be output from the voltage selection circuit 33. It is preferable that the minimum voltage _IVdd is initialized to the highest voltage that can be output from the voltage selection circuit 33. This is to prevent the malfunction of the target circuit 10 caused by the deterioration of the processing capability.

As shown in FIG. 9, the minimum voltage IV _dd oscillates between two voltages (eg, voltages V2 and V1) in the locked state. If the difference between the two voltages is small enough, oscillating the minimum voltage IV _dd in the locked state is not substantially a problem in operating the target circuit 10.

If the voltage that converges in the locked state is known in advance, as shown in FIG.
By devising the dividing method of the above, the oscillation of the minimum voltage _IVdd can be suppressed.

FIG. 10A shows an example in which voltages V2 to V4 are concentrated near a voltage that finally converges in the locked state. As a result, the minimum voltage IV can be reduced without increasing the hardware scale.
It becomes possible to suppress the oscillation of _dd .

FIG.10B shows that the dividing interval of the resistor 332 is reduced,
By providing the switch 332-1 between the power supply voltage V _c1 and V _c2 and one end of a resistor 332, an example which enables to switch the power supply voltage applied to one end of the resistor 332. This makes it possible to suppress the oscillation of the minimum voltage _IVdd according to the type of the target circuit 10.

Further, by passing through a low-pass filter, the oscillation of the minimum voltage _IVdd can be removed.

In the first embodiment, the input pulse signal P1
Is generated intermittently by the input pulse signal generation circuit 31. The reason why the input pulse signal P1 is generated intermittently as described above is as follows (1) to (4).
(3).

(1) This is for suppressing unnecessary power consumption.

(2) In the above description, the voltage selection circuit 33 updates the minimum voltage _IVdd in synchronization with the rising edge of the output pulse signal P2. Therefore, before the input pulse signal P1 is next input to the delay circuit 40, the power supply voltage (the minimum voltage IV
(equivalent to _dd ) must be sufficiently stabilized.

(3) This is to avoid an inappropriate lock state. When the input pulse signal P1 is generated continuously,
There is a possibility that the minimum voltage _IVdd is feedback-controlled such that the rising edge of the input pulse signal P1 coincides with the falling edge of the output pulse signal P2 which does not originally correspond.

FIG. 11A shows the input pulse signal P in the appropriate locked state.
6 shows the correspondence between the rising edge of 1 and the rising edge of the output pulse signal P2. FIG. 11B shows an example of the correspondence between the rising edge of the input pulse signal P1 and the rising edge of the output pulse signal P2 in an inappropriate lock state.

Hereinafter, the power consumed in the minimum voltage detection circuit 30 and the delay circuit 40 will be considered.

The power consumed by the minimum voltage detection circuit 30 and the delay circuit 40 is determined by the delay circuit 40 and the resistor 32 that operate intermittently.
The power consumed by 2 is main. The bidirectional shift circuit 321 has an advantage that it consumes almost no power. This is because in the bidirectional shift circuit 321, only two of the data held in all the D flip-flops change at the same time.

Further, in order to reduce the power consumed in the minimum voltage detection circuit 30 and the delay circuit 40, the following means is effective.

In general, a mode called a sleep mode is often prepared for an LSI used in a portable device. When the target circuit 10 such LSI, as shown in FIG. 10C, the switch 332 between the one end and the supply voltage V _c of the resistor 332
Preferably, the switch 332-2 is turned off during the sleep mode to cut off the current flowing through the resistor 332. During the sleep mode, the pulse input signal P1 may not be generated.

Once in the locked state, the minimum voltage detection circuit 30 need only follow the temperature change of the delay circuit 40. Therefore, at the time of transient response, it is preferable that the input pulse signal P1 is generated at a relatively short interval, thereby leading the lock state quickly, and once the lock state is entered, the input pulse signal P1 is preferably generated at a long interval. Thus, power consumption in the locked state can be reduced.

12A shows an example of a generation interval I ₁ of the input pulse signal P1 during transient response. 12B shows an example of a generation interval I ₂ of the input pulse signal P1 in the locked state.

Further, switching of the generation interval of the input pulse signal P1
It may be linked with the reset period of the LSI by the system. This is because, at the time of reset, it is preferable to generate the input pulse signal P1 at relatively short intervals, thereby leading to a stable state quickly, and at the time of operating the LSI after reset release, it is preferable to generate the input pulse signal P1 at long intervals. This allows
Power consumption during operation of the LSI after reset release can be reduced.

When the output impedance from the resistor 332 is large, the minimum voltage _IVdd may be supplied to the delay circuit 40 via a buffer. Thus, the power consumed by the resistor 332 can be reduced. By inserting such a buffer, the value of the resistor 332 can be increased, and the current that constantly flows through the resistor 332 can be reduced.

Hereinafter, the voltage selection circuit 33a that maintains the level of the minimum voltage _{IVdd at} a constant level in the locked state will be described.

FIG. 13 shows a configuration of the improved voltage selection circuit 33a.
The voltage selection circuit 33a includes a state holding circuit 334 and a switch circuit 335 in addition to the configuration of the voltage selection circuit 33 shown in FIG.

The state holding circuit 334 includes D flip-flops 334f-1 to 334f-3.
34f-5, AND circuits 334a-1 to 334a-7, and OR circuit 334o
-1 to 334o-4.

Each of the D flip-flops 334f-1 to 334f-5 is synchronized with the rising edge of the output pulse signal P2,
Data is input from D flip-flops 331f-1 to 331f-5. Therefore, the state holding circuit 334 holds the state immediately before the bidirectional shift control circuit 331. Hereinafter, the state immediately before the bidirectional shift control circuit 331 is referred to as “previous state”, and the current state of the bidirectional shift control circuit 331 is referred to as “current state”.

The state holding circuit 334 outputs control signals S11 to S15 based on the control signals S1 to S5. The control signals S11 to S15 go to a high level when the following conditions are satisfied, and go to a low level otherwise.

S11: S1 in the previous state is at the high level, and S1 in the current state is at the high level.

S12: (S2 in the previous state is high level and S1 in the current state is high level) or (S1 in the previous state is high level and
(Current state S2 is high level.)

S13: (S3 in the previous state is high level and S2 in the current state is high level) or (S2 in the previous state is high level and
(Current state S3 is high level.)

S14: (S4 in the previous state is high level and S3 in the current state is high level) or (S3 in the previous state is high level and
S4 in the current state is high level).

S15: S5 in the previous state is high level, or S5 in the current state is high level.

One of the control signals S1 to S5 goes high, and the position of the control signal that goes high in the previous state and the current state is shifted by one. Therefore, according to the logic of the control signals S11 to S15 described above, the control signals S11 to S11
The control signal which is at a high level out of 15 is one of the control signals S1 to S5 which were at a high level in the previous state and the control signal which is at the high level in the current state.
A control signal corresponding to the higher voltage of any of the control signals S1 to S5.

The switch circuit 335 includes a plurality of switch elements 335-1 to 33-33.
5-5. A corresponding voltage is supplied to one end of each of the switch elements 335-1 to 335-5.
The control signals S11 to S15 are used to control on / off of the switch elements 335-1 to 335-5, respectively. Only the switch element corresponding to the high-level control signal is turned on, and the voltage corresponding to the switch element is selectively output.

Thus, the voltage IV _dd ′ is output from the switch circuit 335. The voltage IV _dd ′ is supplied to the power supply circuit 50. On the other hand, the voltage IV output from the switch circuit 333
_dd is supplied to the delay circuit 40.

FIG. 14 shows the transition of the voltage output from the improved voltage selection circuit 33a during the period from the transient state to the locked state. In FIG. 14, the thin line indicates the voltage selection circuit 33a.
Represents the transition of the voltage IV _dd 'supplied to the power supply circuit 50, and the bold line represents the transition of the voltage IV _dd supplied from the voltage selection circuit 33a to the delay circuit 40. As shown in FIG. 14, the voltage IV _dd ′ is maintained at a constant level in the locked state.

FIG. 15A shows a configuration of the improved state holding circuit 334a. The state holding circuit 334a is a state holding circuit shown in FIG.
334 has a simpler configuration. The state holding circuit 334
It can be replaced by the state holding circuit 334a.

The state holding circuit 334a includes D flip-flops 334f-1 to 334f-1.
334f-5 and an OR circuit 334o-1.

To each of the D flip-flops 334f-1 to 334f-5, data is input from the D flip-flops 331f-1 to 331f-5 in synchronization with the rising edge of the pulse signal P4.

The pulse signal P4 is obtained by performing an OR operation on the negation of the determination signal K1 and the pulse signal P3 (see FIG. 15B). That is, the pulse signal P4 is output according to the pulse signal P3 only during a period when the determination signal K1 is at the high level. While the determination signal K1 is at the high level, the voltage IV
_This corresponds to the period when _dd rises.

The pulse signal P3 is a signal having a phase different from the phase of the input pulse signal P1, as shown in FIG. 15B. The pulse signal P3 can be generated by the input pulse signal generation circuit 31.

Thus, the D flip-flops 334f-1 to 334f-5
Is updated when the voltage IV _dd output from the switch circuit 333 increases.

Therefore, the voltage IV _dd ′ output from the switch circuit 335
Is updated to the value of the voltage _IVdd when the voltage _IVdd output from the switch circuit 333 rises, and is not updated otherwise. The initial value of the voltage IV _dd 'is equal to the initial value of the voltage IV _dd.

FIG. 16 shows transition of the voltage output from the voltage selection circuit 33a including the improved state holding circuit 334a during the period from the transition state to the lock state. In FIG. 16, a thin line represents a transition of the voltage IV _dd ′ supplied from the voltage selection circuit 33a to the power supply circuit 50, and a thick line represents a transition of the voltage IV _dd supplied from the voltage selection circuit 33a to the delay circuit 40. Represent. As shown in FIG. 16, the voltage IV _dd ′ is maintained at a constant level in the locked state.

FIG. 17 shows a configuration of the system 1 according to the first embodiment of the present invention in a different expression from FIG. 17, the same components as those of the system 1 shown in FIG. 1 are denoted by the same reference numerals.

The function of the minimum voltage detection circuit 30 in FIG. 1 is divided into an input pulse signal generation circuit 31 and a delay-voltage conversion circuit 30a in FIG.

The input pulse signal generation circuit 31 intermittently generates the input pulse signal P1 according to the frequency of the clock CLK. The input pulse signal P1 has a pulse width representing a target delay amount. The input pulse signal P1 is supplied to the delay circuit 40 and the delay / voltage conversion circuit 30a.

The input pulse signal P1 is supplied to the delay-voltage conversion circuit 30a.
And the output pulse signal P2 output from the delay circuit 40. The delay-voltage conversion circuit 30a outputs a voltage in accordance with the delay of the output pulse signal P2 with respect to the input pulse signal P1.
Outputs IV _dd .

FIG. 18 shows a configuration of the delay amount-voltage conversion circuit 30a. The delay amount-voltage conversion circuit 30a includes a delay amount determination circuit 32 and a voltage selection circuit 33. The functions and operations of the delay amount determination circuit 32 and the voltage selection circuit 33 are the same as those shown in FIG. Therefore, their description is omitted here.

Those skilled in the art will understand that the system 1 shown in FIG. 1 and the system 1 shown in FIG. 17 realize the same function and operation.

The function realized by the input pulse signal generation circuit 31, the delay circuit 40, and the delay-voltage conversion circuit 30a receives a clock CLK as an input and provides a voltage IV _dd corresponding to the frequency of the clock CLK as an output. It can be understood that it is. That is, the frequency-voltage conversion circuit 21 shown by a broken line in FIG. 17 converts the frequency (input) of the clock CLK into a voltage IV _dd (output) according to predetermined input / output characteristics. Here, the voltage IV _dd, in which the target circuit 10 is obtained by adding a margin ΔV to the minimum voltage V _min operable. The minimum voltage _Vmin is determined according to the frequency of the clock CLK. Here, ΔV ≧ 0.

When ΔV = 0 (that is, IV _dd = V _min ), a margin ΔV is added between the frequency-voltage conversion circuit 21 and the target circuit 10 to the voltage IV _dd output from the frequency-voltage conversion circuit 21. It is preferable to provide a circuit that performs the operation.

In the first embodiment, using the delay control signal _SCTL2 to adjust the slope of the delay time-power supply voltage characteristic of the delay circuit 40 means adjusting the slope of the input / output characteristic of the frequency-voltage conversion circuit 21. I do. The power supply voltage of the delay circuit 40 is a voltage
IV equal to _dd , delay time by delay circuit 40 and clock CL
This is because there is a reciprocal relationship with the frequency of K. Similarly, adjusting the offset amount of the delay time-power supply voltage characteristic of the delay circuit 40 using the delay control signal _SCTL1 means adjusting the offset amount of the input / output characteristic of the frequency-voltage conversion circuit 21. I do. As described above, the frequency-voltage conversion circuit 21 provides an embodiment of the frequency-voltage conversion circuit configured to be able to adjust the slope and the offset amount of the input / output characteristics thereof.

As described above, the delay time of the delay circuit 40 and the adjustment of the slope of the power supply voltage characteristic and the offset amount are determined by the number N1 of delay stages of the delay block 41 included in the delay circuit 40 and the delay block.
This is achieved by adjusting the number of delay stages N2 of 42. For the configuration of the delay block 41 and the configuration of the delay block 42, see FIG.

For example, the slope of the delay time-power supply voltage characteristic of the delay circuit 40 is adjusted by determining the number of delay stages N2 of the delay block 42 according to (Equation 1).

N2 = n · (K _T / K _INIT ) (Equation 1) Here, K _INIT is such that the pulse width of the input pulse signal P1 is equal to one cycle of the clock CLK, and the number of delay stages of the delay block 42 is is n, and the delay time of the delay circuit 40 when the number of delay stages of the delay block 41 is 0 - represents the slope of the power supply voltage characteristic, K _T is the delay time of the target circuit 10 - represents the slope of the power supply voltage characteristic , N represent the initial number of delay stages of the delay block 42.

After determining the number of delay stages N2 of the delay block 42,
By determining the number of delay stages N1 of the delay block 41 according to (Equation 2), the offset amount of the delay time-power supply voltage characteristic of the delay circuit 40 is adjusted.

N1 = τ / t ₀ (Equation 2) Here, τ is a frequency − within a predetermined frequency range.
The minimum offset amount required for the input / output characteristics of the voltage conversion circuit 21 to be located above the characteristics of the target circuit 10, and t ₀ represents the delay time per stage of the delay block 41.

As described above, the power management circuit 20 includes the frequency-voltage conversion circuit 21 adaptable to the target circuit 10 having an arbitrary characteristic. This means that the power management circuit 20 can be provided as a core of the power management circuit that supplies the optimum operating voltage V _OP according to the target circuit 10.

FIG. 19 shows a configuration of the system 1 when the power management circuit 20 is used as a core of the power management circuit. The system 1 further includes a fractional frequency divider (PLL) 65 in addition to the components shown in FIG. A control signal for setting a multiplication number is input to a fractional frequency divider (PLL) 65 via a terminal 63.

The fractional frequency divider (PLL) 65 generates an internal clock CLK by multiplying the system clock SCLK. The internal clock CLK is supplied to the target circuit 10 and the input pulse signal generation circuit 3
1 and supplied to. The frequency of the internal clock CLK is changed by changing the multiple set in the fractional frequency divider (PLL) 65. This makes it possible to control the operating frequency of the target circuit 10.

The optimal frequency-power supply voltage characteristic for the target circuit 10 can be realized by adjusting the number of delay stages of the delay circuit 40 as described above.

In the above-described first embodiment, the method of adjusting the input / output characteristics of the frequency-voltage conversion circuit 21 under the assumption that the maximum delay path (critical path) of the target circuit 10 is one has been described. However, in an actual LSI, the critical path of the target circuit 10 may change according to the power supply voltage. For example, in an LSI having a complicated gate configuration in which a RAM, a ROM, and the like are integrated into one chip, the critical path of the target circuit 10 often changes according to the power supply voltage.

There are various types of delay paths of the target circuit 10. For example, delay paths caused by the number of gate stages, RAM, R
There is a delay path due to wiring delay as occurs in the OM.

Also, there is a gate such as a multi-input NAND in which the delay amount when the power supply voltage is reduced is larger than that of a normal gate.

Thus, in an actual LSI, the target circuit 10 may have a plurality of critical paths for each power supply voltage.

Hereinafter, the principle of adjusting the input / output characteristics of the frequency-voltage conversion circuit 21 when the target circuit 10 has a plurality of critical paths depending on the power supply voltage will be described with reference to FIGS. 20A to 20E.

In FIG. 20A, a straight line A indicates a delay time-power supply voltage characteristic corresponding to the first critical path of the target circuit 10. A straight line B indicates a delay time-power supply voltage characteristic corresponding to the second critical path of the target circuit 10. The delay time-power supply voltage characteristic is generally represented by a curve. However, here, the delay time-power supply voltage characteristic is represented by a straight line approximation. This is because any curve can be approximated by an appropriate number of straight lines.

Using the frequency-voltage conversion circuit 21 (FIG. 17), a delay circuit
It is possible to adjust the number of delay units included in the delay circuit 40 so that the delay time-power supply voltage characteristic of 40 (FIG. 17) substantially matches the straight line A. In FIG. 20B, the dashed line indicates the delay time-power supply voltage characteristic of the delay circuit 40 thus adjusted. However, according to such adjustment, if the delay time (= clock cycle) is smaller than the time t1, the target circuit 10 malfunctions due to the second critical path.

Similarly, using the frequency-to-voltage conversion circuit 21 of FIG. 17, the delay unit included in the delay circuit 40 (FIG. 17) is changed so that the delay time-power supply voltage characteristic of the delay circuit 40 (FIG. 17) substantially matches the straight line B. It is possible to adjust the number of stages. In FIG. 20C, the dashed line indicates the delay time-power supply voltage characteristic of the delay circuit 40 adjusted as described above. However, according to such adjustment, if the delay time (= clock cycle) is longer than the time t1, the target circuit 10 malfunctions due to the first critical path.

In order for the target circuit 10 to operate normally for all clock cycles in which the target circuit 10 can operate, FIG.
The delay time-power supply voltage characteristic indicated by the dashed line may be realized. Such a delay time-power supply voltage characteristic can be realized using the frequency-voltage conversion circuit 21 (FIG. 17). However, according to the delay time-power supply voltage characteristic shown in FIG. 20D, the power supply voltage V2 larger than necessary for the clock cycle t1 is applied to the target circuit 10. As a result, useless power is consumed.

In order to normally operate the target circuit 10 for all clock cycles in which the target circuit 10 can operate and to prevent useless power from being consumed, a delay time indicated by a broken line in FIG. It is necessary to realize power supply voltage characteristics.

FIG. 21 shows a modification of the frequency-voltage conversion circuit 21 (FIG. 17). The frequency-voltage conversion circuit 21 of FIG. 21 realizes the delay time-power supply voltage characteristic indicated by the broken line in FIG. 20E.

21 includes a delay circuit 40a, a delay circuit 40b, and an OR circuit 40c instead of the delay circuit 40. The configuration of the delay circuits 41a and 40b
The configuration is the same as that of the forty. Regarding the configuration of the delay circuit 40,
Please refer to FIG.

The delay time-power supply voltage characteristic of the delay circuit 40a is adjusted in advance so as to substantially match the straight line A shown in FIG. 20A. Such adjustment is achieved by inputting a control signal to the delay circuit 40a via the terminals 61a and 62a. The delay time-power supply voltage characteristic of the delay circuit 40b is adjusted in advance so as to substantially match the straight line B shown in FIG. 20A. Such adjustment is achieved by inputting a control signal to the delay circuit 40b via the terminals 61b and 62b. As described above, the delay time-power supply voltage characteristic of the delay circuit 40a and the delay circuit 4
The delay time-power supply voltage characteristic of 0b can be adjusted independently of each other.

The input pulse signal generation circuit 31 generates an input pulse signal P1 having a pulse width representing a target delay amount. Here, the target delay amount is the reciprocal of the frequency of the clock CLK (ie,
(The length of one cycle of the clock CLK = clock cycle). The input pulse signal P1 is supplied to the delay circuit 40a and the delay circuit 40b.
Entered as

The delay circuit 40a delays the input pulse signal P1 according to the voltage _IVdd output from the delay-voltage conversion circuit 30a.
The input pulse signal P1 delayed by the delay circuit 40a is
The output pulse signal PA is output to the OR circuit 40c.

The delay circuit 40b delays the input pulse signal P1 according to the voltage _IVdd output from the delay-voltage conversion circuit 30a.
The input pulse signal P1 delayed by the delay circuit 40b is
The output pulse signal PB is output to the OR circuit 40c.

The OR circuit 40c calculates a logical sum of the output pulse signal PA and the output pulse signal PB, and outputs the result to the output pulse signal P2
And outputs it to the delay-voltage conversion circuit 30a.

As described with reference to FIGS. 8A to 8C, the delay amount-voltage conversion circuit 30a controls the minimum voltage IV _dd so that the rising edge of the input pulse signal P1 matches the falling edge of the output pulse signal P2. Feedback control.

FIG. 22A shows the waveform of each pulse signal when the clock cycle is smaller than time t1. Clock cycle is time
If it is smaller than t1, the straight line B represents the critical path as shown in FIG. 20A. Therefore, the amount of delay by the delay circuit 40b is larger than the amount of delay by the delay circuit 40a.
As a result, the falling edge of the output pulse signal P2 coincides with the falling edge of the output pulse signal PB.

FIG. 22B shows the waveform of each pulse signal when the clock cycle is longer than time t1. Clock cycle is time
If it is greater than t1, the straight line A represents the critical path, as shown in FIG. 20A. Therefore, the amount of delay by the delay circuit 40a is larger than the amount of delay by the delay circuit 40b.
As a result, the falling edge of the output pulse signal P2 coincides with the falling edge of the output pulse signal PA.

In this way, when the clock cycle is smaller than the time t1, the minimum voltage IV _dd is feedback-controlled so that the rising edge of the input pulse signal P1 and the falling edge of the output pulse signal PB match, and the clock cycle is time-dependent. If t1 is larger than t1, the minimum voltage _IVdd is feedback-controlled so that the rising edge of the input pulse signal P1 and the falling edge of the output pulse signal PA match. By such control, a delay time-power supply voltage characteristic indicated by a broken line in FIG. 20E is realized.

As described above, according to the frequency-voltage conversion circuit 21 shown in FIG. 21, the delay time-power supply voltage characteristic obtained by synthesizing the delay time-power supply voltage characteristic corresponding to the two different critical paths substantially matches the delay time-power supply voltage characteristic. And delay circuit 40
The delay time-power supply voltage characteristics of a and 40b can be adjusted. This means that the input / output characteristics of the frequency-voltage conversion circuit 21 can be adjusted to correspond to the combined delay time-power supply voltage characteristics. Therefore, even when the target circuit 10 has two different critical paths, the frequency-voltage conversion circuit 21
The minimum voltage corresponding to the frequency of K can be output to the target circuit 10.

Note that even when the target circuit 10 has three or more critical paths, the frequency-voltage conversion circuit 21
The minimum voltage corresponding to the frequency of K can be output to the target circuit 10. When the target circuit 10 has three or more critical paths, three or more delay circuits respectively corresponding to the three or more critical paths are arranged in parallel, and the logical sum of the outputs of the delay circuits is calculated as the delay amount. −Voltage conversion circuit 30
What is necessary is just to input in a.

Embodiment 2 FIG. 23 shows a configuration of a system 2 according to Embodiment 2 of the present invention. In FIG. 23, the system 1 shown in FIG.
The same constituent elements as those described in the above are denoted by the same reference numerals.

In the system 2, the target circuit 10 and the target circuit 10 are clocked.
Target circuit for minimum operating voltage V _OP operable at CLK frequency
And a power management circuit 20a for supplying the power management circuit 20a to the power management circuit 20. The system 2 can be formed on a single semiconductor chip.

The target circuit 10 includes, for example, a digital signal processor (DS)
P) or a central processing unit (CPU). The target circuit 10 is
It operates according to the clock CLK.

The power management circuit 20a includes a frequency-voltage conversion circuit 21a and a power supply circuit 50.

The frequency-voltage conversion circuit 21a receives the clock CLK as an input, and outputs and provides a voltage _IVdd according to the frequency of the clock CLK. The frequency-voltage conversion circuit 21a is configured such that the input / output characteristics of the frequency-voltage conversion circuit 21a can be adjusted based on two independent parameters. One of the two parameters is the slope of the input / output characteristics of the frequency-voltage conversion circuit 21a, and the other is the offset amount of the input / output characteristics of the frequency-voltage conversion circuit 21a. The input / output characteristics of the frequency-voltage conversion circuit 21a are adjusted such that the voltage _IVdd output from the frequency-voltage conversion circuit 21a substantially matches the minimum voltage at which the target circuit 10 can operate at the frequency of the clock CLK. .

Voltage IV output from frequency-voltage conversion circuit 21a
_dd is supplied to the power supply circuit 50.

The power supply circuit 50 operates based on the operating voltage V _OP based on the voltage IV _dd.
Generate For example, the power supply circuit 50, a voltage IV _dd as the target voltage may be a voltage converter for converting a power supply voltage V _dd to the operating voltage V _OP. Such voltage converters can convert DC power supply voltage V _dd (eg, 3V) to high efficiency (eg, 95%)
It is preferable to use a DC / DC converter that converts the voltage into a DC operating voltage _VOP . This is to reduce the power consumption of the entire power management circuit 20. Alternatively, the power supply circuit 50
May be an operational amplifier.

However, the power supply circuit 50 is
Is not required to be included. Instead of generating the operating voltage V _OP based on the voltage IV _dd , the frequency-voltage conversion circuit 2
It may be supplied to the target circuit 10 a voltage IV _dd output from 1a as the operating voltage V _OP.

The frequency-voltage conversion circuit 21a includes an input pulse signal generation circuit 131, a delay circuit 140, and a delay-voltage conversion circuit 30a.

The input pulse signal generation circuit 131 intermittently generates the input pulse signal P1 according to the frequency of the clock CLK. The input pulse signal P1 has a pulse width representing a target delay amount. The pulse width of the input pulse signal P1 is determined as a function of the frequency of the clock CLK. The function is defined by (Equation 3).

Pw = α / f + β (Equation 3) Here, Pw represents the pulse width of the input pulse signal P1, and f
Represents the frequency of the clock CLK, and α and β represent constants.
As will be described later, the slope of the input / output characteristic of the frequency-voltage conversion circuit 21a is adjusted by adjusting the value of the constant α, and the offset amount of the input / output characteristic of the frequency-voltage conversion circuit 21a is Adjusted by adjusting the value.

A control signal for adjusting the value of the constant α is input via the terminal 161. In addition, a control signal for adjusting the value of the constant β is input via the terminal 162.

The voltage _IVdd output from the frequency-voltage conversion circuit 21a is supplied to the delay circuit 140. The delay circuit 140 has a voltage IV
_The input pulse signal P1 is delayed according to _dd . Delay circuit 14
The output of 0 is supplied to the delay amount-voltage conversion circuit 30a as the output pulse signal P2. The delay circuit 140 may include, for example, a plurality of delay units connected in series. However, unlike the delay circuit 40 in the first embodiment, it is not necessary to control the number of delay units through which the input pulse signal P1 passes among the plurality of delay units by using the delay control signal.
In the second embodiment, the input / output characteristics of the frequency-voltage conversion circuit 21a can be adjusted by adjusting the values of the constants α and β used to determine the pulse width of the input pulse signal P1. It is.

The delay-voltage conversion circuit 30a outputs the voltage _IVdd according to the delay of the output pulse signal P2 with respect to the input pulse signal P1. The configuration of the delay amount-voltage conversion circuit 30a is as shown in FIG.

Next, referring to FIGS. 24A and 24B, the input pulse signal P1
Frequency-voltage conversion circuit by adjusting the pulse width of
The principle of adjusting the input / output characteristics of 21a will be described.

24A and 24B, the solid line shows the initial delay time-power supply voltage characteristic of the delay circuit 140. The delay time-power supply voltage characteristic is generally represented by a hyperbola as shown in FIG. However, in FIGS. 24A and 24B, the delay time-power supply voltage characteristic is represented by a straight line approximation. This is because any curve can be approximated by an appropriate number of straight lines. The delay circuit 140 operates with a shorter delay time as the power supply voltage is higher, and operates with a longer delay time as the power supply voltage is lower. Delay circuit 140 operates using voltage _IVdd as a power supply voltage.

Hereinafter, the principle of adjusting the slope of the delay time-power supply voltage characteristic will be described with reference to FIG. 24A.

In FIG. 24A, point A on the solid line indicates that the power supply voltage corresponding to the target delay time t is V (t).
That is, the coordinates of the point A are (V (t), t). On the other hand, the point B on the solid line indicates that the power supply voltage corresponding to the target delay time t / 2 is V (t / 2). That is,
The coordinates of the point B are (V (t / 2), t / 2). Accordingly, the slope K _AB of a straight line (solid line) connecting the point A and the point B is represented by (Equation 4)
Required by

K _AB = (t / 2−t) / {V (t / 2) −V (t)} (Equation 4) In FIG. 24A, the power supply voltage corresponding to the target delay time t is V (t / 2 ), The converted delay time-power supply voltage characteristic of the delay circuit 140 can be obtained. Converted delay time-
The power supply voltage characteristics are indicated by broken lines in FIG. 24A. Such conversion is achieved by inputting the input pulse signal P1 having a pulse width t / 2 with respect to the target delay time t to the delay circuit 140. With such a conversion,
Point A is converted to point A 'and point B is converted to point B'.

A point A 'on the broken line indicates that the power supply voltage corresponding to the target delay time t is V (t / 2). That is, point A '
Is (V (t / 2), t). On the other hand, a point on the broken line
B ′ is such that the power supply voltage corresponding to the target delay time t / 2 is V (t / 4)
It represents that. That is, the coordinates of the point B ′ are
(V (t / 4), t / 2). Therefore, the slope _{KA'B '} of the straight line (broken line) connecting the points A' and B 'is obtained by (Equation 5).

_{KA'B '} = (t / 2-t) / {V (t / 4) -V (t / 2)} = (t / 2-t) / {(1/2)} V (t / 2 ) −V (t)｝ = 2 · K _AB (Equation 5) As described above, by inputting the input pulse signal P1 having the pulse width t / 2 with respect to the target delay time t to the delay circuit 140, The slope of the converted delay time-power supply voltage characteristic of the delay circuit 140 is twice the slope of the initial delay time-power supply voltage characteristic of the delay circuit 140. Similarly, the target delay time t
By inputting an input pulse signal P1 having a pulse width t / 3 to the delay circuit 140, the slope of the converted delay time-power supply voltage characteristic of the delay circuit 140 is changed to the initial delay time of the delay circuit 140-power supply. It can be three times the slope of the voltage characteristic.

Hereinafter, the principle of adjusting the offset amount of the delay time-power supply voltage characteristic will be described with reference to FIG. 24B.

In FIG. 24B, the point A on the solid line indicates that the power supply voltage corresponding to the target delay time t is V (t).
That is, the coordinates of the point A are (V (t), t). On the other hand, the point B on the solid line indicates that the power supply voltage corresponding to the target delay time (t + 5) is V (t + 5). That is, the coordinates of the point B are (V (t + 5), t + 5).

In FIG. 24B, the delay time of the delay circuit 140 is set so that the power supply voltage corresponding to the target delay time t becomes V (t + 5).
When the power supply voltage characteristics are converted, a converted delay time-power supply voltage characteristic of the delay circuit 140 is obtained. The converted delay time-power supply voltage characteristic is indicated by a broken line in FIG. 24B. Such conversion is achieved by inputting an input pulse signal P1 having a pulse width (t + 5) with respect to the target delay time t to the delay circuit 140. By such conversion, point A is converted to point A ', and point B is converted to point B'.

A point A ′ on the broken line indicates that the power supply voltage corresponding to the target delay time t is V (t + 5). That is, the point
The coordinates of A ′ are (V (t + 5), t). On the other hand, a point B 'on the broken line indicates that the power supply voltage corresponding to the target delay time (t + 5) is V (t + 10). That is, the point
The coordinates of B ′ are (V (t + 10), t + 5).

Thus, the pulse width (t +
By inputting the input pulse signal P1 having 5) to the delay circuit 140, the delay time-power supply voltage characteristic of the delay circuit 140 translates by -5 (nsec) along the Y-axis direction. Similarly, the pulse width (t−10) with respect to the target delay time t
Is input to the delay circuit 140, the delay time-power supply voltage characteristic of the delay circuit 140 is changed to Y.
It can be translated by +10 (nsec) along the axial direction. The amount of movement of the delay time-power supply voltage characteristic along the Y-axis direction is referred to as the delay time-offset amount of the power supply voltage characteristic.

Thus, the pulse width Pw of the input pulse signal P1 is given by (Equation 6).

Pw = α · t + β (Equation 6) Here, α and β are arbitrary constants. By adjusting the constant α, the slope of the delay time-power supply voltage characteristic of the delay circuit 140 is adjusted. By adjusting the constant β, the offset amount of the delay time-power supply voltage characteristic of the delay circuit 140 is adjusted. The input pulse signal P1 having the pulse width Pw is
It is generated by the input pulse signal generation circuit 131.

Here, if f is the frequency of the clock CLK, t = 1 / f
There is a relationship. Therefore, it can be seen that (Equation 3) and (Equation 6) are equivalent.

In the second embodiment, the delay circuit 140
Adjusting the slope of the delay time-power supply voltage characteristic means adjusting the slope of the input / output characteristic of the frequency-voltage conversion circuit 21a. This is because the power supply voltage of the delay circuit 140 is equal to the voltage _IVdd , and the delay time of the delay circuit 140 and the frequency of the clock CLK have an inverse relationship. Similarly, adjusting the offset amount of the delay time-power supply voltage characteristic of the delay circuit 140 using the constant β is equivalent to the frequency-voltage conversion circuit.
This means that the offset amount of the input / output characteristics of 21a is adjusted. As described above, the frequency-voltage conversion circuit 21a provides one embodiment of the frequency-voltage conversion circuit configured to be able to adjust the slope and the offset amount of the input / output characteristics thereof.

Next, referring to FIG. 25, the voltage IV output from frequency-voltage conversion circuit 21a with respect to the frequency of clock CLK
A method of adjusting the input / output characteristics of the frequency-voltage conversion circuit 21a so that _dd substantially matches the minimum voltage at which the target circuit 10 can operate at that frequency of the clock CLK will be described.

Step 1: Obtain the characteristic slope of the target circuit 10. The inclination of the characteristic of the target circuit 10 is obtained by measuring the minimum power supply voltage at which the target circuit 10 operates at least for at least two operating frequencies of the clock CLK, and measuring those measurement points on a graph showing a delay time-power supply voltage characteristic. And the slope of a straight line connecting those measurement points is obtained.
For example, the voltage V (1 / f _A ) is measured as the minimum power supply voltage at which the target circuit 10 operates at the frequency f _A of the clock CLK, and the minimum power supply voltage at which the target circuit 10 operates at the frequency f _B of the clock CLK. Assume that voltage V (1 / f _B ) has been measured.
In this case, a point A having coordinates (V (1 / f _A ), 1 / f _A ) and a point B having coordinates ((V (1 / f _B ), 1 / f _B )) are defined by a delay time−power supply. When plotted on a graph showing voltage characteristics, FIG. 25
It becomes as shown in. In Figure 25, the straight line L _T represents the characteristics of the target circuit 10. The slope K _TAB of the characteristic of the target circuit 10 is
It is obtained according to (Equation 7).

K _TAB = (1 / f _A −1 / f _B ) / {(V (1 / f _A ) −V (1 / f _B )} (Equation 7) Step 2: The frequency-voltage conversion circuit 21a The input / output characteristics of the frequency-voltage conversion circuit 21a are adjusted so that the slope K of the input / output characteristics substantially matches the slope K _TAB of the characteristics of the target circuit 10. For example, the frequency is adjusted so as to satisfy (Equation 8). -The input / output characteristics of the voltage conversion circuit 21a may be adjusted.

| K−K _TAB | <ε (Equation 8) Here, ε is the absolute value of the error between the slope K of the input / output characteristic of the frequency-voltage conversion circuit 21a and the slope K _TAB of the characteristic of the target circuit 10. It is a constant representing the target value.

Such adjustment is achieved by determining the pulse width Pw of the input pulse signal P1 according to (Equation 9). Figure
In 25, the straight line L _1, the frequency after adjusting the inclination K -
5 shows an example of the input / output characteristics of the voltage conversion circuit 21a.

Pw = (K _INIT / K _TAB ) · t (Equation 9) where K _INIT is the initial delay time of the delay circuit 140 when the pulse width Pw of the input pulse signal P1 is equal to one cycle of the clock CLK. -Represents the slope of the power supply voltage characteristic, K _TAB represents the slope of the characteristic of the target circuit 10, and t represents the reciprocal (= 1 / f) of the frequency f of the clock CLK.

Step 3: The offset amount of the input / output characteristics of the frequency-voltage conversion circuit 21a is adjusted so that the target circuit 10 can operate in the predetermined frequency range of the clock CLK. Such adjustment is performed by changing the pulse width Pw of the input pulse signal P1 (Equation 1).
0).

Pw = (K _INIT / K _TAB ) · t−τ (Equation 10) Here, τ is a frequency − within a predetermined frequency range.
It represents the minimum offset amount necessary for the input / output characteristics of the voltage conversion circuit 21a to be positioned above the characteristics of the target circuit 10. That is, the offset amount τ is determined by a predetermined frequency range.
In the case where f _min is equal to or more than f _{max and} (Equation 11) is satisfied, V _L2 (y) is determined to be minimum.

V _LT (y) ≦ V _L2 (y) (f _min ≦ y ≦ f _max ) (Equation 11) Here, V _LT is a function x = V indicating the characteristic of the target circuit 10.
_LT (y), and _VL2 is the frequency-to-voltage conversion circuit 2 after adjustment.
A function x = V _L2 (y) indicating the input / output characteristic of 1a is represented. FIG.
In the straight line L _2, the frequency after adjusting the inclination K and the offset amount tau - represents an example of an input-output characteristic of the voltage converter circuit 21a.

If K _INIT / K _TAB = α, −τ = β, then (Equation 10)
Is equivalent to (Equation 6).

Note that adjusting the pulse width Pw of the input pulse signal P1 and adjusting the number of stages of the delay units included in the delay circuit as described in the first embodiment may be used together. In this manner, the input / output characteristics of the frequency-voltage conversion circuit 2a can be made to substantially match the characteristics of the target circuit 10.

As described above, the power management circuit 20a includes the frequency-voltage conversion circuit 21a adaptable to the target circuit 10 having arbitrary characteristics. This means that the power management circuit 20a can be provided as a core of a power management circuit that supplies an optimum operating voltage according to the target circuit 10.

FIG. 26 shows the configuration of the system 2 when the power management circuit 20a is used as a core of the power management circuit. System 2 further includes a fractional frequency divider (PLL) 165 in addition to the components shown in FIG. A control signal for setting a multiplication number is input to a fractional frequency divider (PLL) 165 via a terminal 163.

The fractional frequency divider (PLL) 165 generates the internal clock CLK by multiplying the system clock SCLK. The internal clock CLK is generated by the target circuit 10 and the input pulse signal generation circuit 1.
31 and supplied to. The frequency of the internal clock CLK is changed by changing the multiplier set in the fractional frequency divider 165 (PLL). This makes it possible to control the operating frequency of the target circuit 10.

The fractional frequency divider (PLL) 165 is a fractional frequency divider 165 (PLL).
The high-speed clock HCLK output from a VCO (not shown) included in L) is supplied to the input pulse signal generation circuit 131. In this system, the clock CLK is the clock H
It is assumed that the clock is obtained by dividing CLK. The value of the constant α can be adjusted in the input pulse signal generation circuit 131 using the clock CLK and the clock HCLK.

Further, the system clock SCLK is input to the input pulse signal generation circuit 131. The system clock SCLK is
The input pulse signal generation circuit 131 is used to adjust the value of the constant β. This is because the system clock SCLK does not depend on the temperature or the process.

The optimum frequency-power supply voltage characteristic for the target circuit 10 can be realized by adjusting the pulse width of the input pulse signal P1 using the clock described above.

Hereinafter, the device 3 for automatically adjusting the input / output characteristics of the frequency-voltage conversion circuit 21a in the system 2 including the target circuit 10 and the frequency-voltage conversion circuit 21a will be described. The system 2 and the device 3 can be formed on a single semiconductor chip.

The target circuit 10 operates according to the clock CLK. The frequency-voltage conversion circuit 21a receives the clock CLK as an input, and provides a voltage _IVdd according to the frequency of the clock CLK as an output. The power supply circuit 50 supplies the operating voltage V _OP of the target circuit 10 to the target circuit 10 according to the voltage _IVdd . Alternatively, without using the power supply circuit 50, the frequency - may supply voltage IV _dd output from the voltage conversion circuit 21a to the target circuit 10 as the operating voltage V _OP of the target circuit 10.

FIG. 27 shows the configuration of the device 3. The device 3 includes an operation circuit 18
0, a matching circuit 181 and an adjusting circuit 182.

The operation circuit 180 actually operates the target circuit 10 on the input vector at the frequency of the clock CLK, and outputs the operation result. As the input vector, one that realizes the longest delay path is used.

Collation circuit 181 collates the operation result of target circuit 10 with the expected value, and outputs the collation result. The expected value is the target circuit
It is stored in advance in a memory (not shown) in the device 3 based on the ten operation specifications. The verification result is represented by either a normal operation (OK) or an abnormal operation (NG).

Thus, the operation circuit 180 and the matching circuit 181 is used, the number in relation to the frequency of the operating voltage V _OP and the clock CLK of the target circuit 10, a determining self-diagnosis function whether the target circuit 10 is operating normally are doing.

If the collation result is normal operation (OK), the adjustment circuit
182 raises the operating voltage V _OP by a predetermined voltage ΔV.
Conversely, when the comparison result indicates an abnormal operation (NG), the adjustment circuit 182 lowers the operating voltage _VOP by a predetermined voltage ΔV. By such feedback control, the adjustment circuit 18
2 detects the minimum voltage at which the target circuit 10 can operate with respect to the frequency of the clock CLK. The adjustment circuit 182 detects such a minimum voltage for at least two frequencies of the clock CLK. Thereby, the adjustment circuit 182
The characteristics of the target circuit 10 can be detected.

Next, the adjustment circuit 182 adjusts the frequency so that the voltage _IVdd output from the frequency-voltage conversion circuit 2a with respect to the frequency of the clock CLK substantially matches the minimum voltage at which the target circuit 10 can operate at that frequency. -Adjust the slope and offset amount of the input / output characteristics of the voltage conversion circuit 21a. The method of adjusting the slope and the offset amount of the input / output characteristics of the frequency-voltage conversion circuit 21a is the same as the method described with reference to FIG.

Alternatively, the adjustment circuit 182 includes the frequency-voltage conversion circuit 21a
First Embodiment
The adjustment may be made by adjusting the number of stages of the delay unit included in the delay circuit as described in (1). Further, the adjustment circuit 182 may use both the adjustment of the pulse width Pw of the input pulse signal P1 and the adjustment of the number of delay units included in the delay circuit.

The preferred embodiment of the present invention has been described above. However, the above embodiments are not intended to limit the scope of the present invention. Those skilled in the art will appreciate that modifications and changes can be made to the embodiments described above. Such modifications and alterations are to be construed as falling within the scope of the invention.

INDUSTRIAL APPLICABILITY According to the frequency-voltage conversion circuit of the present invention, the input / output characteristics of the frequency-voltage conversion circuit can be adjusted to adapt to the characteristics of the target circuit. This makes it possible to supply an appropriate voltage to any target circuit.

According to the system including the frequency-voltage conversion circuit of the present invention, it is possible to supply the minimum operating voltage necessary for the target circuit to operate normally. Thereby, power consumption is reduced.

According to the method and apparatus for adjusting the input / output characteristics of the frequency-to-voltage conversion circuit of the present invention, the input / output characteristics of the frequency-to-voltage conversion circuit can be adjusted to adapt to the characteristics of the target circuit. This makes it possible to supply an appropriate voltage to any target circuit.

According to the delay amount determination circuit of the present invention, it is possible to determine with a simple configuration whether or not the actual delay amount is larger than a desired delay amount. Such a delay amount determination circuit is suitable for use in a frequency-voltage conversion circuit.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akira Matsuzawa 15-5 Hachiman Sumidaguchi, Yawata City, Kyoto (72) Inventor Shiro Michimasa 3-3-5-2202 Hachizuka, Ikeda-shi, Osaka (72) Inventor Yamamoto Shinichi 1-8-49 Soya, Hirakata-shi, Osaka (56) References JP-A-58-171842 (JP, A) JP-A-58-195218 (JP, A) JP-A-3-241403 (JP, A) JP-A-7-6156 (JP, A) JP-A-60-19222 (JP, A) JP-A-8-5705 (JP, A) JP-A-9-288527 (JP, A) JP-A-9-270690 (JP JP, A) JP-A-5-158587 (JP, A) JP-A-60-10318 (JP, A) JP-A-54-148430 (JP, A) JP-A-10-209826 (JP, A) (58) ) investigated the field (Int.Cl. ^7, DB name) G06F 1/04 G06F 1/08 G06F 1/32 G06F 15/78 H03K 5/13 (54) [Title of the invention] System equipped with wave number-voltage conversion circuit, delay amount judgment circuit, frequency-voltage conversion circuit, method of adjusting input-output characteristics of frequency-voltage conversion circuit, and automatic adjustment of input-output characteristics of frequency-voltage conversion circuit apparatus

Claims (29)

(57) [Claims] An input pulse signal generating circuit for generating an input pulse signal having a pulse width representing a target delay amount according to a clock frequency; and a delay circuit for delaying the input pulse signal, wherein the input pulse signal is A delay circuit that outputs a pulse signal obtained by delaying the output pulse signal as an output pulse signal, and outputs a voltage corresponding to the target delay amount based on a delay amount of the output pulse signal with respect to the input pulse signal; And a delay-voltage conversion circuit that supplies the input pulse signal to the delay circuit according to the voltage output from the delay-voltage conversion circuit. . 2. The frequency-voltage conversion circuit according to claim 1, wherein the input pulse signal generation circuit generates the input pulse signal intermittently. 3. The frequency-voltage conversion circuit according to claim 2, wherein a cycle at which the input pulse signal is generated intermittently is variable. 4. The frequency-voltage conversion circuit according to claim 1, wherein said input pulse signal generation circuit stops generating said input pulse signal in a specific mode. 5. The frequency-voltage conversion circuit according to claim 1, wherein said delay circuit is configured such that a delay time-power supply voltage characteristic of said delay circuit is adjustable. 6. The frequency circuit according to claim 1, wherein said delay circuit is configured such that a delay time of said delay circuit and a slope of a power supply voltage characteristic and an offset amount can be adjusted.
Voltage conversion circuit. 7. The delay circuit includes a first delay block that operates according to the voltage output from the delay amount-voltage conversion circuit, and the first delay block includes a plurality of first delay units. The frequency-voltage according to claim 1, wherein the number of stages of the first delay unit through which the input pulse signal passes among the plurality of first delay units is adjusted according to a first delay control signal. Conversion circuit. 8. The delay circuit further includes a second delay block that operates according to a predetermined fixed voltage, wherein the second delay block includes a plurality of second delay units, and 8. The frequency of claim 7, wherein the number of stages of the second delay unit through which the input pulse signal passes among the second delay units is adjusted according to a second delay control signal. 9.
Voltage conversion circuit. 9. The frequency-to-voltage conversion circuit according to claim 1, wherein a pulse width of the input pulse signal is determined as a function of a frequency of the clock. 10. The function is represented by Pw = α / f + β, where Pw is the pulse width of the input pulse signal, f is the frequency of the clock, and α and β are constants.
3. The frequency-voltage conversion circuit according to claim 1. 11. The delay amount-voltage conversion circuit increases an output voltage when a delay amount of the output pulse signal with respect to the input pulse signal is larger than the target delay amount, and increases the output pulse with respect to the input pulse signal. When the delay amount of the signal is smaller than the target delay amount, the output voltage is feedback-controlled so as to lower the output voltage.
The frequency-voltage conversion circuit according to claim 1. 12. The delay amount-to-voltage conversion circuit determines whether a delay amount of the output pulse signal with respect to the input pulse signal is greater than the target delay amount, and outputs a determination signal indicating a determination result. The frequency-voltage conversion circuit according to claim 1, further comprising: a circuit; and a voltage selection circuit that selectively outputs one of a plurality of voltages according to the determination signal. 13. A bidirectional shift control circuit that shifts data specifying one voltage to be selected from among the plurality of voltages in a direction corresponding to the determination signal, based on the data. 13. The frequency-voltage conversion circuit according to claim 12, further comprising: a switch circuit that selects one of the plurality of voltages. 14. The frequency-voltage conversion circuit according to claim 12, wherein said voltage selection circuit outputs a highest voltage among said plurality of voltages as an initial output voltage. 15. The voltage selection circuit includes a resistor, one end of the resistor is connected to a high potential, the other end of the resistor is connected to a low potential, and the plurality of voltages divide the resistor. 13. The frequency-voltage conversion circuit according to claim 12, which is obtained by: 16. The frequency-voltage conversion circuit according to claim 15, wherein said voltage selection circuit further comprises a switch connected in series to said resistor, wherein said switch is turned off in a specific mode. 17. The bidirectional shift control circuit includes a plurality of stages of units. Each of the plurality of stages of units includes a memory circuit for storing the data and a two-input one-input unit.
An output selector, wherein an output of the selector included in the unit of the specific stage among the units of the plurality of stages is connected to the memory circuit included in the unit of the specific stage; The input of the selector included in the unit of the specific stage among the units of the specific stage is the memory circuit included in the unit of the stage immediately before the unit of the specific stage and one of the units of the specific stage. 14. The frequency-voltage according to claim 13, wherein the selector is connected to the memory circuit included in a unit in a subsequent stage, and the selector included in each of the units in the plurality of stages is controlled by the determination signal. Conversion circuit. 18. The bi-directional shift control means, comprising: means for preventing the data stored in the memory circuit included in the first one of the plurality of units from being erased; 18. The frequency-voltage conversion circuit according to claim 17, further comprising: means for preventing the data stored in the memory circuit included in the last one of the units of the stage from being erased. 19. The delay-to-voltage conversion circuit further comprises means for storing an output voltage one before the current output voltage, and wherein the delay-to-voltage conversion circuit converts the current output voltage to Outputting as a first output voltage, outputting one of the current output voltage and the immediately preceding output voltage as a second output voltage, wherein the first output voltage is supplied to the delay circuit. The frequency-voltage conversion circuit according to claim 1, wherein 20. The delay amount-voltage conversion circuit further includes means for storing an initial output voltage, wherein the delay amount-voltage conversion circuit outputs a current output voltage as a first output voltage, Outputting the initial output voltage as a second output voltage, wherein the first output voltage is supplied to the delay circuit; and the initial output voltage is the current output voltage when the current output voltage increases. The frequency-voltage conversion circuit according to claim 1, wherein the frequency-voltage conversion circuit is updated to: 21. An input pulse signal generating circuit for generating an input pulse signal having a pulse width representing a target delay amount, and a delay circuit for delaying the input pulse signal, the delay circuit being obtained by delaying the input pulse signal. A delay circuit that outputs a pulse signal to be output as an output pulse signal; and a determination that determines whether a delay amount of the output pulse signal with respect to the input pulse signal is greater than the target delay amount and outputs a determination signal indicating a determination result. And a delay amount determination circuit comprising: 22. The delay amount determination circuit according to claim 21, wherein a pulse width of the input pulse signal is variably adjustable. 23. The determination circuit includes a data latch circuit that receives the input pulse signal as a clock input and receives the output pulse signal as a data input, and an output of the data latch circuit is output as the determination signal. Claims
22. The delay amount determining circuit according to 21. 24. A target circuit operating according to a clock,
A frequency-voltage conversion circuit that receives the clock as an input and provides a voltage corresponding to the frequency of the clock as an operation voltage of the target circuit, wherein the frequency-voltage conversion circuit outputs the The voltage is
The input / output characteristics of the frequency-to-voltage conversion circuit can be adjusted so that the target circuit substantially matches the minimum voltage operable at the frequency of the clock. The target circuit includes a plurality of different delay times-power supply voltages. And the input / output characteristics of the frequency-voltage conversion circuit are adjusted based on a delay time-power supply voltage characteristic obtained by combining the plurality of different delay time-power supply voltage characteristics. Features system. 25. The frequency-voltage conversion circuit includes a plurality of delay circuits corresponding to the plurality of different delay time-power supply voltage characteristics, and each of the plurality of delay circuits includes:
25. The system according to claim 24, wherein the delay time-supply voltage characteristic is configured to be adjustable. 26. A target circuit that operates according to a clock;
A frequency-voltage conversion circuit that receives the clock as an input and provides a voltage corresponding to the frequency of the clock as an operation voltage of the target circuit, and adjusts input / output characteristics of the frequency-voltage conversion circuit. The method comprising: measuring the frequency of the clock based on an operating voltage of the target circuit measured for each of a plurality of frequencies of the clock.
Adjusting the slope of the input / output characteristics of the voltage conversion circuit; and Adjusting the frequency-to-voltage conversion circuit, the input-pulse signal generation circuit for generating an input pulse signal having a pulse width representing a target delay amount according to a clock frequency, and delaying the input pulse signal. A delay circuit that outputs a pulse signal obtained by delaying the input pulse signal as an output pulse signal, and the target delay based on a delay amount of the output pulse signal with respect to the input pulse signal. A delay amount-voltage conversion circuit that outputs a voltage corresponding to the amount and supplies the voltage to the delay circuit. The delay circuit delays the input pulse signal according to the voltage output from the delay-voltage conversion circuit, and the slope of the input / output characteristic of the frequency-voltage conversion circuit is the delay time of the delay circuit. The offset amount of the input / output characteristics of the frequency-voltage conversion circuit is adjusted by adjusting a slope of the power supply voltage characteristic, and the offset amount of the input / output characteristics of the delay circuit is adjusted by adjusting the offset amount of the delay time-power supply voltage characteristic of the delay circuit. Method. 27. The delay circuit includes a first delay block that operates according to the voltage output from the delay amount-voltage conversion circuit and a second delay block that operates according to a predetermined fixed voltage. The first delay block includes a plurality of first delay units, the second delay block includes a plurality of second delay units, and a slope of a delay time-power supply voltage characteristic of the delay circuit. Is adjusted by adjusting the number of stages of the first delay unit, through which the input pulse signal passes, of the plurality of first delay units, and the offset amount of the delay time-power supply voltage characteristic of the delay circuit is 27. The method according to claim 26, wherein the method is adjusted by adjusting the number of stages of the second delay unit through which the input pulse signal passes. 28. A target circuit operating according to a clock,
A frequency-voltage conversion circuit that receives the clock as an input and provides a voltage corresponding to the frequency of the clock as an operation voltage of the target circuit, and adjusts input / output characteristics of the frequency-voltage conversion circuit. The method comprising: measuring the frequency of the clock based on an operating voltage of the target circuit measured for each of a plurality of frequencies of the clock.
Adjusting the slope of the input / output characteristics of the voltage conversion circuit, and adjusting the offset amount of the input / output characteristics of the frequency-voltage conversion circuit so that the target circuit can operate in a predetermined frequency range of the clock. Adjusting the frequency-to-voltage conversion circuit, the input-pulse signal generation circuit for generating an input pulse signal having a pulse width representing a target delay amount according to a clock frequency, and delaying the input pulse signal. A delay circuit that outputs a pulse signal obtained by delaying the input pulse signal as an output pulse signal, and the target delay based on a delay amount of the output pulse signal with respect to the input pulse signal. A delay amount-voltage conversion circuit that outputs a voltage corresponding to the amount and supplies the voltage to the delay circuit. The delay circuit delays the input pulse signal in accordance with the voltage output from the delay-voltage conversion circuit, and the slope and offset of the input / output characteristics of the frequency-voltage conversion circuit are the frequency of the clock. Adjusted by adjusting the pulse width of the input pulse signal as a function of 29. The function is represented by Pw = α / f + β, where Pw is the pulse width of the input pulse signal, f is the frequency of the clock, α and β are constants, and the frequency-voltage The slope of the input / output characteristics of the conversion circuit is adjusted by adjusting the value of the constant α, and the offset amount of the input / output characteristics of the frequency-voltage conversion circuit is adjusted by adjusting the value of the constant β. 29. The method of claim 28, wherein