JPH09270690A - Drive voltage control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize low power consumption with respect to a circuit in the operating state by revising a drive voltage applied to an operating circuit in response to a frequency of a system clock. SOLUTION: An internal cell area 101 (equivalent to a work area) and an F/V voltage drop circuit 102 (equivalent to drive voltage control circuit) are provided in an integrated circuit 100. Then the F/V voltage drop circuit 102 receives a system clock CLK and a constant voltage power supply V0 from the outside of the integrated circuit 100. Furthermore, the internal cell area 101 is made up of a CMOS transistor(TR) or the like and receives the system clock CLK and an output voltage V1 of the F/V voltage drop circuit 102. The internal cell area 101 uses the output voltage V1 of the F/V voltage drop circuit 102 and is operated by an operating frequency provided by the system clock CLK.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for reducing power consumption of a semiconductor integrated circuit or the like.

[0002]

2. Description of the Related Art Conventionally, a power management mechanism has been known as a technique for reducing the power consumption of semiconductor integrated circuits and the like. What is this power management mechanism?
During the operation of the electronic circuit, the power supply to the inoperative semiconductor element is cut in units such as circuit blocks.

This power management mechanism is generally systematically incorporated into an electronic circuit by the user of the semiconductor device.

[0004]

However, in this power management mechanism, since the circuit block or the like for which the power supply is cut must be selected according to the operating state of the electronic circuit, the control becomes very complicated. It had the drawback of becoming This drawback causes an increase in design cost and the like.

Further, this power management mechanism can reduce the power consumption of the circuit blocks in the non-operating state, but cannot reduce the power consumption of the circuit blocks in the operating state. There was a limit to the reduction of power consumption.

The present invention has been made in view of the above-mentioned drawbacks of the prior art, and provides a drive voltage control circuit capable of realizing low power consumption for a circuit in an operating state with a simple structure. With the goal.

[0007]

A drive voltage control circuit according to the present invention is a drive voltage control circuit for controlling a drive voltage supplied to an operation circuit which operates on the basis of a predetermined system clock. The driving voltage supplied to the operating circuit is changed according to the frequency of.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram schematically showing the overall configuration of an integrated circuit using the drive voltage control circuit according to this embodiment.

In FIG. 1, an internal cell region 101 (corresponding to the "operating circuit" of the present invention) is provided in the integrated circuit 100.
And an F / V step-down circuit 102 (corresponding to the “driving voltage control circuit” of the present invention). And this F
In the / V step-down circuit 102, from the outside of the integrated circuit 100,
The system clock CLK and the constant power supply voltage V ₀ are input. The internal cell region 101 is composed of a CMOS transistor or the like, receives the system clock CLK, and outputs the output voltage V _{1 of the} F / V step-down circuit 102.
Is entered. The internal cell region 101 operates at the operating frequency given by the system clock CLK, using the output voltage V ₁ of the F / V step-down circuit 102 as a drive voltage.

FIG. 2 is a block diagram schematically showing the internal structure of the F / V circuit 102 shown in FIG.

As shown in the figure, the F / V circuit 10
2 is a clock counter 201 and a D / A converter 20
2 is provided. Here, the clock counter 201
Takes in the system clock CLK, counts the number of clocks per predetermined time, and outputs the count information D _CLK as the counting result.

Further, D / A converter 202 inputs an this count information D _CLK and constant power supply voltage V _0, transforms the constant power supply voltage V ₀ depending on the value of the count information D _CLK,
Output as the output voltage V ₁ . Here, the count information D
The relationship between _CLK and the output voltage V ₁ is determined so that the internal cell region 101 satisfies the inequality (1) described later.

Next, the operation of the circuit shown in FIGS. 1 and 2 will be described.

Here, for convenience of explanation, the constant power supply voltage V _{0 is used.}
Is set to 5V. Further, the D / A converter 202 outputs the output voltage V ₁ when the system clock CLK is 20 MHz.
Is 5 V, and the output voltage V ₁ when the system clock CLK is 10 MHz is 4 V.

First, it is assumed that the system clock CLK of 20 MHz and the constant power supply voltage V ₀ = 5V are input to the integrated circuit 100. The clock counter 201 in the F / V step-down circuit 102 always takes in the system clock CLK and counts the number of clocks per predetermined time.
When the data D _CLK indicating the counting result is input to the D / A converter 202, the D / A converter 2
02 sets the output voltage V ₁ to 5 V (that is, outputs it as it is without stepping down).

As a result, the internal cell region 101 has the system clock CLK (20 MHz) and the drive voltage V ₁ (5
V) and are input to perform the circuit operation.

Next, the system clock CLK is 20 MHz.
It is assumed that the frequency is switched from z to 10 MHz. As a result, the counting result of the clock counter 201 also changes.
The output voltage V ₁ of the D / A converter 202 is also stepped down from 5V to 4V based on the count information D _CLK indicating the counting result.

As a result, the internal cell region 101 has the system clock CLK (10 MHz) and the drive voltage V ₁ (4
V) and are input to perform the circuit operation. In this case, for the reason described below, the power consumption of the integrated circuit 100 can be reduced by the amount corresponding to the step-down of the drive voltage V ₁ . In addition, as described above, the count information D _{CL K}
The relationship between the output voltage V ₁ and the output voltage V ₁ is determined so that the internal cell region 101 satisfies the inequality (1) described later.
Even in this case, the stable operation of the internal cell region 101 can be maintained.

Next, the reason why the F / V step-down circuit 102 shown in FIGS. 1 and 2 can achieve low power consumption while ensuring stable operation will be described with reference to FIG.

Here, as a part of the internal cell region 101, as shown in FIG. 3A, two CMOS circuit blocks (first CMOS circuit block 301 and second CMOS circuit block 301) are provided.
CMOS circuit block 302) of FIG. Then, as conceptually shown in FIG.
The first CMOS circuit block 301 inputs the signal D _in at the rising timing of an arbitrary clock pulse P _{1 in} the system clock CLK (pulse interval is T),
Further, it is assumed that the signal D _out is output after the time t ₁ from the rising timing. And the second CMOS
The circuit block 302 takes in this signal D _out at the rising timing of the next clock pulse P _{2 in} the system clock CLK.

Here, the frequency of the system clock CLK (that is, the operating frequency of the internal cell area 101) is 20M.
If the frequency is Hz, the pulse interval of the system clock CLK is T = 50 nsec. Therefore, in order for the internal cell area 101 to operate normally, the first CM
The following inequality (1) must be satisfied, where t ₂ is the time taken for the signal D _out output from the OS circuit block 301 to reach the second CMOS circuit block 302.

T> t ₁ + t ₂ (1) That is, the CMOS circuit block 30 is set so that the inequality (1) is satisfied under a predetermined power supply voltage (for example, 5 V).
1,302 designs are made.

On the other hand, the switching time of the transistor (here, the CMOS transistor forming the internal cell region 101) depends on the power supply voltage (voltage V _{1 in the} internal cell region 101). That is, the higher the power supply voltage, the faster the switching operation of the transistor. On the other hand, when the power supply voltage is lowered, the switching operation becomes slower, but if the voltage is equal to or higher than a predetermined voltage (depending on the size of the transistor, etc.), the operation stability is secured. Therefore, the time t ₁ required for the first CMOS circuit block 301 to output the signal D _out after inputting the signal D _in
Varies depending on the value of the power supply voltage.

The delay time of the signal transmitted in the wiring pattern also changes according to the voltage value of this signal. The voltage value of this signal is usually determined by the value of the power supply voltage. Therefore, the time t ₂ until the signal D _out output from the first CMOS circuit block 301 reaches the second CMOS circuit block 302 also changes depending on the value of the power supply voltage.

Therefore, the CMOS circuit blocks 301 and 302 for satisfying the inequality (1) are designed after determining not only the operating frequency but also the value of the power supply voltage.

The frequency of the system clock CLK supplied to the integrated circuit 100 shown in FIG. 1 is 20 MH.
It is assumed that the frequency is switched from z to 10 MHz. At this time,
The pulse interval T of this system clock CLK is 50n.
It changes from sec to 100 nsec (see FIG. 3B). In such a case, the first CMOS circuit block 3
01 takes time t ₁ from the input of the signal D _in to the output of the signal D _out , and the first CMOS circuit block 30
Even if the time t ₂ required for the signal D _out output from 1 to reach the second CMOS circuit block 302 is long within the range that satisfies the above inequality (1), no problem occurs and stable operation is maintained. Can be made. Therefore,
The power supply voltage can be reduced within the range where the inequality (1) is satisfied.

The power consumption P of the CMOS transistor circuit (here, the internal cell region 101) is given by the following equation (2), where f is the operating frequency, C is the load capacitance, and V is the power supply voltage.

P = fCV ² (2) As can be seen from the equation (2), lowering the power supply voltage
It is very effective in reducing the power consumption P of the internal cell region 101.

As described above, according to the F / V step-down circuit 102 of the present embodiment, the drive voltage can be changed according to the operating frequency, so that stable operation can be ensured and low power consumption can be achieved. it can.

In this embodiment, the F / V step-down circuit 1
02 is composed of the clock counter 201 and the D / A converter 202, but the present invention is not limited to such a structure. That is, the effect of the present invention can be obtained as long as the output voltage can be changed according to the frequency of the system clock CLK.

Further, in this embodiment, the internal cell region 10 is
Although the case where 1 is configured by the CMOS transistor has been described as an example, it goes without saying that another type of circuit may be used as long as the circuit is configured to operate using the system clock CLK.

Further, although the relationship between the frequency of the system clock CLK and the driving voltage V ₁ is determined so that the internal cell region 101 satisfies the inequality (1), such a condition is not essential. For example, the timing at which the second CMOS transistor 302 takes in the signal D _out is
If the clock pulse P ₃ rises (see FIG. 3B), the relationship between the frequency of the system clock CLK and the drive voltage V ₁ is determined so that the internal cell region 101 satisfies the following expression (3). That is, the relationship between the frequency of the system clock CLK and the drive voltage V ₁ is of a nature that should be appropriately determined according to the delay condition of the operating circuit (in this embodiment, the internal cell region 101).

2T> t ₁ + t ₂ (1) Also, the operating speed of the transistor and the delay time of the signal propagating through the wiring pattern vary depending on the size of the transistor, the electrical resistance of the wiring pattern, and the like. Therefore, the delay condition of the operating circuit may be determined by simulation or the like while considering factors such as the size of the transistor and the electric resistance of the wiring pattern.

In addition, in this embodiment, the integrated circuit 100
Although the case where the frequency of the system clock CLK is switched during the operation has been described as an example, the effect of the present invention can be obtained even when applied to a circuit having no function of switching the frequency of the system clock CLK.
For example, the effect of the present invention can be obtained even when the user fixes the semiconductor device equipped with the present invention with the system clock CLK having a frequency lower than the normal frequency (20 MHz in this embodiment). Obtainable. That is, in this case, the user can achieve low power consumption by using the semiconductor element with a normal power supply voltage (5 V in the case of the present embodiment).

[0036]

As described in detail above, according to the present invention, it is possible to provide a drive voltage control circuit which can realize low power consumption for a circuit in an operating state with a simple structure.

[Brief description of drawings]

FIG. 1 is a block diagram schematically showing an overall configuration of an integrated circuit using a drive voltage control circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram schematically showing an internal configuration of the F / V circuit shown in FIG.

FIG. 3 is a diagram for explaining the reason why low power consumption can be achieved with the F / V step-down circuit shown in FIGS. 1 and 2, and FIG. 3A is a conceptual diagram showing an example of an internal configuration of an internal cell region. FIG. 3B is a block diagram schematically showing the operation, and FIG. 6B is a timing chart showing the operation of the circuit shown in FIG.

[Explanation of symbols]

 101 Internal Cell Area 102 F / V Step-Down Circuit 201 Clock Counter 202 D / A Converter 301, 302 CMOS Circuit Block

Claims (5)

[Claims] 1. A drive voltage control circuit for controlling a drive voltage supplied to an operation circuit that operates based on a predetermined system clock, wherein the drive voltage is supplied to the operation circuit according to the frequency of the system clock. A drive voltage control circuit, characterized in that: 2. An operating frequency detecting means for detecting an operating frequency of the operating circuit, and a voltage control means for changing a drive voltage supplied to the operating circuit according to the operating frequency detected by the operating frequency detecting circuit. The drive voltage control circuit according to claim 1, further comprising: 3. The operating frequency detecting means is a clock counter which takes in the system clock and counts the number of clocks per predetermined time.
The drive voltage control circuit according to. 4. The voltage control means is a D / A converter that changes the drive voltage according to the detection result input from the operating frequency detection means.
The drive voltage control circuit according to. 5. The drive voltage control according to claim 1, wherein the relationship between the frequency of the system clock and the drive voltage is determined according to the delay condition of the operating circuit. circuit.