JP3323153B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a PLL circuit in which feedback of a PLL output is kept normal.

[0002]

2. Description of the Related Art Conventional general skew adjustment PLL
The circuit is shown in FIG.

The PLL circuit shown in FIG. 4 includes a delay circuit 1, a phase comparator 2, a charge pump circuit 3, a filter circuit 4, a voltage controlled oscillator 5, a buffer 6, and a frequency divider 7. The voltage controlled oscillator 5 includes a voltage-current conversion circuit 5a and a current controlled oscillator 5b.

The delay circuit 1, the phase comparator 2, the charge pump circuit 3, the filter circuit 4, the voltage controlled oscillator 5, the buffer 6, and the frequency divider 7 constitute a PLL core. The PLL circuit includes a reference signal input terminal 9, a feedback signal input terminal 10, an output terminal 11, and a reset terminal 1.
5 is provided. Reference numeral 8 denotes an external logic circuit unrelated to the PLL circuit inserted into the feedback path.

In such a configuration, an output frequency which is a PLL output from the output terminal 11 is taken into the frequency divider 7 for setting the multiplication rate from the feedback signal input terminal 10 through the logic circuit 8. Then, the frequency divider 7 divides the frequency by 1 / N so as to have the same frequency as the reference signal.

Before the frequency divider 7, feedback is applied so that the phase of the feedback signal matches the phase of the reference signal. The reference signal input from the reference signal input terminal 9 is input to the phase comparator 2 via the delay circuit 1 for compensating for the delay caused by the frequency divider 7 of the feedback signal.

At this time, when the reset is performed by the internal operation of the logic circuit 8 and the output of the logic circuit 8 is interrupted, the PL is reset.
Only the reference signal continues to be input to the L circuit. For this reason,
The PLL circuit is controlled to increase the frequency. In this case, since the conventional PLL circuit does not include a means for controlling the upper limit of the oscillation frequency, the PLL output exceeds the normal operation frequency range of the logic circuit 8.

As described above, when the PLL output exceeds the frequency range of the normal operation of the logic circuit 8, normal feedback is not applied. Therefore, the PLL circuit cannot be locked until a reset signal is input from the reset terminal 15. Becomes

To solve such a problem, FIG.
There is a PLL circuit as shown in FIG.

In the PLL circuit shown in FIG.
Has been added. The control voltage 12 is set by the added reference voltage 17 of the comparator 16 so as to be within the frequency range of the normal operation of the logic circuit 8.

That is, when the control voltage 12 exceeds the reference voltage 17, the feedback by the comparator 16 suppresses the control voltage 12 from rising above the reference voltage 17. This prevents a malfunction of the PLL circuit.

[0012]

However, in the conventional PLL circuit shown in FIG. 5, since the rise of the control voltage 12 is suppressed by the reference voltage 17 of the comparator 16, the operating range of the control voltage 12 is controlled. Is narrowed. As described above, when the operation range of the control voltage 12 is narrowed, there is a disadvantage that the frequency range of the PLL output cannot be widened. There is also a disadvantage that it is difficult to set the control of the frequency range of the PLL output due to a variation in the manufacturing process of the comparator 16 and the like.

By the way, as a device for stabilizing the operation of the PLL circuit, for example, Japanese Patent Application Laid-Open No. 4-42617.
There is a PLL circuit disclosed in Japanese Unexamined Patent Publication (Kokai) No. H11-26095. This is because when the state changes from a state without the input signal of the PLL circuit to a state with the input signal,
By suppressing the disturbance of the oscillation frequency of the output signal, the time until the phase is locked is shortened.

However, in this prior art, no means is taken when the feedback signal of the PLL circuit is interrupted due to the interruption of a logic circuit unrelated to the PLL circuit inserted during the feedback.

SUMMARY OF THE INVENTION The present invention has been made in view of such a situation, and it is possible to widen a frequency range of a PLL output, and to easily set a control of a frequency range including process variations. And a PLL circuit capable of keeping the feedback of the PLL output normal.

[0016]

A PLL according to claim 1, wherein:
The circuit is inserted in the feedback path of the feedback signal, and P
An external logic circuit irrelevant to the LL circuit core unit and a 1 /
A frequency divider for dividing by N, a delay circuit for taking in the reference signal and compensating for a delay of a feedback signal generated by the frequency divider, and a phase comparator for comparing phases of outputs of the delay circuit and the frequency divider A control voltage generating means for generating a control voltage according to a comparison result from the phase comparator; a voltage controlled oscillator for performing a PLL output based on the control voltage; Output frequency control means for controlling the output frequency, which is the PLL output from the voltage controlled oscillator, not to exceed a frequency at which the logic circuit becomes operable when only the reference signal is input after interruption. It is characterized by the following. The output frequency control means may include a speed detection circuit that outputs a predetermined signal before an output frequency of the voltage controlled oscillator exceeds a limit of a normal operation frequency of the logic circuit, and a predetermined signal from the speed detection circuit. When receiving the signal, the counter may count a predetermined number of waves and then output a counter for suppressing the control voltage. The speed detection circuit includes a first N-channel MOS transistor and a first P-channel MOS transistor.
A first inverter circuit for taking in the output frequency from the voltage controlled oscillator, a second Nch-type MOS transistor and a second Pch-type MOS transistor,
A second inverter circuit for outputting the predetermined signal, wherein a gate length of the first Nch-type MOS transistor and the first Pch-type MOS transistor is such that a voltage at which a logic of the first inverter circuit is inverted. The power supply voltage is set to be higher than half of the power supply voltage, and the second Nch
The gate lengths of the type MOS transistor and the second Pch type MOS transistor may be set so that the voltage at which the logic of the second inverter circuit is inverted is lower than half the power supply voltage. P according to the present invention
In the LL circuit , a 1 / N frequency divider is inserted into the feedback path of the feedback signal, and the frequency of the feedback signal from an external logic circuit unrelated to the PLL operation is divided by 1 / N so that the frequency becomes the same as that of the reference signal. While taking a reference signal, compensating for the delay of the feedback signal generated by the frequency divider with a delay circuit, comparing the phases of the outputs of the delay circuit and the frequency divider with a phase comparator, When the control voltage generating means generates a control voltage according to the comparison result and the voltage-controlled oscillator performs PLL output based on the control voltage, the output signal of the logic circuit cuts off the feedback signal, and only the reference signal is interrupted. When input, the output frequency control means controls the output frequency, which is the PLL output from the voltage controlled oscillator, so as not to exceed the frequency at which the logic circuit can operate. To so that.

[0017]

Embodiments of the present invention will be described below. Note that, in the drawings described below, parts common to FIGS. 4 and 5 are denoted by the same reference numerals.

FIG. 1 is a block diagram showing an embodiment of the PLL circuit of the present invention, FIG. 2 is a circuit diagram showing details of the speed detection circuit of FIG. 1, and FIG. 3 is an operation of the PLL circuit of FIG. FIG.

The PLL circuit shown in FIG. 1 includes a delay circuit 1, a phase comparator 2, a charge pump circuit 3, a filter circuit 4, a voltage controlled oscillator 5, a buffer 6, a frequency divider 7, a speed detection circuit 13, and a counter 14. Have. The voltage controlled oscillator 5 includes a voltage-current conversion circuit 5a and a current controlled oscillator 5b. The delay circuit 1, the phase comparator 2, the charge pump circuit 3, the filter circuit 4, the voltage controlled oscillator 5, the buffer 6, the frequency divider 7, the speed detection circuit 13, and the counter 14 constitute a PLL core unit.

The PLL circuit has a reference signal input terminal 9, a feedback signal input terminal 10, and an output terminal 11. Reference numeral 8 denotes an external logic circuit unrelated to the PLL circuit inserted into the feedback path.

Here, the delay circuit 1 takes in the reference signal from the reference signal input terminal 9 and compensates for the delay of the feedback signal caused by the frequency divider 7. The phase comparator 2 includes a delay circuit 1
And the phase of the output of the frequency divider 7 is compared. As the control voltage generating means, first, the charge pump circuit 3 includes the phase comparator 2
And generates a control current corresponding to the comparison result. Next, the filter circuit 4 generates a control voltage.

The voltage-controlled oscillator 5 performs a PLL output from the output terminal 11 and includes a voltage-current conversion circuit 5a.
Converts the control voltage to a current. In addition, the current control oscillator 5
b oscillates at a frequency corresponding to the current converted by the voltage-current conversion circuit 5a.

The frequency divider 7 controls the signal from the feedback signal input terminal 10 so that 1 / N
Divide. The speed detection circuit 13 includes the voltage-controlled oscillator 5
Before the output frequency of the logic circuit 8 exceeds the frequency limit at which the logic circuit 8 can operate normally, a predetermined signal of “Low” is output.

The counter 14 receives the reference signal from the reference signal input terminal 9 as a clock input, and
Output 3 is a reset input. The output of the counter 14 controls the control voltage 12. Here, the speed detection circuit 13 and the counter 14 constitute output frequency control means.

FIG. 2 shows the details of the speed detection circuit 13.

The speed detection circuit 13 is an Nch type MOS
It includes transistors MN1 and MN2 and Pch type MOS transistors MP1 and MP2.

Nch type MOS transistors MN1 and Pc
a first inverter circuit including an h-type MOS transistor MP1, and a second inverter circuit including an N-channel MOS transistor MN2 and a P-channel MOS transistor MP2.
Connected to the inverter circuit.

The Nch type MOS transistor MN1
The input (2-A) connected to the gates of the Pch type MOS transistor MP1 and the Pch type MOS transistor MP1 is connected to the output terminal 11 of FIG. Nch type MOS transistor MN2 and Pch
The output (2-C) connected to the drain of the type MOS transistor MP2 is connected to the reset input of the counter 14 in FIG.

Nch type MOS transistors MN2 and Pc
Gate (2-B) with h-type MOS transistor MP2
, Nch type MOS transistor MN1 and Pch type MO
The drain (2-B) of the S transistor MP1 is connected.

The Nch type MOS transistor MN1
And the gate length of the Pch type MOS transistor MP1 is
The voltage at which the logic of the first inverter circuit is inverted is set to be higher than half of the power supply voltage. Nch type M
The gate lengths of the OS transistor MN2 and the second Pch-type MOS transistor MP2 are set such that the voltage at which the logic of the second inverter circuit is inverted is lower than half the power supply voltage.

The speed detection circuit 13 receives the input (2-A)
When a signal having a frequency that has become higher than the limit of the frequency at which the logic circuit 8 can operate normally is input to the gates of the Nch-type MOS transistor MN1 and the Pch-type MOS transistor MP1 constituting the first inverter circuit of the preceding stage, From the setting of the length, the drive capability of the Nch-type MOS transistor MN1 becomes smaller than the drive capability of the Pch-type MOS transistor MP1. Therefore, the potential of (2-B) cannot be completely lowered to “Low” and becomes “Hi” output.

From the setting of the gate lengths of the Nch type MOS transistor MN2 and the Pch type MOS transistor MP2 constituting the second inverter circuit of the next stage, Pc
The drive capability of the h-type MOS transistor MP2 is Nch
It becomes smaller than the drive capability of the type MOS transistor MN2. For this reason, the potential of the output (2-C) cannot be raised to "Hi", and the output becomes "Low". Note that in a configuration having two stages of inverters, the potential of the output (2-C) becomes “L”.
When the number of inverters cannot be reduced to "ow", the number of inverter stages may be increased by an even number, such as four or six stages.

Next, the operation of the PLL circuit having such a configuration will be described.

First, the output frequency output from the output terminal 11 of FIG.
From 0, it is input to the frequency divider 7 for setting the multiplication rate. The input output frequency is frequency-divided by the frequency divider 7 so as to have the same frequency as the reference signal by 1 / N. Before the frequency divider 7, feedback is applied so that the phase of the feedback signal matches the phase of the reference signal.

The reference signal input from the reference signal input terminal 9 is input to the phase comparator 2 via the delay circuit 1 for compensating for the delay caused by the feedback signal generated by the frequency divider 7. Then, when the reset is performed by the internal operation of the logic circuit 8 and the output of the logic circuit 8 is interrupted, only the reference signal is continuously input to the PLL circuit.

Therefore, the PLL circuit is controlled to increase the frequency. In this case, “Low” is output from the speed detection circuit 13 before the output frequency of the voltage controlled oscillator 5 exceeds the frequency limit at which the logic circuit 8 can operate normally.

At this time, when the counter 14 receives “Low” from the speed detection circuit 13, the counter 14 is not reset. At this time, the counter 14
Is obtained by counting the reference signal of the PLL circuit at a constant wave number.
"Hi" is output. As a result, the control voltage 12 is reduced, so that the PLL circuit is maintained at the lowest frequency. As a result, the output frequency from the voltage controlled oscillator 5 becomes
Exceeding the frequency at which the logic circuit 8 can operate normally is suppressed.

Here, the operation of the speed detection circuit 13 and the counter 14 will be described with reference to FIG. FIG. 3 (a)
3 is a reference signal, and FIGS. 3B to 3D are speed detection circuits 1.
3 is a pulse at each point, and FIG.
Respectively are shown. FIG. 3B shows a pulse input to the input (2-A) in FIG.
FIG. 3C shows the pulse (2-B) in FIG. FIG. 3D shows a pulse output from the output (2-C) in FIG.

FIG. 3F shows the signal pattern on the left side.
FIG. 3G shows the right side of the signal pattern, respectively.
The left side of the signal pattern (f) indicates that the output frequency of the voltage controlled oscillator 5, which is the output of the PLL circuit, is within the frequency range in which the logic circuit 8 can operate normally. on the other hand,
The right side of the signal pattern (g) shows a case where the output frequency of the voltage controlled oscillator 5 has increased to just before the limit of the frequency at which the logic circuit 8 can operate normally.

Then, as shown in the right side of the signal pattern (g), when the reset is caused by the internal operation of the logic circuit 8 and the output of the logic circuit 8 is interrupted, only the reference signal shown in FIG. . At this time, the PLL circuit is controlled to increase the frequency, and the input (2-A) of the speed detection circuit 13 is outputted from the voltage controlled oscillator 5 as shown in FIG. A signal having a higher frequency than that in the state of (1) is input. Before the output frequency of the voltage controlled oscillator 5 exceeds the limit of the frequency at which the logic circuit 8 can operate normally, as shown in FIG. 3D, the output (2-C) of the speed detection circuit 13 “Low” is output.

At this time, when the counter 14 receives "Low" from the speed detection circuit 13, the counter 14 is not reset, and outputs "Hi" when the reference signal of the PLL circuit is counted at a constant wave number.

As a result, the control voltage 12 is reduced, so that the PLL circuit is maintained at the lowest frequency. As a result, the output frequency from the voltage controlled oscillator 5 is suppressed from exceeding the frequency at which the logic circuit 8 can operate normally.

As described above, in this embodiment, the frequency divider 7 inserts the feedback signal into the feedback path of the feedback signal and outputs the reference signal from the external logic circuit 8 irrelevant to the PLL circuit core unit. 1 / so that it becomes the same frequency as the signal
While dividing the frequency by N, taking in the reference signal, the delay of the feedback signal generated by the frequency divider 7 was compensated by the delay circuit 1, and the phases of the outputs of the delay circuit 1 and the frequency divider 7 were compared by the phase comparator 2. Thereafter, when the control voltage 12 according to the comparison result from the phase comparator 2 is generated by the charge pump circuit 3 and the filter circuit 4, and the voltage controlled oscillator 5 performs the PLL output based on the control voltage 12, When the feedback signal is interrupted due to the output cutoff of the logic circuit 8 and only the reference signal is input, the operation of the speed detection circuit 13 and the counter 14 causes the P-
The output frequency, which is the LL output, is controlled so as not to exceed the frequency at which the logic circuit 8 can operate.

Therefore, the PLL circuit according to the present embodiment does not limit the operating range of the control voltage 12, so that the frequency range of the PLL output can be widened. In addition, the control of the frequency range including the variation in the process can be easily set, and the feedback of the PLL output can be kept normal.

[0045]

As described above, according to the PLL circuit of the present invention, the PLL circuit is inserted into the feedback path of the feedback signal,
The output signal from an external logic circuit unrelated to the L circuit core is frequency-divided by a frequency divider to 1 / N so as to have the same frequency as the reference signal. The delay circuit compensates for the delay of the feedback signal, compares the phases of the outputs of the delay circuit and the frequency divider with the phase comparator, and then generates the control voltage according to the comparison result from the phase comparator. Further, when the voltage-controlled oscillator performs PLL output based on the control voltage, and when the feedback signal is interrupted due to the output cutoff of the logic circuit and only the reference signal is input, the output frequency control means outputs Since the output frequency of the PLL output from the control oscillator is controlled so as not to exceed the frequency at which the logic circuit becomes operable, the frequency range of the PLL output can be widened. Can, moreover the setting of the control frequency range, including variations in the process can be easily performed, and further can maintain normal feedback of the PLL output.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a circuit diagram showing details of a speed detection circuit of FIG. 1;

FIG. 3 is a diagram for explaining an operation of the PLL circuit of FIG. 1;

FIG. 4 is a block diagram illustrating an example of a conventional PLL circuit.

FIG. 5 is a block diagram showing another example of a conventional PLL circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Delay circuit 2 Phase comparator 3 Charge pump circuit 4 Filter circuit 5 Voltage controlled oscillator 5a Voltage-current conversion circuit 5b Current controlled oscillator 6 Buffer 7 Divider 8 Logic circuit 9 Reference signal input terminal 10 Feedback signal input terminal 11 Output terminal Reference Signs List 12 Control voltage 13 Speed detection circuit 14 Counter MN1 to MN2 Nch type MOS transistor MP1 to MP2 Pch type MOS transistor

Claims (3)

(57) [Claims] 1. An external logic circuit which is inserted into a feedback path of a feedback signal and is unrelated to a PLL circuit core unit, and 1 / N frequency division of the feedback signal so as to have the same frequency as a reference signal. A delay circuit that takes in the reference signal and compensates for a delay of a feedback signal generated by the frequency divider; a phase comparator that compares phases of outputs of the delay circuit and the frequency divider; Control voltage generating means for generating a control voltage according to the comparison result from the phase comparator; a voltage controlled oscillator for outputting a PLL based on the control voltage; and an output cutoff of the logic circuit, whereby the feedback signal is interrupted. Output frequency control means for controlling the output frequency as the PLL output from the voltage controlled oscillator not to exceed a frequency at which the logic circuit becomes operable when only the reference signal is input; And a PLL comprising:
circuit. 2. The output frequency control means, comprising: a speed detection circuit that outputs a predetermined signal before an output frequency of the voltage controlled oscillator exceeds a limit of a normal operation frequency of the logic circuit; 2. The PLL circuit according to claim 1 , further comprising: a counter that counts a predetermined number of waves of the reference signal when receiving the predetermined signal, and outputs a counter for suppressing the control voltage. 3. A speed detection circuit comprising: a first Nch-type MOS transistor and a first Pch-type M transistor.
A first inverter circuit configured with an OS transistor and taking in an output frequency from the voltage controlled oscillator; a second Nch-type MOS transistor and a second Pch-type M transistor.
An OS transistor, and a second inverter circuit that outputs the predetermined signal. The first Nch-type MOS transistor and the first Pc
The gate length of the h-type MOS transistor is set such that the voltage at which the logic of the first inverter circuit is inverted is higher than half the power supply voltage, and the second Nch-type MOS transistor and the second Pc
3. The PLL circuit according to claim 2, wherein a gate length of the h-type MOS transistor is set such that a voltage at which the logic of the second inverter circuit is inverted is lower than half of a power supply voltage.