JP3321813B2 - M scramble circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an M scramble circuit used for channel coding of digital signals and the like, and more particularly to an M scramble circuit used for channel coding of a digital VTR recorded and reproduced by a partial response class IV system. Circuit.

[0002]

2. Description of the Related Art When a crumbled NRZ system is used as a modulation system for digital magnetic recording such as a digital VTR, there is a problem in waveform characteristics and overwrite characteristics because the low-frequency component of a recording signal is not restricted. Therefore, as disclosed in Japanese Patent Application Laid-Open No. 2-96982, the applicant prepared M-sequence (pseudo-random number) signals having a plurality of mutually different phases, and among the signals scrambled by these M-sequence signals. Corresponding to a low-frequency component with low
An adaptive M scrambling method for selecting a sequence signal has been proposed.

[0003] The adaptive M scrambling method will be briefly described with reference to FIG. In FIG. 6, the input data signal from the input terminal 1 is EX-OR
(Exclusive OR) circuit or mod 2 (modulo 2) adders 2a to 2d. A reset signal related to a predetermined synchronization block is supplied to an M-sequence (random number) signal generation circuit 4 via an input terminal 3. The M-sequence signal generation circuit 4 outputs four M-sequence signals having different phases and supplies them to the adders 2a to 2d. Each output signal (generation sequence) from each of the adders 2a to 2d is sent to a measurement circuit 5 for measuring a run length, a DSV (Digital Sum Value) or the like in each signal, and each buffer memory 6
a to 6d. The measuring circuit 5 determines which of the output signals has the shortest longest run length and / or has the smallest maximum DSV in the synchronous block. Output signals from the buffer memories 6a to 6d are sent to the selected terminals a to d of the changeover switch 7, respectively, and the signal of the best system is selected and taken out based on the determination result in the measuring circuit 5. An output signal from the changeover switch 7 is sent to a recording data generation circuit 8, where identification information (hereinafter, referred to as ID) and SYNC (synchronization) information representing an M-sequence signal determined by the measurement circuit 5 in the recording data generation circuit 8. And the like are added and taken out from the output terminal 9.

[0004] Such an adaptive M scrambling method is applied, for example, to channel coding for recording digital signals in a digital VTR. FIGS. 7A and 7B are block circuit diagrams showing a general configuration of a digital VTR. FIG. 7A shows the configuration on the recording side, and FIG. 7B shows the configuration on the reproduction side.

In FIG. 7A, for example, when a video signal of the NTSC system is supplied to an input terminal 11, the video signal is digitized by an A / D converter 12 and
Bit reduction is performed at 3. Further, after an ECC encoder 14 adds a parity code (error correction code) or the like for error correction, the channel coder 15 converts the data into a data string corresponding to the characteristics of the tape head system. This data string is supplied to the adder 16, and the SYNC
The synchronization code from the (synchronization) generation circuit 17 is added to the data string. The data is supplied to the recording head 19 as recording data via the recording amplifier 18 and is recorded on the tape 20.

At the time of reproduction, FIG.
A signal reproduced by the reproducing head 21 from the tape 20 is supplied to an equalizer 23 through a reproducing amplifier 22 and subjected to a predetermined equalizing process, and then supplied to a clock reproducing circuit 24 to reproduce data and a transmission clock. . The reproduced data string is converted by the channel decoder 2 which performs the reverse conversion to the above-described channel coder 15 on the recording side.
5 and the SYNC detection circuit 25a to perform error correction using the parity code. The error-corrected signal is sent to a D / A converter 28 via an ECC decoder 26 and a bit reduction decoder 27, and an analog-converted video signal is extracted from an output terminal 29.

In such a configuration of the digital VTR, the above-described adaptive M scramble circuit shown in FIG. 6 is used for the channel coder 15 and the adder 16. In addition, a configuration for descrambling the adaptive M scramble is used in the channel decoder 25 on the reproduction side.

[0008]

In the above-described M scramble circuit, identification information (ID) for identifying which M-sequence signal is selected is added. If an error occurs in step (1), the correct M-sequence cannot be selected during reproduction, and accurate recording and reproduction cannot be performed. In order to prevent this, it is conceivable to add parity to the ID.

However, the partial response
In a digital signal recording / reproducing system adopting the class IV, a precoder is required on the recording side, so that it is necessary to take care not to cause mutual interference between the precoding process and the parity addition.

[0010] Here, the partial response is a method of shaping the spectrum of a code by positively utilizing the intersymbol interference due to the transmission characteristics of a transmission path (or a recording medium). An NRZI code, an interleaved NRZI code, and the like belong to the IV. The precoder is for converting input data into an intermediate sequence in order to avoid propagation of a code error at the time of reproduction (at the time of identification). For example, as shown in FIG.
The output from the R (exclusive OR) circuit 81 is fed back to the EX-OR circuit 81 via the two-stage latch circuits 82 and 83. The transfer characteristic of this circuit is expressed by the formula [1 / (1 + D) ² ] mod 2.

Therefore, in a system using the partial response class IV, the adaptive M
To realize the scramble method, the latch circuit 8
Since the previous data is stored in 2, 83, if the ID or ID parity is inserted after the precoder, a correct precode output cannot be obtained.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide an M scramble circuit applicable to a system using a partial response class IV.

[0013]

An M scrambling circuit according to the present invention comprises: an M sequence signal generating means for generating a plurality of different M sequence signals; and a means for scrambling a digital input signal with the plurality of M sequence signals. Precoding each of these scrambled generated sequences with a partial response class IV, a plurality of precoders having latch means, and a measurement for measuring an output signal from these precoders to determine an optimal signal Means, switching selection means for switching and selecting an optimum signal among the output signals from the plurality of precoders in accordance with the output signal from the measuring means, and corresponding to the output signal from the switching selection means. The identification information of the M-sequence signal, the error correction code of the identification information, and the contents of the latch means in the precoder are synchronized. By adding the adjustment bit for presetting the data head position of click, by having a recording data generation means for generating recording data,
The above-mentioned problem is solved.

[0014]

[0015]

According to the first aspect of the present invention, since the adjustment bit is used, the data content of the latch means in the precoder can be preset at a head position of the synchronous block to be constant, thereby improving the error rate. it can. According to the second aspect, since the pre-coding is performed after the identification information and the error correction code of the identification information are added in advance, it is possible to prevent the adverse effect of inserting the identification information or the like after the pre-coding.

[0016]

FIG. 1 is a block circuit diagram showing a schematic configuration of an M scramble circuit according to a first embodiment of the present invention.
In FIG. 1, an input terminal 31 is, for example, an ECC encoder 1 of a digital VTR shown in FIG.
A data signal, such as the output from 4 is provided. This input data signal is applied to an adder (EX-
(OR circuit) 32a to 32d. A reset signal RST related to a predetermined synchronization block is supplied to the input terminal 33, and the reset signal RST is supplied to an M-sequence signal generation circuit 34. The M-sequence signal generation circuit 34 outputs four M-sequence signals having different phases, that is, a pseudo-random number data signal.
a to 32d. Each of these adders 3
In 2a to 32d, the input data signal is added to each of the different M-sequence signals (addition of mod2) and output as four-sequence scrambled signals S1 to S4.

These signals S1 to S4 are output from the precoder 3
At 5a to 35d, they are precoded in the partial response class IV and output in the form of precoded signals S5 to S8, respectively. These precoders 35a-3
5d is an exclusive OR (E) as shown in FIG.
X-OR) circuit 81 is output to the two-stage latch circuit 8
The configuration is such that feedback is provided to the EX-OR circuit 81 via 2, 83. These precoders 35
Each of the precode signals S5 to S8 from a to 35d is a buffer memory 36a having a storage capacity for one synchronous block.
To 36 d and the measurement circuit 37.

In the measuring circuit 37, each precode signal S5
Measure the run length, digital sum value (DSV) and the like in S8. Specifically, among the pre-code signals S5 to S8, the one having the shortest longest run length and / or the one having the smallest maximum DSV in the synchronous block is determined. The priority order is run length first. The measuring circuit 37 outputs the switching control signal for selecting the discriminated precode signal, and the M corresponding to the precode signal (scrambled before the precode).
The identification information (ID) of the sequence signal is output.

Output signals from the buffer memories 36a to 36d are sent to selected terminals a to d of a changeover switch 38, respectively.
Is controlled by the above-described switching control signal, the best precode signal based on the determination result in the measuring circuit 37 is selected and taken out. The output signal from the changeover switch 38 is sent to the recording data generation circuit 39.

In the recording data generation circuit 39,
Identification information (ID) indicating the M-sequence signal used for scrambling the pre-code signal with respect to the pre-code signal (output sequence) switched and selected by the changeover switch 38
And an ID parity bit ID _P for preventing this ID error. At this time, the latch circuit 8 of the precoder is placed at the head position of the synchronous block.
The recording signal REC as shown in FIG. 2 is obtained by inserting the adjustment bit ADJ for presetting the data contents of 2, 83. As a result, the data contents of the latch circuits 82 and 83 become constant at the data head position of the synchronous block. This recording signal REC is output to output terminal 4
0, and sent to, for example, the recording amplifier 18 shown in FIG.

In FIG. 2, the recording data REC
Is a 2-byte synchronization signal SY, a 1-byte ID parity bit ID _P , a 2-byte ID, 0.
It consists of 5 bytes of adjustment bits ADJ and 30 to 255 bytes of output sequence data. Since the adjustment bit ADJ is provided to preset the contents of the data latch in the precoder at the data start position of the synchronization block, the detection of the presence of the precoder in the recording system such as the partial response class IV described above is performed. Even when the scheme is used, the adaptive M scrambling scheme can be applied, and the error rate can be improved.

Next, FIG. 3 shows a configuration example on the reproducing side corresponding to the M scramble circuit shown in FIG.
For example, when applied to a digital VTR, it is used for the channel decoder 25 and the SYNC detection circuit 25a shown in FIG. In FIG. 3, "1", "0" is input to an input terminal 41 by, for example, a detection decoding circuit or the like.
The determined data string is input. In the input data sequence, the SYNC detection circuit 42 detects a break for each synchronization block and a break for each byte. Of these, the delimiter for each byte is given to the byte synchronizing circuit 43, and the input data string is decomposed for each byte, and the byte synchronizing circuit 43 sends the ID error correction circuit 44 and the EX-OR circuit (mod2 adder) 45. Sent to On the other hand, the delimiter for each synchronization block from the SYNC detection circuit 42 is supplied to the M-sequence signal generation circuit 46, and the M-sequence signal is reset for each synchronization block. The M-sequence signal generator 46 outputs four M-sequence signals (pseudo-random data signals) corresponding to the four M-sequence signals from the M-sequence signal generator 34 on the recording side, respectively. It is sent to each of the selected terminals a to d.

The ID error correction circuit 44 corrects the error of the ID and outputs the ID indicating the M sequence used at the time of recording.
Is determined. By switching the changeover switch 47 in accordance with the determined ID of the M sequence, the same M sequence as at the time of recording is selected and sent to the EX-OR circuit 45,
Mod2 is added to the input data. That is, so-called descrambling is performed, and the data before scrambling on the recording side is obtained and taken out from the output terminal 48. The ID data from the ID error correction circuit 44 is taken out via the output terminal 49.

FIG. 4 is a block circuit diagram showing a schematic configuration of a second embodiment of the present invention. The second shown in FIG.
In this embodiment, the same parts as those in the first embodiment of the present invention shown in FIG. That is, in FIG. 4, adders (EX-OR circuits) 32a to 32d of each mod 2 convert the input signal from the input terminal 31 with four M-sequence signals having different phases from the M-sequence signal generation circuit 34. The scrambled signals S1 to S4 are output.

In the second embodiment, these four
The series signals S1 to S4 are sent to the identification information adding circuits 51a to 51
1d, and identification information (ID) for identifying the M-sequence signal used for each scramble by these identification information adding circuits 51a to 51d.
And an ID parity bit I for error correction of the ID
D _P to calculate the respective target insertion. The pre ID and ID _{signal P} is added is sent respectively to the precoder 35a to 35d.

[0026] This is because, as described above (see FIG. 8) latch circuits 82 and 83 in the precoder is correct precoded when inserting the ID and ID _P later because it affected the previous data, Is no longer performed. That is, the four-sequence signals S1 to S4 from the adders 32a to 32d are already scrambled by the respective M-sequence signals and the identification information (I
D) is known, and the respective ID parity ID _P can be calculated and obtained by the error correction encoding process. Therefore, in the second embodiment, these IDs and IDs are calculated.
After calculating and inserting _P first, the above precoding process is performed.

In the precoders 35a to 35d, precoding processing is performed in a partial response class IV, and each precode output signal is transmitted through buffer memories 36a to 36d each having a storage capacity of one synchronous block, and a changeover switch 38. To the selected terminals a to d. The precode signals from the precoders 35a to 35d are sent to the measurement circuit 52.

The measuring circuit 52 measures a run length, a digital sum value (DSV), etc. in each precode signal including the ID and ID _P , and the maximum run length is one for each synchronous block. The shortest one and / or the one with the smallest maximum DSV are determined, and a switching control signal for selecting the determined precode signal is output to switch the changeover switch 38. Accordingly, the best precode signal based on the result of the determination in the measuring circuit 52 is selected by the changeover switch 38, and the recording signal REC as shown in FIG.

In the example of FIG. 5, one synchronization block of the recording data REC includes a 2-byte synchronization signal SY, a 1-byte ID parity bit ID _P , a 3-byte ID, and a 3-byte ID.
The output sequence data is composed of up to 255 bytes.

As for the reproducing-side configuration for such a recording-side configuration, the decoder configuration shown in FIG. 3 described above can be used as it is, and a description thereof will be omitted.

According to the second embodiment of the present invention as described above, the identification information ID indicating the corresponding M sequence by the identification information adding circuits 51a to 51d and the ID parity ID which is the error correction code of the ID. _{Since P} is pre-coded by the precoders 35a to 35d after being added in advance, it is possible to prevent the adverse effect of inserting the identification information or the like after the pre-coding. Therefore,
Even when a detection method having a precoder is used in a recording system such as the partial response class IV described above, the adaptive M scrambling method can be applied, and the error rate can be improved.

The present invention is not limited to the above embodiment. For example, the identification information ID includes not only the M-sequence discrimination information data but also various other auxiliary information. You may. Also, the application device of the M scramble circuit of the present invention is not limited to a digital VTR, but can be used for various digital magnetic recording devices, digital transmission devices, and the like. Further, as the plurality of M-sequence signals, not only signals having different phases are extracted from one M-sequence signal generation circuit 34, but also, for example, are extracted from a plurality of M-sequence signal generation circuits having different repetition periods, generator polynomials, and the like. It may be configured as follows.

[0033]

According to the M scrambling circuit of the present invention, a digital input signal is scrambled with a plurality of M sequence signals different from each other, and these scrambled generated sequences are converted into a plurality of precoders having latch means. The precoding is performed in the partial response class IV, and the optimum signal among the obtained precoding output signals is determined, and the optimum signal is selected and output. The identification information of the corresponding M-sequence signal, the error correction code of the identification information, and the adjustment bit for presetting the contents of the latch means in the precoder at the data head position of the synchronous block are recorded. Data is generated, the latch in the precoder is used at the start position of the synchronization block by the adjustment bit. It can be constant by presetting the data content of stages. As a result, the adaptive randomizer (M-scramble) method can be applied even when a magnetic recording / reproducing method having a precoder in the recording system is used as in the partial response class IV method, and the error rate can be improved.

[0034]

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a schematic configuration of a first embodiment of an M scramble circuit of the present invention.

FIG. 2 is a diagram showing a format of a recording signal in the embodiment.

FIG. 3 is a block circuit diagram showing a configuration example on the reproduction side corresponding to the M scramble circuit of the embodiment.

FIG. 4 is a block circuit diagram showing a schematic configuration of a second embodiment of the M scramble circuit of the present invention.

FIG. 5 is a diagram showing a format of a recording signal in the second embodiment.

FIG. 6 is a block circuit diagram illustrating a schematic configuration of an example of a conventional M scramble circuit.

FIG. 7 is a block circuit diagram showing a schematic configuration of a digital VTR.

FIG. 8 is a circuit diagram illustrating an example of a precoder.

[Explanation of symbols]

31 Data signal input terminals 32a to 32d Adder of mod2 (EX-OR
33) Reset signal input terminal 34 M-sequence signal generation circuit 35a to 35d Precoder 36a to 36d Buffer memory 37, 52 · Measurement circuit 38 ····· Changeover switch 39 ····· Recording data generation circuit 40 ····· Recording signal output terminal 51a to 51d ············· Identification information adding circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11B 20/14 G11B 20/10 H03M 13/00

Claims (1)

(57) [Claims] An M-sequence signal generating means for generating a plurality of M-sequence signals different from each other; a means for scrambling a digital input signal with each of the plurality of M-sequence signals; A plurality of precoders that precode in response class IV and have latching means; measuring means for measuring output signals from these precoders to determine an optimal signal; and, in accordance with an output signal from the measuring means. Switching selection means for switching and selecting an optimum signal among the output signals from the plurality of precoders; identification information of an M-sequence signal corresponding to the output signal from the switching selection means; A correction code,
By adding and said latch means for adjusting bit for presetting the data head position of the sync block contents in the precoder, and having a recording data generation means for generating recording data M Scramble circuit.