KR100262092B1 - Data converter in recording d-vhs system - Google Patents

Abstract

PURPOSE: A device for converting data in a recording process of a D-VHS(Digital-Video Home System) is provided to input parallel data to convert the parallel data into serial data in a record mode, and to perform a scrambling and a pre-coding process, so as to convert a data type into a data type appropriate for being stored in a tape. CONSTITUTION: A serial converter(10) converts 8-bit parallel data into serial data(11). A counter(20) generates a selection signal(21) indicating synchronization, ID, data and amble section. A data separator(30) separates the converted serial data(11) from the synchronization, the ID, the data and the amble section. An initial value setup unit(40) generates an initial value(41). A scrambler(50) receives data supplied to the data separator(30) on the basis of the selection signal(21) and the initial value(41), and generates a series of scramble data(51). The first data coupler(60) receives the scramble data(51), synchronous/ID data from the data separator(30), and the selection signal(21), and multiplexes the received data and the signal as a piece of data. A pre-coder(70) reverses the first data coupling signal(61) to pre-code the signal(61), and generates pre-coding data(71). The second data coupler(80) couples the pre-coding data(71) with amble data of the data separator(30) on the basis of the selection signal(21), and outputs final data(81).

Description

Data conversion apparatus at the time of recording of D-XHS system

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data conversion apparatus for recording a D-VHS system, and more particularly, to a data conversion apparatus for providing data for recording on a tape by receiving parallel data, performing a scrambling process and a pre-coding process.

Digital Video Home System (D-VHS) is a new digital data recording technology based on the Video Home System (VHS), one of the world's most popular home video formats. In April 1995, the technical standard of digital VHS Standard (STD) mode was completed through technical agreement between Hitachi, Matsushita Electric, and Philips. D-VHS not only performs existing VHS functions, but also records digital data transmitted through digital broadcasting such as DVB and DSS, and reproduces original data immediately before recording. Digital VHS is a bit stream recording / reproducing apparatus having a function of storing and outputting to tape without providing compressed or processed data. Digital VHS uses a generalized ferric oxide tape (S-VHS) to provide 7 hours for input data rates of 14.1 Mbps with high stability and price competitiveness, and 14 hours for 7 Mbps for long playback modes. Can be stored. It is a 44-gigabyte, suited-capacity, with very high recording density and price competitiveness compared to DVD, RAM, HDD, and Mo's DSM (Data Storage Media).

Applications include video servers, safety surveillance, data record storage media, and the like.

In other words, while the D-VHS system provides the features of the existing VHS, and to address the needs of multimedia applications, the new VHS technology provides a bitstream recording capability that allows the recording of compressed data such as digital broadcasting. . In other words, D-VHS can be used in new applications such as home digital data storage, which is expected in the future, by including most of the advantages of tape media, such as high capacity and low cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data conversion apparatus for converting data into a data format suitable for storage on a tape by receiving parallel data in record mode and converting the serial data into serial data in a D-VHS system. For the purpose of

1 is a block diagram showing a data conversion apparatus according to an embodiment of the present invention.

FIG. 2 illustrates a case where the scramble initial value of the scrambling part of FIG. 1 is a main code initial value.

FIG. 3 illustrates a case in which a scrambling initial value of the scrambling part of FIG. 1 is a sub code initial value.

4 is a detailed block diagram of the precoding unit of FIG. 1.

5 shows sync, ID, data, and amble sections constituting one track.

FIG. 6 is a diagram illustrating the main code data section of FIG. 5 in detail.

FIG. 7 is a diagram illustrating the sub code data section of FIG. 5 in detail.

8 shows a plurality of tracks recorded on a tape.

<Description of the code | symbol about the principal part of drawing>

10: serial converter 20: counter

30: data separator 40: initial value setting unit

50: scrambling unit 60: first data coupling unit

70: precoding unit 80: second data combining unit

In order to realize the object of the present invention, the present invention

A serial converter for converting parallel data into serial data; A counter unit for generating a selection signal; A data separator for separating the converted serial data into sync, ID, data and amble sections, respectively; An initial value setting unit for receiving an ID section generated from the data separation unit to generate an initial value; A scrambling unit for receiving a data signal provided to the data separation unit based on an initial value provided from the initial value setting unit and a selection signal provided from the counter to generate a series of scrambled data; A first data combiner configured to receive data scrambled from the scrambling unit, a synchronization signal from the data separating unit, an ID, and a selection signal from the counter to mux the data into one data; A pre-coding unit for generating pre-coded data by inverting and then pre-coding the signal supplied from the first data combiner; And a second data combiner configured to combine the precoded data provided to the precoding unit with the amble signal provided from the data separator and output a final data format based on the selection signal provided from the counter. Provide the device.

According to the above configuration, in the record mode, 8-bit parallel data is input and converted into serial data, followed by scrambling and pre-coding processing, and then outputting data in a form that can be stored on a tape.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention through an embodiment of the present invention.

1 is a block diagram showing a data conversion apparatus according to an embodiment of the present invention.

Referring to FIG. 1, the data converter includes a serial converter 10, a counter 20, a first data separator 30, an initial value setting unit 40, a scrambling unit 50, and first data. The combiner 60, the precoding unit 70, and the second data combiner 80 are configured.

The serial converter 10 provides the data separator 30 with the serial data 11 generated after converting the 8-bit parallel data based on the synchronization signal into serial data.

The counter unit 20 receives the selection signal 21 representing the synchronization, ID, data, and amble sections in the input data based on the synchronization signal, the data separator 30, the scrambling unit 50, and the first data. The combination unit 60, the precoding unit 70, and the second data combiner 80 are provided to each.

The data separator 30 separates the serial data 11 provided from the serial converter 10 into sync, ID, data, and amble sections based on the selection signal 21 provided from the counter 20. After that, the synchronization and ID are provided to the initial value setting unit 40 and the first data combiner 60, the data is provided to the scrambling unit 50, and the amble is provided to the second data combiner 80, respectively. do.

The initial value setting unit 40 receives the sync-ID signal from the data separator 30 and generates a new initial value 41 for each sync block SB and provides it to the scrambling unit 50.

The scrambling unit 50 is provided from the data separator 30 based on the initial value 41 provided from the initial value setting unit 40 and the selection signal 21 provided from the counter 20. The data is supplied to provide a series of scrambled data 51 to the first data combiner 60.

The first data combiner 60 receives the data 51 scrambled from the scrambling unit 50, the sync-ID signal from the data separation unit 30, and the selection signal 21 from the counter 20, respectively. The received data is combined with one data and provided to the precoding unit 70.

The precoding unit 70 inverts the signal 61 supplied from the first data combining unit 60 based on the selection signal 21 provided from the counter 20, and then precodes the precoding data ( 71) to the second data combiner 80. And

The second data combiner 80 precodes the data 71 provided to the precoding unit 70 and the data separator 30 based on the selection signal 21 provided from the counter 20. The final data format is output by combining the amble signals provided from the &lt; RTI ID = 0.0 &gt;

In the configuration of the above circuit, the scrambling process and the precoding process will be described in more detail.

The configuration of the scrambling unit 50 will be described with reference to FIG. 2.

The scrambling unit 50 includes 15 registers arranged in series (X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15), and a first summer 52 and the second summer 54.

The 15 registers arranged in series (X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15) store data input to the least significant bit (LSB). The buffering method sequentially moves to the most significant bit (MSB).

The first summer 52 passes the data from the least significant bit (LSB) register (X1) through the seventh register (X7) and the fifteenth register (X15) from the least significant bit (LSB) register (X1). One data is summed and returned to the register X1 of the least significant bit LSB, and the second summer 54 passes through the fifteenth register X15 from the least significant bit LSB register X1. And the data input from the data separator 30 are added up.

In this case, registers from the least significant bit (LSB) register (X1) to the ninth register (X9) represent a sync block number, and registers from the tenth register (X10) to the twelfth register (X12). Denotes a track pair number, and the thirteenth registers X13 to 15th registers X15 all represent '1'.

At this time, the raw polynomial of the scrambling unit 50 is P (X) = X ¹⁵⁺ X ⁷ +1 It can be represented as

In the case of the main code, the initial scrambling value of the scrambling unit 50 is (number of 9-bit sync blocks, number of track bits of 3 bits, 1, 1, 1) as shown in FIG. As shown in Fig. 3, (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1).

4 is a detailed block diagram of the precoding unit 70 of the present invention.

The precoding unit 70 includes an inverter 72, a first delayer 76, a second delayer 78, and a summer 74.

The inverter 72 inverts the data 61 input from the first data combiner 60 to provide an inverted signal 73 to the summer 74.

The first delay unit 76 provides the second delay unit 78 with the first delay signal 77 generated by delaying the inversion signal 73 for one period of the clock.

The second delayer 78 receives the first delayed signal 77 and delays it again for one period to generate a second delayed signal 79 and feeds it back to the summer 74.

Thereafter, the summer 74 receives the inversion signal 73 provided from the inverter 72 and the second delay signal 79 provided from the second delayer 78 to perform a sum operation, and then outputs an output terminal. Output through, and feedback to the first retarder (76).

Next, the structure of the 8-bit parallel data provided to the data separator 30 will be described in more detail.

FIG. 5 shows a sync block SB of each sync, ID, data, and amble section constituting one track.

One track as described above can be recorded on the tape as shown in FIG.

That is, one track has an amble with five sync blocks, sub code data with four sync blocks, an amble with seven sync blocks, and a main code with 336 sync blocks. The data is composed of an amble with four sync blocks, and there are a total of 356 sync blocks in one track. At this time, one sync block is 112 bytes.

In addition, as shown in FIG. 6, one sync block of main code data composed of a total of 336 sync blocks shown in FIG. 5 has a synchronization of 2 bytes, a first ID of 1 byte, a second ID of 1 byte, and a byte of 1 byte. The sub-code data consisting of the third ID parity, 99 bytes of main data, and 8 bytes of parity, and the four coded blocks of FIG. A first ID, a second ID of one byte, a third ID parity of one byte, a format ID of one byte, subdata of 19 bytes, and parity of four bytes.

According to the present invention described above, in the record mode of digital data in D-VHS, 8-bit parallel data is input and converted into serial data, followed by scrambling and pre-coding processing, and then the data is suitable for storage on a tape. You can output

As described above, the present invention, in the record mode of digital data in the D-VHS, receives 8-bit parallel data and converts the serial-converted signal into a synchronization, ID, data, and amble after converting the serial-converted signal into a serial data form using a serial converter. To perform data scrambling on the data among the separated signals, and then to resynchronize the synchronization and ID of the separated signals, and then perform precoding processing, and to convert the amble signal of the separated signals into the precoded signal. By combining, the data can be converted into a form that can be stored on a tape and output data in a form suitable for a record mode of a D-VHS system.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (5)

A serial converter 10 for converting input parallel data of 8 bits into serial data 11; A counter unit 20 for generating a selection signal 21 representing a synchronization, ID, data and amble section in the input data; A data separator 30 for separating the converted serial data 11 into sync, ID, data, and amble sections, respectively; An initial value setting unit 40 for receiving an synchronization period, an ID interval, a data interval, and an amble interval generated from the data separator 30 to generate an initial value 41; On the basis of the initial value 41 provided from the initial value setting unit 40 and the selection signal 21 provided from the counter 20, the data provided to the data separator 30 is scrambled. A scrambling unit 50 for generating data 51; First data for receiving the scrambled data 51 from the scrambling unit 50, the synchronization, ID data from the data separator 30, and the selection signal 21 from the counter 20 to be muxed into one piece of data. Coupling part 60; A pre-coding unit 70 for generating pre-coded data 71 by inverting and then pre-coding the first data combination signal 61 provided from the first data combiner 60; And On the basis of the selection signal 21 provided from the counter 20, the precoding data 71 provided to the precoding unit 70 and the amble data provided from the data separation unit 30 are combined. And a second data combiner (80) for outputting data (81). The method of claim 1, wherein the scrambling portion 50 15 registers (X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, etc.) for serially moving data input in the least significant bit in a buffered manner. X15); A first summer 52 for summing data passing through the seventh register (X7) from the least significant bit register and data passing through the fifteenth register (X15) from the least significant bit register to return to the least significant bit register; ; And And a second summer (54) for summing data passing through the fifteenth register (X15) from the least significant bit register and the data signal. The data conversion apparatus according to claim 1, wherein the main code initial value of the scrambling unit (50) comprises (9-bit sync block number, 3-bit track pair number, 1, 1, 1). According to claim 1, wherein the scrambling unit 50 is characterized in that the sub-code initial value is (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1) Data inverter The method of claim 1, wherein the precoding unit 70 An inverter 72 for inverting the input data; A first delay unit (76) for delaying the inverted signal for a predetermined time T; A second delay unit (78) for generating a 2T delay signal by delaying the signal delayed for the T time again for a predetermined time T; And And a summer (74) for summing the 2T delay signal and the inverted signal.

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